From 0c42f9a5b29d8c56ea27b89a704bc300c95d0846 Mon Sep 17 00:00:00 2001 From: "evangelos.ganotopoulos@arm.com" Date: Mon, 2 Sep 2024 11:27:24 +0200 Subject: [PATCH 1/4] Remove --update-rte to ensure support reproducible builds. Added files and folders located in RTE directory. Added Hello.cbuild-pack.yml. --- .github/workflows/hello-ci.yml | 2 +- Hello.cbuild-pack.yml | 29 + RTE/CMSIS/RTX_Config.c | 67 ++ RTE/CMSIS/RTX_Config.c.base@5.2.0 | 67 ++ RTE/CMSIS/RTX_Config.h.base@5.6.0 | 663 ++++++++++++++++++ .../CMSDK_CM0_VHT/RTE_Device.h.base@1.0.0 | 50 ++ RTE/Device/CMSDK_CM0_VHT/ac6_arm.sct | 76 ++ .../CMSDK_CM0_VHT/ac6_arm.sct.base@1.0.0 | 76 ++ RTE/Device/CMSDK_CM0_VHT/gcc_arm.ld | 277 ++++++++ .../CMSDK_CM0_VHT/gcc_arm.ld.base@1.1.0 | 277 ++++++++ RTE/Device/CMSDK_CM0_VHT/startup_CMSDK_CM0.c | 218 ++++++ .../startup_CMSDK_CM0.c.base@1.1.0 | 218 ++++++ RTE/Device/CMSDK_CM0_VHT/system_CMSDK_CM0.c | 71 ++ .../system_CMSDK_CM0.c.base@1.1.0 | 71 ++ .../CMSDK_CM0plus_VHT/RTE_Device.h.base@1.0.0 | 50 ++ RTE/Device/CMSDK_CM0plus_VHT/ac6_arm.sct | 76 ++ .../CMSDK_CM0plus_VHT/ac6_arm.sct.base@1.0.0 | 76 ++ RTE/Device/CMSDK_CM0plus_VHT/gcc_arm.ld | 277 ++++++++ .../CMSDK_CM0plus_VHT/gcc_arm.ld.base@1.1.0 | 277 ++++++++ .../CMSDK_CM0plus_VHT/startup_CMSDK_CM0plus.c | 218 ++++++ .../startup_CMSDK_CM0plus.c.base@1.1.0 | 218 ++++++ .../CMSDK_CM0plus_VHT/system_CMSDK_CM0plus.c | 74 ++ .../system_CMSDK_CM0plus.c.base@1.1.0 | 74 ++ .../CMSDK_CM3_VHT/RTE_Device.h.base@1.0.0 | 50 ++ RTE/Device/CMSDK_CM3_VHT/ac6_arm.sct | 76 ++ .../CMSDK_CM3_VHT/ac6_arm.sct.base@1.0.0 | 76 ++ RTE/Device/CMSDK_CM3_VHT/gcc_arm.ld | 277 ++++++++ .../CMSDK_CM3_VHT/gcc_arm.ld.base@1.1.0 | 277 ++++++++ RTE/Device/CMSDK_CM3_VHT/startup_CMSDK_CM3.c | 421 +++++++++++ .../startup_CMSDK_CM3.c.base@1.1.0 | 421 +++++++++++ RTE/Device/CMSDK_CM3_VHT/system_CMSDK_CM3.c | 78 +++ .../system_CMSDK_CM3.c.base@1.1.0 | 78 +++ .../CMSDK_CM4_FP_VHT/RTE_Device.h.base@1.0.0 | 50 ++ RTE/Device/CMSDK_CM4_FP_VHT/ac6_arm.sct | 76 ++ .../CMSDK_CM4_FP_VHT/ac6_arm.sct.base@1.0.0 | 76 ++ RTE/Device/CMSDK_CM4_FP_VHT/gcc_arm.ld | 277 ++++++++ .../CMSDK_CM4_FP_VHT/gcc_arm.ld.base@1.1.0 | 277 ++++++++ .../CMSDK_CM4_FP_VHT/startup_CMSDK_CM4.c | 423 +++++++++++ .../startup_CMSDK_CM4.c.base@1.1.0 | 423 +++++++++++ .../CMSDK_CM4_FP_VHT/system_CMSDK_CM4.c | 85 +++ .../system_CMSDK_CM4.c.base@1.1.0 | 85 +++ .../CMSDK_CM4_VHT/RTE_Device.h.base@1.0.0 | 50 ++ RTE/Device/CMSDK_CM4_VHT/ac6_arm.sct | 76 ++ .../CMSDK_CM4_VHT/ac6_arm.sct.base@1.0.0 | 76 ++ RTE/Device/CMSDK_CM4_VHT/gcc_arm.ld | 277 ++++++++ .../CMSDK_CM4_VHT/gcc_arm.ld.base@1.1.0 | 277 ++++++++ RTE/Device/CMSDK_CM4_VHT/startup_CMSDK_CM4.c | 423 +++++++++++ .../startup_CMSDK_CM4.c.base@1.1.0 | 423 +++++++++++ RTE/Device/CMSDK_CM4_VHT/system_CMSDK_CM4.c | 85 +++ .../system_CMSDK_CM4.c.base@1.1.0 | 85 +++ .../CMSDK_CM7_DP_VHT/RTE_Device.h.base@1.0.0 | 50 ++ RTE/Device/CMSDK_CM7_DP_VHT/ac6_arm.sct | 76 ++ .../CMSDK_CM7_DP_VHT/ac6_arm.sct.base@1.0.0 | 76 ++ .../CMSDK_CM7_DP_VHT/startup_CMSDK_CM7.c | 425 +++++++++++ .../startup_CMSDK_CM7.c.base@1.1.0 | 425 +++++++++++ .../CMSDK_CM7_DP_VHT/system_CMSDK_CM7.c | 87 +++ .../system_CMSDK_CM7.c.base@1.1.0 | 87 +++ .../CMSDK_CM7_SP_VHT/RTE_Device.h.base@1.0.0 | 50 ++ RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct | 76 ++ .../CMSDK_CM7_SP_VHT/ac6_arm.sct.base@1.0.0 | 76 ++ .../CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c | 425 +++++++++++ .../startup_CMSDK_CM7.c.base@1.1.0 | 425 +++++++++++ .../CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c | 87 +++ .../system_CMSDK_CM7.c.base@1.1.0 | 87 +++ .../CMSDK_CM7_VHT/RTE_Device.h.base@1.0.0 | 50 ++ RTE/Device/CMSDK_CM7_VHT/ac6_arm.sct | 76 ++ .../CMSDK_CM7_VHT/ac6_arm.sct.base@1.0.0 | 76 ++ RTE/Device/CMSDK_CM7_VHT/gcc_arm.ld | 277 ++++++++ .../CMSDK_CM7_VHT/gcc_arm.ld.base@1.1.0 | 277 ++++++++ RTE/Device/CMSDK_CM7_VHT/startup_CMSDK_CM7.c | 425 +++++++++++ .../startup_CMSDK_CM7.c.base@1.1.0 | 425 +++++++++++ RTE/Device/CMSDK_CM7_VHT/system_CMSDK_CM7.c | 87 +++ .../system_CMSDK_CM7.c.base@1.1.0 | 87 +++ .../IOTKit_CM23_VHT/RTE_Device.h.base@1.0.0 | 50 ++ RTE/Device/IOTKit_CM23_VHT/ac6_arm.sct | 119 ++++ .../IOTKit_CM23_VHT/ac6_arm.sct.base@1.0.0 | 119 ++++ .../IOTKit_CM23_VHT/partition_IOTKit_CM23.h | 585 ++++++++++++++++ .../partition_IOTKit_CM23.h.base@1.0.0 | 585 ++++++++++++++++ .../IOTKit_CM23_VHT/startup_IOTKit_CM23.c | 506 +++++++++++++ .../startup_IOTKit_CM23.c.base@1.2.0 | 506 +++++++++++++ .../IOTKit_CM23_VHT/system_IOTKit_CM23.c | 132 ++++ .../system_IOTKit_CM23.c.base@1.2.0 | 132 ++++ .../RTE_Device.h.base@1.0.0 | 50 ++ RTE/Device/IOTKit_CM33_FP_VHT/ac6_arm.sct | 119 ++++ .../IOTKit_CM33_FP_VHT/ac6_arm.sct.base@1.0.0 | 119 ++++ .../partition_IOTKit_CM33.h | 637 +++++++++++++++++ .../partition_IOTKit_CM33.h.base@1.0.0 | 637 +++++++++++++++++ .../IOTKit_CM33_FP_VHT/startup_IOTKit_CM33.c | 513 ++++++++++++++ .../startup_IOTKit_CM33.c.base@1.2.0 | 513 ++++++++++++++ .../IOTKit_CM33_FP_VHT/system_IOTKit_CM33.c | 149 ++++ .../system_IOTKit_CM33.c.base@1.2.0 | 149 ++++ .../IOTKit_CM33_VHT/RTE_Device.h.base@1.0.0 | 50 ++ RTE/Device/IOTKit_CM33_VHT/ac6_arm.sct | 119 ++++ .../IOTKit_CM33_VHT/ac6_arm.sct.base@1.0.0 | 119 ++++ .../IOTKit_CM33_VHT/partition_IOTKit_CM33.h | 637 +++++++++++++++++ .../partition_IOTKit_CM33.h.base@1.0.0 | 637 +++++++++++++++++ .../IOTKit_CM33_VHT/startup_IOTKit_CM33.c | 513 ++++++++++++++ .../startup_IOTKit_CM33.c.base@1.2.0 | 513 ++++++++++++++ .../IOTKit_CM33_VHT/system_IOTKit_CM33.c | 149 ++++ .../system_IOTKit_CM33.c.base@1.2.0 | 149 ++++ .../SSE-300-MPS3/ac6_linker_script.sct.src | 109 +++ RTE/Device/SSE-300-MPS3/device_cfg.h | 148 ++++ .../SSE-300-MPS3/device_cfg.h.base@1.1.4 | 148 ++++ .../SSE-300-MPS3/regions_SSE-300-MPS3.h | 366 ++++++++++ RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c | 487 +++++++++++++ .../startup_SSE300MPS3.c.base@1.1.1 | 487 +++++++++++++ RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c | 105 +++ .../system_SSE300MPS3.c.base@1.1.1 | 105 +++ .../ac6_linker_script.sct.src | 109 +++ RTE/Device/SSE-310-MPS3_FVP/device_cfg.h | 219 ++++++ .../SSE-310-MPS3_FVP/device_cfg.h.base@1.1.0 | 219 ++++++ .../regions_SSE-310-MPS3_FVP.h | 366 ++++++++++ .../SSE-310-MPS3_FVP/startup_SSE310MPS3.c | 493 +++++++++++++ .../startup_SSE310MPS3.c.base@1.1.0 | 493 +++++++++++++ .../SSE-310-MPS3_FVP/system_SSE310MPS3.c | 107 +++ .../system_SSE310MPS3.c.base@1.1.0 | 107 +++ .../SSE-315-FVP/ac6_linker_script.sct.src | 109 +++ RTE/Device/SSE-315-FVP/device_cfg.h | 275 ++++++++ .../SSE-315-FVP/device_cfg.h.base@1.1.0 | 275 ++++++++ RTE/Device/SSE-315-FVP/regions_SSE-315-FVP.h | 366 ++++++++++ RTE/Device/SSE-315-FVP/startup_SSE315.c | 410 +++++++++++ .../SSE-315-FVP/startup_SSE315.c.base@1.1.0 | 410 +++++++++++ RTE/Device/SSE-315-FVP/system_SSE315.c | 107 +++ .../SSE-315-FVP/system_SSE315.c.base@1.1.0 | 107 +++ RTE/_Debug_CM0/RTE_Components.h | 35 + RTE/_Debug_CM0plus/RTE_Components.h | 35 + RTE/_Debug_CM23/RTE_Components.h | 35 + RTE/_Debug_CM3/RTE_Components.h | 35 + RTE/_Debug_CM33/RTE_Components.h | 35 + RTE/_Debug_CM33_FP/RTE_Components.h | 35 + RTE/_Debug_CM4/RTE_Components.h | 35 + RTE/_Debug_CM4_FP/RTE_Components.h | 35 + RTE/_Debug_CM7/RTE_Components.h | 35 + RTE/_Debug_CM7_DP/RTE_Components.h | 35 + RTE/_Debug_CM7_SP/RTE_Components.h | 35 + RTE/_Debug_CS300/RTE_Components.h | 42 ++ RTE/_Debug_CS310/RTE_Components.h | 42 ++ RTE/_Debug_CS315/RTE_Components.h | 42 ++ RTE/_Release_CM0/RTE_Components.h | 35 + RTE/_Release_CM0plus/RTE_Components.h | 35 + RTE/_Release_CM23/RTE_Components.h | 35 + RTE/_Release_CM3/RTE_Components.h | 35 + RTE/_Release_CM33/RTE_Components.h | 35 + RTE/_Release_CM33_FP/RTE_Components.h | 35 + RTE/_Release_CM4/RTE_Components.h | 35 + RTE/_Release_CM4_FP/RTE_Components.h | 35 + RTE/_Release_CM7/RTE_Components.h | 35 + RTE/_Release_CM7_DP/RTE_Components.h | 35 + RTE/_Release_CM7_SP/RTE_Components.h | 35 + RTE/_Release_CS300/RTE_Components.h | 42 ++ RTE/_Release_CS310/RTE_Components.h | 42 ++ RTE/_Release_CS315/RTE_Components.h | 42 ++ 152 files changed, 28686 insertions(+), 1 deletion(-) create mode 100644 Hello.cbuild-pack.yml create mode 100644 RTE/CMSIS/RTX_Config.c create mode 100644 RTE/CMSIS/RTX_Config.c.base@5.2.0 create mode 100644 RTE/CMSIS/RTX_Config.h.base@5.6.0 create mode 100644 RTE/Device/CMSDK_CM0_VHT/RTE_Device.h.base@1.0.0 create mode 100644 RTE/Device/CMSDK_CM0_VHT/ac6_arm.sct create mode 100644 RTE/Device/CMSDK_CM0_VHT/ac6_arm.sct.base@1.0.0 create mode 100644 RTE/Device/CMSDK_CM0_VHT/gcc_arm.ld create mode 100644 RTE/Device/CMSDK_CM0_VHT/gcc_arm.ld.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM0_VHT/startup_CMSDK_CM0.c create mode 100644 RTE/Device/CMSDK_CM0_VHT/startup_CMSDK_CM0.c.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM0_VHT/system_CMSDK_CM0.c create mode 100644 RTE/Device/CMSDK_CM0_VHT/system_CMSDK_CM0.c.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM0plus_VHT/RTE_Device.h.base@1.0.0 create mode 100644 RTE/Device/CMSDK_CM0plus_VHT/ac6_arm.sct create mode 100644 RTE/Device/CMSDK_CM0plus_VHT/ac6_arm.sct.base@1.0.0 create mode 100644 RTE/Device/CMSDK_CM0plus_VHT/gcc_arm.ld create mode 100644 RTE/Device/CMSDK_CM0plus_VHT/gcc_arm.ld.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM0plus_VHT/startup_CMSDK_CM0plus.c create mode 100644 RTE/Device/CMSDK_CM0plus_VHT/startup_CMSDK_CM0plus.c.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM0plus_VHT/system_CMSDK_CM0plus.c create mode 100644 RTE/Device/CMSDK_CM0plus_VHT/system_CMSDK_CM0plus.c.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM3_VHT/RTE_Device.h.base@1.0.0 create mode 100644 RTE/Device/CMSDK_CM3_VHT/ac6_arm.sct create mode 100644 RTE/Device/CMSDK_CM3_VHT/ac6_arm.sct.base@1.0.0 create mode 100644 RTE/Device/CMSDK_CM3_VHT/gcc_arm.ld create mode 100644 RTE/Device/CMSDK_CM3_VHT/gcc_arm.ld.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM3_VHT/startup_CMSDK_CM3.c create mode 100644 RTE/Device/CMSDK_CM3_VHT/startup_CMSDK_CM3.c.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM3_VHT/system_CMSDK_CM3.c create mode 100644 RTE/Device/CMSDK_CM3_VHT/system_CMSDK_CM3.c.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM4_FP_VHT/RTE_Device.h.base@1.0.0 create mode 100644 RTE/Device/CMSDK_CM4_FP_VHT/ac6_arm.sct create mode 100644 RTE/Device/CMSDK_CM4_FP_VHT/ac6_arm.sct.base@1.0.0 create mode 100644 RTE/Device/CMSDK_CM4_FP_VHT/gcc_arm.ld create mode 100644 RTE/Device/CMSDK_CM4_FP_VHT/gcc_arm.ld.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM4_FP_VHT/startup_CMSDK_CM4.c create mode 100644 RTE/Device/CMSDK_CM4_FP_VHT/startup_CMSDK_CM4.c.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM4_FP_VHT/system_CMSDK_CM4.c create mode 100644 RTE/Device/CMSDK_CM4_FP_VHT/system_CMSDK_CM4.c.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM4_VHT/RTE_Device.h.base@1.0.0 create mode 100644 RTE/Device/CMSDK_CM4_VHT/ac6_arm.sct create mode 100644 RTE/Device/CMSDK_CM4_VHT/ac6_arm.sct.base@1.0.0 create mode 100644 RTE/Device/CMSDK_CM4_VHT/gcc_arm.ld create mode 100644 RTE/Device/CMSDK_CM4_VHT/gcc_arm.ld.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM4_VHT/startup_CMSDK_CM4.c create mode 100644 RTE/Device/CMSDK_CM4_VHT/startup_CMSDK_CM4.c.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM4_VHT/system_CMSDK_CM4.c create mode 100644 RTE/Device/CMSDK_CM4_VHT/system_CMSDK_CM4.c.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM7_DP_VHT/RTE_Device.h.base@1.0.0 create mode 100644 RTE/Device/CMSDK_CM7_DP_VHT/ac6_arm.sct create mode 100644 RTE/Device/CMSDK_CM7_DP_VHT/ac6_arm.sct.base@1.0.0 create mode 100644 RTE/Device/CMSDK_CM7_DP_VHT/startup_CMSDK_CM7.c create mode 100644 RTE/Device/CMSDK_CM7_DP_VHT/startup_CMSDK_CM7.c.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM7_DP_VHT/system_CMSDK_CM7.c create mode 100644 RTE/Device/CMSDK_CM7_DP_VHT/system_CMSDK_CM7.c.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM7_SP_VHT/RTE_Device.h.base@1.0.0 create mode 100644 RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct create mode 100644 RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct.base@1.0.0 create mode 100644 RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c create mode 100644 RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c create mode 100644 RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM7_VHT/RTE_Device.h.base@1.0.0 create mode 100644 RTE/Device/CMSDK_CM7_VHT/ac6_arm.sct create mode 100644 RTE/Device/CMSDK_CM7_VHT/ac6_arm.sct.base@1.0.0 create mode 100644 RTE/Device/CMSDK_CM7_VHT/gcc_arm.ld create mode 100644 RTE/Device/CMSDK_CM7_VHT/gcc_arm.ld.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM7_VHT/startup_CMSDK_CM7.c create mode 100644 RTE/Device/CMSDK_CM7_VHT/startup_CMSDK_CM7.c.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM7_VHT/system_CMSDK_CM7.c create mode 100644 RTE/Device/CMSDK_CM7_VHT/system_CMSDK_CM7.c.base@1.1.0 create mode 100644 RTE/Device/IOTKit_CM23_VHT/RTE_Device.h.base@1.0.0 create mode 100644 RTE/Device/IOTKit_CM23_VHT/ac6_arm.sct create mode 100644 RTE/Device/IOTKit_CM23_VHT/ac6_arm.sct.base@1.0.0 create mode 100644 RTE/Device/IOTKit_CM23_VHT/partition_IOTKit_CM23.h create mode 100644 RTE/Device/IOTKit_CM23_VHT/partition_IOTKit_CM23.h.base@1.0.0 create mode 100644 RTE/Device/IOTKit_CM23_VHT/startup_IOTKit_CM23.c create mode 100644 RTE/Device/IOTKit_CM23_VHT/startup_IOTKit_CM23.c.base@1.2.0 create mode 100644 RTE/Device/IOTKit_CM23_VHT/system_IOTKit_CM23.c create mode 100644 RTE/Device/IOTKit_CM23_VHT/system_IOTKit_CM23.c.base@1.2.0 create mode 100644 RTE/Device/IOTKit_CM33_FP_VHT/RTE_Device.h.base@1.0.0 create mode 100644 RTE/Device/IOTKit_CM33_FP_VHT/ac6_arm.sct create mode 100644 RTE/Device/IOTKit_CM33_FP_VHT/ac6_arm.sct.base@1.0.0 create mode 100644 RTE/Device/IOTKit_CM33_FP_VHT/partition_IOTKit_CM33.h create mode 100644 RTE/Device/IOTKit_CM33_FP_VHT/partition_IOTKit_CM33.h.base@1.0.0 create mode 100644 RTE/Device/IOTKit_CM33_FP_VHT/startup_IOTKit_CM33.c create mode 100644 RTE/Device/IOTKit_CM33_FP_VHT/startup_IOTKit_CM33.c.base@1.2.0 create mode 100644 RTE/Device/IOTKit_CM33_FP_VHT/system_IOTKit_CM33.c create mode 100644 RTE/Device/IOTKit_CM33_FP_VHT/system_IOTKit_CM33.c.base@1.2.0 create mode 100644 RTE/Device/IOTKit_CM33_VHT/RTE_Device.h.base@1.0.0 create mode 100644 RTE/Device/IOTKit_CM33_VHT/ac6_arm.sct create mode 100644 RTE/Device/IOTKit_CM33_VHT/ac6_arm.sct.base@1.0.0 create mode 100644 RTE/Device/IOTKit_CM33_VHT/partition_IOTKit_CM33.h create mode 100644 RTE/Device/IOTKit_CM33_VHT/partition_IOTKit_CM33.h.base@1.0.0 create mode 100644 RTE/Device/IOTKit_CM33_VHT/startup_IOTKit_CM33.c create mode 100644 RTE/Device/IOTKit_CM33_VHT/startup_IOTKit_CM33.c.base@1.2.0 create mode 100644 RTE/Device/IOTKit_CM33_VHT/system_IOTKit_CM33.c create mode 100644 RTE/Device/IOTKit_CM33_VHT/system_IOTKit_CM33.c.base@1.2.0 create mode 100644 RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src create mode 100644 RTE/Device/SSE-300-MPS3/device_cfg.h create mode 100644 RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.4 create mode 100644 RTE/Device/SSE-300-MPS3/regions_SSE-300-MPS3.h create mode 100644 RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c create mode 100644 RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 create mode 100644 RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c create mode 100644 RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 create mode 100644 RTE/Device/SSE-310-MPS3_FVP/ac6_linker_script.sct.src create mode 100644 RTE/Device/SSE-310-MPS3_FVP/device_cfg.h create mode 100644 RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.1.0 create mode 100644 RTE/Device/SSE-310-MPS3_FVP/regions_SSE-310-MPS3_FVP.h create mode 100644 RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c create mode 100644 RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 create mode 100644 RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c create mode 100644 RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 create mode 100644 RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src create mode 100644 RTE/Device/SSE-315-FVP/device_cfg.h create mode 100644 RTE/Device/SSE-315-FVP/device_cfg.h.base@1.1.0 create mode 100644 RTE/Device/SSE-315-FVP/regions_SSE-315-FVP.h create mode 100644 RTE/Device/SSE-315-FVP/startup_SSE315.c create mode 100644 RTE/Device/SSE-315-FVP/startup_SSE315.c.base@1.1.0 create mode 100644 RTE/Device/SSE-315-FVP/system_SSE315.c create mode 100644 RTE/Device/SSE-315-FVP/system_SSE315.c.base@1.1.0 create mode 100644 RTE/_Debug_CM0/RTE_Components.h create mode 100644 RTE/_Debug_CM0plus/RTE_Components.h create mode 100644 RTE/_Debug_CM23/RTE_Components.h create mode 100644 RTE/_Debug_CM3/RTE_Components.h create mode 100644 RTE/_Debug_CM33/RTE_Components.h create mode 100644 RTE/_Debug_CM33_FP/RTE_Components.h create mode 100644 RTE/_Debug_CM4/RTE_Components.h create mode 100644 RTE/_Debug_CM4_FP/RTE_Components.h create mode 100644 RTE/_Debug_CM7/RTE_Components.h create mode 100644 RTE/_Debug_CM7_DP/RTE_Components.h create mode 100644 RTE/_Debug_CM7_SP/RTE_Components.h create mode 100644 RTE/_Debug_CS300/RTE_Components.h create mode 100644 RTE/_Debug_CS310/RTE_Components.h create mode 100644 RTE/_Debug_CS315/RTE_Components.h create mode 100644 RTE/_Release_CM0/RTE_Components.h create mode 100644 RTE/_Release_CM0plus/RTE_Components.h create mode 100644 RTE/_Release_CM23/RTE_Components.h create mode 100644 RTE/_Release_CM3/RTE_Components.h create mode 100644 RTE/_Release_CM33/RTE_Components.h create mode 100644 RTE/_Release_CM33_FP/RTE_Components.h create mode 100644 RTE/_Release_CM4/RTE_Components.h create mode 100644 RTE/_Release_CM4_FP/RTE_Components.h create mode 100644 RTE/_Release_CM7/RTE_Components.h create mode 100644 RTE/_Release_CM7_DP/RTE_Components.h create mode 100644 RTE/_Release_CM7_SP/RTE_Components.h create mode 100644 RTE/_Release_CS300/RTE_Components.h create mode 100644 RTE/_Release_CS310/RTE_Components.h create mode 100644 RTE/_Release_CS315/RTE_Components.h diff --git a/.github/workflows/hello-ci.yml b/.github/workflows/hello-ci.yml index a47a4b2..8609245 100644 --- a/.github/workflows/hello-ci.yml +++ b/.github/workflows/hello-ci.yml @@ -59,7 +59,7 @@ jobs: - name: Build context Hello.${{ matrix.build.type }}+${{ matrix.target.type }} with ${{ matrix.compiler.name }} working-directory: ./ run: | - cbuild Hello.csolution.yml --update-rte --packs \ + cbuild Hello.csolution.yml --packs \ --context Hello.${{ matrix.build.type }}+${{ matrix.target.type }} \ --toolchain ${{ matrix.compiler.name }} --rebuild diff --git a/Hello.cbuild-pack.yml b/Hello.cbuild-pack.yml new file mode 100644 index 0000000..8a86183 --- /dev/null +++ b/Hello.cbuild-pack.yml @@ -0,0 +1,29 @@ +cbuild-pack: + resolved-packs: + - resolved-pack: ARM::CMSIS@6.1.0 + selected-by-pack: + - ARM::CMSIS + - resolved-pack: ARM::CMSIS-Compiler@2.1.0 + selected-by-pack: + - ARM::CMSIS-Compiler + - resolved-pack: ARM::CMSIS-RTX@5.9.0 + selected-by-pack: + - ARM::CMSIS-RTX + - resolved-pack: ARM::SSE_315_BSP@1.0.0 + selected-by-pack: + - ARM::SSE_315_BSP + - resolved-pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 + selected-by-pack: + - ARM::V2M_MPS3_SSE_300_BSP + - resolved-pack: ARM::V2M_MPS3_SSE_310_BSP@1.4.0 + selected-by-pack: + - ARM::V2M_MPS3_SSE_310_BSP + - resolved-pack: Keil::V2M-MPS2_CMx_BSP@1.8.2 + selected-by-pack: + - Keil::V2M-MPS2_CMx_BSP + - resolved-pack: Keil::V2M-MPS2_IOTKit_BSP@1.5.2 + selected-by-pack: + - Keil::V2M-MPS2_IOTKit_BSP + - resolved-pack: Keil::V2M-MPS3_IOTKit_BSP@1.0.2 + selected-by-pack: + - Keil::V2M-MPS3_IOTKit_BSP diff --git a/RTE/CMSIS/RTX_Config.c b/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..d21fa0a --- /dev/null +++ b/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2013-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.2.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackOverflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + case osRtxErrorSVC: + // Invalid SVC function called (function=object_id) + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/RTE/CMSIS/RTX_Config.c.base@5.2.0 b/RTE/CMSIS/RTX_Config.c.base@5.2.0 new file mode 100644 index 0000000..d21fa0a --- /dev/null +++ b/RTE/CMSIS/RTX_Config.c.base@5.2.0 @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2013-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.2.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackOverflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + case osRtxErrorSVC: + // Invalid SVC function called (function=object_id) + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/RTE/CMSIS/RTX_Config.h.base@5.6.0 b/RTE/CMSIS/RTX_Config.h.base@5.6.0 new file mode 100644 index 0000000..fe0c57b --- /dev/null +++ b/RTE/CMSIS/RTX_Config.h.base@5.6.0 @@ -0,0 +1,663 @@ +/* + * Copyright (c) 2013-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.6.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 32768 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 32768 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// Safety features (Source variant only) +// Enables FuSa related features. +// Requires RTX Source variant. +// Enables: +// - selected features from this group +// - Thread functions: osThreadProtectPrivileged +#ifndef OS_SAFETY_FEATURES +#define OS_SAFETY_FEATURES 0 +#endif + +// Safety Class +// Threads assigned to lower classes cannot modify higher class threads. +// Enables: +// - Object attributes: osSafetyClass +// - Kernel functions: osKernelProtect, osKernelDestroyClass +// - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass +#ifndef OS_SAFETY_CLASS +#define OS_SAFETY_CLASS 1 +#endif + +// MPU Protected Zone +// Access protection via MPU (Spatial isolation). +// Enables: +// - Thread attributes: osThreadZone +// - Thread functions: osThreadGetZone, osThreadTerminateZone +// - Zone Management: osZoneSetup_Callback +#ifndef OS_EXECUTION_ZONE +#define OS_EXECUTION_ZONE 1 +#endif + +// Thread Watchdog +// Watchdog alerts ensure timing for critical threads (Temporal isolation). +// Enables: +// - Thread functions: osThreadFeedWatchdog +// - Handler functions: osWatchdogAlarm_Handler +#ifndef OS_THREAD_WATCHDOG +#define OS_THREAD_WATCHDOG 1 +#endif + +// Object Pointer checking +// Check object pointer alignment and memory region. +#ifndef OS_OBJ_PTR_CHECK +#define OS_OBJ_PTR_CHECK 0 +#endif + +// SVC Function Pointer checking +// Check SVC function pointer alignment and memory region. +// User needs to define a linker execution region RTX_SVC_VENEERS +// containing input sections: rtx_*.o (.text.os.svc.veneer.*) +#ifndef OS_SVC_PTR_CHECK +#define OS_SVC_PTR_CHECK 0 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 3072 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 3072 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 512 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Idle Thread Safety Class <0-15> +// Defines the Safety Class number. +// Default: 0 +#ifndef OS_IDLE_THREAD_CLASS +#define OS_IDLE_THREAD_CLASS 0 +#endif + +// Idle Thread Zone <0-127> +// Defines Thread Zone. +// Default: 0 +#ifndef OS_IDLE_THREAD_ZONE +#define OS_IDLE_THREAD_ZONE 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch (requires RTX source variant). +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Default Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Unprivileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 0 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 512 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 512 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Thread Safety Class <0-15> +// Defines the Safety Class number. +// Default: 0 +#ifndef OS_TIMER_THREAD_CLASS +#define OS_TIMER_THREAD_CLASS 0 +#endif + +// Timer Thread Zone <0-127> +// Defines Thread Zone. +// Default: 0 +#ifndef OS_TIMER_THREAD_ZONE +#define OS_TIMER_THREAD_ZONE 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x81U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x81U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x85U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x81U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x81U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x81U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x81U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x81U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x81U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x81U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#ifndef OS_THREAD_LIBSPACE_NUM +#define OS_THREAD_LIBSPACE_NUM 4 +#endif +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/RTE/Device/CMSDK_CM0_VHT/RTE_Device.h.base@1.0.0 b/RTE/Device/CMSDK_CM0_VHT/RTE_Device.h.base@1.0.0 new file mode 100644 index 0000000..786b74f --- /dev/null +++ b/RTE/Device/CMSDK_CM0_VHT/RTE_Device.h.base@1.0.0 @@ -0,0 +1,50 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 25. April 2016 + * $Revision: V1.0.0 + * + * Project: RTE Device Configuration for ARM CMSDK_CM device + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_USART0 0 + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_UART2 0 + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_UART3 0 + +#endif /* __RTE_DEVICE_H */ diff --git a/RTE/Device/CMSDK_CM0_VHT/ac6_arm.sct b/RTE/Device/CMSDK_CM0_VHT/ac6_arm.sct new file mode 100644 index 0000000..d89c8d7 --- /dev/null +++ b/RTE/Device/CMSDK_CM0_VHT/ac6_arm.sct @@ -0,0 +1,76 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/RTE/Device/CMSDK_CM0_VHT/ac6_arm.sct.base@1.0.0 b/RTE/Device/CMSDK_CM0_VHT/ac6_arm.sct.base@1.0.0 new file mode 100644 index 0000000..d89c8d7 --- /dev/null +++ b/RTE/Device/CMSDK_CM0_VHT/ac6_arm.sct.base@1.0.0 @@ -0,0 +1,76 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/RTE/Device/CMSDK_CM0_VHT/gcc_arm.ld b/RTE/Device/CMSDK_CM0_VHT/gcc_arm.ld new file mode 100644 index 0000000..aa2735f --- /dev/null +++ b/RTE/Device/CMSDK_CM0_VHT/gcc_arm.ld @@ -0,0 +1,277 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/CMSDK_CM0_VHT/gcc_arm.ld.base@1.1.0 b/RTE/Device/CMSDK_CM0_VHT/gcc_arm.ld.base@1.1.0 new file mode 100644 index 0000000..aa2735f --- /dev/null +++ b/RTE/Device/CMSDK_CM0_VHT/gcc_arm.ld.base@1.1.0 @@ -0,0 +1,277 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/CMSDK_CM0_VHT/startup_CMSDK_CM0.c b/RTE/Device/CMSDK_CM0_VHT/startup_CMSDK_CM0.c new file mode 100644 index 0000000..cb505f7 --- /dev/null +++ b/RTE/Device/CMSDK_CM0_VHT/startup_CMSDK_CM0.c @@ -0,0 +1,218 @@ +/****************************************************************************** + * @file startup_CMSDK_CM0.c + * @brief CMSIS Startup File for CMSDK_M0 Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM0) || defined (CMSDK_CM0_VHT) + #include "CMSDK_CM0.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM0_VHT /* VSI Interrupts */ +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#else +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + UART0RX_Handler, /* 0 UART 0 receive interrupt */ + UART0TX_Handler, /* 1 UART 0 transmit interrupt */ + UART1RX_Handler, /* 2 UART 1 receive interrupt */ + UART1TX_Handler, /* 3 UART 1 transmit interrupt */ + UART2RX_Handler, /* 4 UART 2 receive interrupt */ + UART2TX_Handler, /* 5 UART 2 transmit interrupt */ + GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ + GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ + TIMER0_Handler, /* 8 Timer 0 interrupt */ + TIMER1_Handler, /* 9 Timer 1 interrupt */ + DUALTIMER_Handler, /* 10 Dual Timer interrupt */ + SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ + ETHERNET_Handler, /* 13 Ethernet interrupt */ + I2S_Handler, /* 14 Audio I2S interrupt */ + TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ + GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ + GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ + UART3RX_Handler, /* 18 UART 3 receive interrupt */ + UART3TX_Handler, /* 19 UART 3 transmit interrupt */ + UART4RX_Handler, /* 20 UART 4 receive interrupt */ + UART4TX_Handler, /* 21 UART 4 transmit interrupt */ + SPI_2_Handler, /* 22 SPI 2 interrupt */ + SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ +#if defined CMSDK_CM0_VHT + ARM_VSI0_Handler, /* 24 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 25 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 26 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 27 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 28 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 29 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 30 VSI 6 interrupt */ + ARM_VSI7_Handler /* 31 VSI 7 interrupt */ +#else + GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ + GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ + GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ + GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ + GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ + GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ + GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ + GPIO0_7_Handler /* 31 GPIO 0 individual interrupt ( 7) */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/CMSDK_CM0_VHT/startup_CMSDK_CM0.c.base@1.1.0 b/RTE/Device/CMSDK_CM0_VHT/startup_CMSDK_CM0.c.base@1.1.0 new file mode 100644 index 0000000..cb505f7 --- /dev/null +++ b/RTE/Device/CMSDK_CM0_VHT/startup_CMSDK_CM0.c.base@1.1.0 @@ -0,0 +1,218 @@ +/****************************************************************************** + * @file startup_CMSDK_CM0.c + * @brief CMSIS Startup File for CMSDK_M0 Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM0) || defined (CMSDK_CM0_VHT) + #include "CMSDK_CM0.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM0_VHT /* VSI Interrupts */ +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#else +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + UART0RX_Handler, /* 0 UART 0 receive interrupt */ + UART0TX_Handler, /* 1 UART 0 transmit interrupt */ + UART1RX_Handler, /* 2 UART 1 receive interrupt */ + UART1TX_Handler, /* 3 UART 1 transmit interrupt */ + UART2RX_Handler, /* 4 UART 2 receive interrupt */ + UART2TX_Handler, /* 5 UART 2 transmit interrupt */ + GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ + GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ + TIMER0_Handler, /* 8 Timer 0 interrupt */ + TIMER1_Handler, /* 9 Timer 1 interrupt */ + DUALTIMER_Handler, /* 10 Dual Timer interrupt */ + SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ + ETHERNET_Handler, /* 13 Ethernet interrupt */ + I2S_Handler, /* 14 Audio I2S interrupt */ + TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ + GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ + GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ + UART3RX_Handler, /* 18 UART 3 receive interrupt */ + UART3TX_Handler, /* 19 UART 3 transmit interrupt */ + UART4RX_Handler, /* 20 UART 4 receive interrupt */ + UART4TX_Handler, /* 21 UART 4 transmit interrupt */ + SPI_2_Handler, /* 22 SPI 2 interrupt */ + SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ +#if defined CMSDK_CM0_VHT + ARM_VSI0_Handler, /* 24 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 25 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 26 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 27 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 28 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 29 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 30 VSI 6 interrupt */ + ARM_VSI7_Handler /* 31 VSI 7 interrupt */ +#else + GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ + GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ + GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ + GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ + GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ + GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ + GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ + GPIO0_7_Handler /* 31 GPIO 0 individual interrupt ( 7) */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/CMSDK_CM0_VHT/system_CMSDK_CM0.c b/RTE/Device/CMSDK_CM0_VHT/system_CMSDK_CM0.c new file mode 100644 index 0000000..b838f25 --- /dev/null +++ b/RTE/Device/CMSDK_CM0_VHT/system_CMSDK_CM0.c @@ -0,0 +1,71 @@ +/****************************************************************************** + * @file system_CMSDK_CM0.c + * @brief CMSIS System Source File for CMSDK_M0 Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM0) || defined (CMSDK_CM0_VHT) + #include "CMSDK_CM0.h" +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/CMSDK_CM0_VHT/system_CMSDK_CM0.c.base@1.1.0 b/RTE/Device/CMSDK_CM0_VHT/system_CMSDK_CM0.c.base@1.1.0 new file mode 100644 index 0000000..b838f25 --- /dev/null +++ b/RTE/Device/CMSDK_CM0_VHT/system_CMSDK_CM0.c.base@1.1.0 @@ -0,0 +1,71 @@ +/****************************************************************************** + * @file system_CMSDK_CM0.c + * @brief CMSIS System Source File for CMSDK_M0 Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM0) || defined (CMSDK_CM0_VHT) + #include "CMSDK_CM0.h" +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/CMSDK_CM0plus_VHT/RTE_Device.h.base@1.0.0 b/RTE/Device/CMSDK_CM0plus_VHT/RTE_Device.h.base@1.0.0 new file mode 100644 index 0000000..786b74f --- /dev/null +++ b/RTE/Device/CMSDK_CM0plus_VHT/RTE_Device.h.base@1.0.0 @@ -0,0 +1,50 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 25. April 2016 + * $Revision: V1.0.0 + * + * Project: RTE Device Configuration for ARM CMSDK_CM device + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_USART0 0 + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_UART2 0 + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_UART3 0 + +#endif /* __RTE_DEVICE_H */ diff --git a/RTE/Device/CMSDK_CM0plus_VHT/ac6_arm.sct b/RTE/Device/CMSDK_CM0plus_VHT/ac6_arm.sct new file mode 100644 index 0000000..7a68551 --- /dev/null +++ b/RTE/Device/CMSDK_CM0plus_VHT/ac6_arm.sct @@ -0,0 +1,76 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0+ -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/RTE/Device/CMSDK_CM0plus_VHT/ac6_arm.sct.base@1.0.0 b/RTE/Device/CMSDK_CM0plus_VHT/ac6_arm.sct.base@1.0.0 new file mode 100644 index 0000000..7a68551 --- /dev/null +++ b/RTE/Device/CMSDK_CM0plus_VHT/ac6_arm.sct.base@1.0.0 @@ -0,0 +1,76 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0+ -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/RTE/Device/CMSDK_CM0plus_VHT/gcc_arm.ld b/RTE/Device/CMSDK_CM0plus_VHT/gcc_arm.ld new file mode 100644 index 0000000..aa2735f --- /dev/null +++ b/RTE/Device/CMSDK_CM0plus_VHT/gcc_arm.ld @@ -0,0 +1,277 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/CMSDK_CM0plus_VHT/gcc_arm.ld.base@1.1.0 b/RTE/Device/CMSDK_CM0plus_VHT/gcc_arm.ld.base@1.1.0 new file mode 100644 index 0000000..aa2735f --- /dev/null +++ b/RTE/Device/CMSDK_CM0plus_VHT/gcc_arm.ld.base@1.1.0 @@ -0,0 +1,277 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/CMSDK_CM0plus_VHT/startup_CMSDK_CM0plus.c b/RTE/Device/CMSDK_CM0plus_VHT/startup_CMSDK_CM0plus.c new file mode 100644 index 0000000..f89c4b6 --- /dev/null +++ b/RTE/Device/CMSDK_CM0plus_VHT/startup_CMSDK_CM0plus.c @@ -0,0 +1,218 @@ +/****************************************************************************** + * @file startup_CMSDK_CM0plus.c + * @brief CMSIS Startup File for CMSDK_M0plus Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM0plus) || defined (CMSDK_CM0plus_VHT) + #include "CMSDK_CM0plus.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM0plus_VHT /* VSI Interrupts */ +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#else +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + UART0RX_Handler, /* 0 UART 0 receive interrupt */ + UART0TX_Handler, /* 1 UART 0 transmit interrupt */ + UART1RX_Handler, /* 2 UART 1 receive interrupt */ + UART1TX_Handler, /* 3 UART 1 transmit interrupt */ + UART2RX_Handler, /* 4 UART 2 receive interrupt */ + UART2TX_Handler, /* 5 UART 2 transmit interrupt */ + GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ + GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ + TIMER0_Handler, /* 8 Timer 0 interrupt */ + TIMER1_Handler, /* 9 Timer 1 interrupt */ + DUALTIMER_Handler, /* 10 Dual Timer interrupt */ + SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ + ETHERNET_Handler, /* 13 Ethernet interrupt */ + I2S_Handler, /* 14 Audio I2S interrupt */ + TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ + GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ + GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ + UART3RX_Handler, /* 18 UART 3 receive interrupt */ + UART3TX_Handler, /* 19 UART 3 transmit interrupt */ + UART4RX_Handler, /* 20 UART 4 receive interrupt */ + UART4TX_Handler, /* 21 UART 4 transmit interrupt */ + SPI_2_Handler, /* 22 SPI 2 interrupt */ + SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ +#if defined CMSDK_CM0plus_VHT + ARM_VSI0_Handler, /* 24 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 25 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 26 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 27 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 28 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 29 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 30 VSI 6 interrupt */ + ARM_VSI7_Handler /* 31 VSI 7 interrupt */ +#else + GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ + GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ + GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ + GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ + GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ + GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ + GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ + GPIO0_7_Handler /* 31 GPIO 0 individual interrupt ( 7) */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/CMSDK_CM0plus_VHT/startup_CMSDK_CM0plus.c.base@1.1.0 b/RTE/Device/CMSDK_CM0plus_VHT/startup_CMSDK_CM0plus.c.base@1.1.0 new file mode 100644 index 0000000..f89c4b6 --- /dev/null +++ b/RTE/Device/CMSDK_CM0plus_VHT/startup_CMSDK_CM0plus.c.base@1.1.0 @@ -0,0 +1,218 @@ +/****************************************************************************** + * @file startup_CMSDK_CM0plus.c + * @brief CMSIS Startup File for CMSDK_M0plus Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM0plus) || defined (CMSDK_CM0plus_VHT) + #include "CMSDK_CM0plus.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM0plus_VHT /* VSI Interrupts */ +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#else +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + UART0RX_Handler, /* 0 UART 0 receive interrupt */ + UART0TX_Handler, /* 1 UART 0 transmit interrupt */ + UART1RX_Handler, /* 2 UART 1 receive interrupt */ + UART1TX_Handler, /* 3 UART 1 transmit interrupt */ + UART2RX_Handler, /* 4 UART 2 receive interrupt */ + UART2TX_Handler, /* 5 UART 2 transmit interrupt */ + GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ + GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ + TIMER0_Handler, /* 8 Timer 0 interrupt */ + TIMER1_Handler, /* 9 Timer 1 interrupt */ + DUALTIMER_Handler, /* 10 Dual Timer interrupt */ + SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ + ETHERNET_Handler, /* 13 Ethernet interrupt */ + I2S_Handler, /* 14 Audio I2S interrupt */ + TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ + GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ + GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ + UART3RX_Handler, /* 18 UART 3 receive interrupt */ + UART3TX_Handler, /* 19 UART 3 transmit interrupt */ + UART4RX_Handler, /* 20 UART 4 receive interrupt */ + UART4TX_Handler, /* 21 UART 4 transmit interrupt */ + SPI_2_Handler, /* 22 SPI 2 interrupt */ + SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ +#if defined CMSDK_CM0plus_VHT + ARM_VSI0_Handler, /* 24 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 25 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 26 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 27 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 28 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 29 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 30 VSI 6 interrupt */ + ARM_VSI7_Handler /* 31 VSI 7 interrupt */ +#else + GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ + GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ + GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ + GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ + GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ + GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ + GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ + GPIO0_7_Handler /* 31 GPIO 0 individual interrupt ( 7) */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/CMSDK_CM0plus_VHT/system_CMSDK_CM0plus.c b/RTE/Device/CMSDK_CM0plus_VHT/system_CMSDK_CM0plus.c new file mode 100644 index 0000000..cd31f9e --- /dev/null +++ b/RTE/Device/CMSDK_CM0plus_VHT/system_CMSDK_CM0plus.c @@ -0,0 +1,74 @@ +/****************************************************************************** + * @file system_CMSDK_CM0plus.c + * @brief CMSIS System Source File for CMSDK_M0plus Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM0plus) || defined (CMSDK_CM0plus_VHT) + #include "CMSDK_CM0plus.h" +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/CMSDK_CM0plus_VHT/system_CMSDK_CM0plus.c.base@1.1.0 b/RTE/Device/CMSDK_CM0plus_VHT/system_CMSDK_CM0plus.c.base@1.1.0 new file mode 100644 index 0000000..cd31f9e --- /dev/null +++ b/RTE/Device/CMSDK_CM0plus_VHT/system_CMSDK_CM0plus.c.base@1.1.0 @@ -0,0 +1,74 @@ +/****************************************************************************** + * @file system_CMSDK_CM0plus.c + * @brief CMSIS System Source File for CMSDK_M0plus Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM0plus) || defined (CMSDK_CM0plus_VHT) + #include "CMSDK_CM0plus.h" +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/CMSDK_CM3_VHT/RTE_Device.h.base@1.0.0 b/RTE/Device/CMSDK_CM3_VHT/RTE_Device.h.base@1.0.0 new file mode 100644 index 0000000..786b74f --- /dev/null +++ b/RTE/Device/CMSDK_CM3_VHT/RTE_Device.h.base@1.0.0 @@ -0,0 +1,50 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 25. April 2016 + * $Revision: V1.0.0 + * + * Project: RTE Device Configuration for ARM CMSDK_CM device + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_USART0 0 + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_UART2 0 + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_UART3 0 + +#endif /* __RTE_DEVICE_H */ diff --git a/RTE/Device/CMSDK_CM3_VHT/ac6_arm.sct b/RTE/Device/CMSDK_CM3_VHT/ac6_arm.sct new file mode 100644 index 0000000..6c981e9 --- /dev/null +++ b/RTE/Device/CMSDK_CM3_VHT/ac6_arm.sct @@ -0,0 +1,76 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/RTE/Device/CMSDK_CM3_VHT/ac6_arm.sct.base@1.0.0 b/RTE/Device/CMSDK_CM3_VHT/ac6_arm.sct.base@1.0.0 new file mode 100644 index 0000000..6c981e9 --- /dev/null +++ b/RTE/Device/CMSDK_CM3_VHT/ac6_arm.sct.base@1.0.0 @@ -0,0 +1,76 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/RTE/Device/CMSDK_CM3_VHT/gcc_arm.ld b/RTE/Device/CMSDK_CM3_VHT/gcc_arm.ld new file mode 100644 index 0000000..aa2735f --- /dev/null +++ b/RTE/Device/CMSDK_CM3_VHT/gcc_arm.ld @@ -0,0 +1,277 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/CMSDK_CM3_VHT/gcc_arm.ld.base@1.1.0 b/RTE/Device/CMSDK_CM3_VHT/gcc_arm.ld.base@1.1.0 new file mode 100644 index 0000000..aa2735f --- /dev/null +++ b/RTE/Device/CMSDK_CM3_VHT/gcc_arm.ld.base@1.1.0 @@ -0,0 +1,277 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/CMSDK_CM3_VHT/startup_CMSDK_CM3.c b/RTE/Device/CMSDK_CM3_VHT/startup_CMSDK_CM3.c new file mode 100644 index 0000000..117c390 --- /dev/null +++ b/RTE/Device/CMSDK_CM3_VHT/startup_CMSDK_CM3.c @@ -0,0 +1,421 @@ +/****************************************************************************** + * @file startup_CMSDK_CM3.c + * @brief CMSIS Startup File for CMSDK_M3 Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM3) || defined (CMSDK_CM3_VHT) + #include "CMSDK_CM3.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM3_VHT +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + UART0RX_Handler, /* 0 UART 0 receive interrupt */ + UART0TX_Handler, /* 1 UART 0 transmit interrupt */ + UART1RX_Handler, /* 2 UART 1 receive interrupt */ + UART1TX_Handler, /* 3 UART 1 transmit interrupt */ + UART2RX_Handler, /* 4 UART 2 receive interrupt */ + UART2TX_Handler, /* 5 UART 2 transmit interrupt */ + GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ + GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ + TIMER0_Handler, /* 8 Timer 0 interrupt */ + TIMER1_Handler, /* 9 Timer 1 interrupt */ + DUALTIMER_Handler, /* 10 Dual Timer interrupt */ + SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ + ETHERNET_Handler, /* 13 Ethernet interrupt */ + I2S_Handler, /* 14 Audio I2S interrupt */ + TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ + GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ + GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ + UART3RX_Handler, /* 18 UART 3 receive interrupt */ + UART3TX_Handler, /* 19 UART 3 transmit interrupt */ + UART4RX_Handler, /* 20 UART 4 receive interrupt */ + UART4TX_Handler, /* 21 UART 4 transmit interrupt */ + SPI_2_Handler, /* 22 SPI 2 interrupt */ + SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ + GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ + GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ + GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ + GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ + GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ + GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ + GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ + GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ + 0, /* 32 Reserved */ + 0, /* 33 Reserved */ + 0, /* 34 Reserved */ + 0, /* 35 Reserved */ + 0, /* 36 Reserved */ + 0, /* 37 Reserved */ + 0, /* 38 Reserved */ + 0, /* 39 Reserved */ + 0, /* 40 Reserved */ + 0, /* 41 Reserved */ + 0, /* 42 Reserved */ + 0, /* 43 Reserved */ + 0, /* 44 Reserved */ + 0, /* 45 Reserved */ + 0, /* 46 Reserved */ + 0, /* 47 Reserved */ + 0, /* 48 Reserved */ + 0, /* 49 Reserved */ + 0, /* 50 Reserved */ + 0, /* 51 Reserved */ + 0, /* 52 Reserved */ + 0, /* 53 Reserved */ + 0, /* 54 Reserved */ + 0, /* 55 Reserved */ + 0, /* 56 Reserved */ + 0, /* 57 Reserved */ + 0, /* 58 Reserved */ + 0, /* 59 Reserved */ + 0, /* 60 Reserved */ + 0, /* 61 Reserved */ + 0, /* 62 Reserved */ + 0, /* 63 Reserved */ + 0, /* 64 Reserved */ + 0, /* 65 Reserved */ + 0, /* 66 Reserved */ + 0, /* 67 Reserved */ + 0, /* 68 Reserved */ + 0, /* 69 Reserved */ + 0, /* 70 Reserved */ + 0, /* 71 Reserved */ + 0, /* 72 Reserved */ + 0, /* 73 Reserved */ + 0, /* 74 Reserved */ + 0, /* 75 Reserved */ + 0, /* 76 Reserved */ + 0, /* 77 Reserved */ + 0, /* 78 Reserved */ + 0, /* 79 Reserved */ + 0, /* 80 Reserved */ + 0, /* 81 Reserved */ + 0, /* 82 Reserved */ + 0, /* 83 Reserved */ + 0, /* 84 Reserved */ + 0, /* 85 Reserved */ + 0, /* 86 Reserved */ + 0, /* 87 Reserved */ + 0, /* 88 Reserved */ + 0, /* 89 Reserved */ + 0, /* 90 Reserved */ + 0, /* 91 Reserved */ + 0, /* 92 Reserved */ + 0, /* 93 Reserved */ + 0, /* 94 Reserved */ + 0, /* 95 Reserved */ + 0, /* 96 Reserved */ + 0, /* 97 Reserved */ + 0, /* 98 Reserved */ + 0, /* 99 Reserved */ + 0, /* 100 Reserved */ + 0, /* 101 Reserved */ + 0, /* 102 Reserved */ + 0, /* 103 Reserved */ + 0, /* 104 Reserved */ + 0, /* 105 Reserved */ + 0, /* 106 Reserved */ + 0, /* 107 Reserved */ + 0, /* 108 Reserved */ + 0, /* 109 Reserved */ + 0, /* 110 Reserved */ + 0, /* 111 Reserved */ + 0, /* 112 Reserved */ + 0, /* 113 Reserved */ + 0, /* 114 Reserved */ + 0, /* 115 Reserved */ + 0, /* 116 Reserved */ + 0, /* 117 Reserved */ + 0, /* 118 Reserved */ + 0, /* 119 Reserved */ + 0, /* 120 Reserved */ + 0, /* 121 Reserved */ + 0, /* 122 Reserved */ + 0, /* 123 Reserved */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined CMSDK_CM3_VHT + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/CMSDK_CM3_VHT/startup_CMSDK_CM3.c.base@1.1.0 b/RTE/Device/CMSDK_CM3_VHT/startup_CMSDK_CM3.c.base@1.1.0 new file mode 100644 index 0000000..117c390 --- /dev/null +++ b/RTE/Device/CMSDK_CM3_VHT/startup_CMSDK_CM3.c.base@1.1.0 @@ -0,0 +1,421 @@ +/****************************************************************************** + * @file startup_CMSDK_CM3.c + * @brief CMSIS Startup File for CMSDK_M3 Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM3) || defined (CMSDK_CM3_VHT) + #include "CMSDK_CM3.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM3_VHT +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + UART0RX_Handler, /* 0 UART 0 receive interrupt */ + UART0TX_Handler, /* 1 UART 0 transmit interrupt */ + UART1RX_Handler, /* 2 UART 1 receive interrupt */ + UART1TX_Handler, /* 3 UART 1 transmit interrupt */ + UART2RX_Handler, /* 4 UART 2 receive interrupt */ + UART2TX_Handler, /* 5 UART 2 transmit interrupt */ + GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ + GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ + TIMER0_Handler, /* 8 Timer 0 interrupt */ + TIMER1_Handler, /* 9 Timer 1 interrupt */ + DUALTIMER_Handler, /* 10 Dual Timer interrupt */ + SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ + ETHERNET_Handler, /* 13 Ethernet interrupt */ + I2S_Handler, /* 14 Audio I2S interrupt */ + TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ + GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ + GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ + UART3RX_Handler, /* 18 UART 3 receive interrupt */ + UART3TX_Handler, /* 19 UART 3 transmit interrupt */ + UART4RX_Handler, /* 20 UART 4 receive interrupt */ + UART4TX_Handler, /* 21 UART 4 transmit interrupt */ + SPI_2_Handler, /* 22 SPI 2 interrupt */ + SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ + GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ + GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ + GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ + GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ + GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ + GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ + GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ + GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ + 0, /* 32 Reserved */ + 0, /* 33 Reserved */ + 0, /* 34 Reserved */ + 0, /* 35 Reserved */ + 0, /* 36 Reserved */ + 0, /* 37 Reserved */ + 0, /* 38 Reserved */ + 0, /* 39 Reserved */ + 0, /* 40 Reserved */ + 0, /* 41 Reserved */ + 0, /* 42 Reserved */ + 0, /* 43 Reserved */ + 0, /* 44 Reserved */ + 0, /* 45 Reserved */ + 0, /* 46 Reserved */ + 0, /* 47 Reserved */ + 0, /* 48 Reserved */ + 0, /* 49 Reserved */ + 0, /* 50 Reserved */ + 0, /* 51 Reserved */ + 0, /* 52 Reserved */ + 0, /* 53 Reserved */ + 0, /* 54 Reserved */ + 0, /* 55 Reserved */ + 0, /* 56 Reserved */ + 0, /* 57 Reserved */ + 0, /* 58 Reserved */ + 0, /* 59 Reserved */ + 0, /* 60 Reserved */ + 0, /* 61 Reserved */ + 0, /* 62 Reserved */ + 0, /* 63 Reserved */ + 0, /* 64 Reserved */ + 0, /* 65 Reserved */ + 0, /* 66 Reserved */ + 0, /* 67 Reserved */ + 0, /* 68 Reserved */ + 0, /* 69 Reserved */ + 0, /* 70 Reserved */ + 0, /* 71 Reserved */ + 0, /* 72 Reserved */ + 0, /* 73 Reserved */ + 0, /* 74 Reserved */ + 0, /* 75 Reserved */ + 0, /* 76 Reserved */ + 0, /* 77 Reserved */ + 0, /* 78 Reserved */ + 0, /* 79 Reserved */ + 0, /* 80 Reserved */ + 0, /* 81 Reserved */ + 0, /* 82 Reserved */ + 0, /* 83 Reserved */ + 0, /* 84 Reserved */ + 0, /* 85 Reserved */ + 0, /* 86 Reserved */ + 0, /* 87 Reserved */ + 0, /* 88 Reserved */ + 0, /* 89 Reserved */ + 0, /* 90 Reserved */ + 0, /* 91 Reserved */ + 0, /* 92 Reserved */ + 0, /* 93 Reserved */ + 0, /* 94 Reserved */ + 0, /* 95 Reserved */ + 0, /* 96 Reserved */ + 0, /* 97 Reserved */ + 0, /* 98 Reserved */ + 0, /* 99 Reserved */ + 0, /* 100 Reserved */ + 0, /* 101 Reserved */ + 0, /* 102 Reserved */ + 0, /* 103 Reserved */ + 0, /* 104 Reserved */ + 0, /* 105 Reserved */ + 0, /* 106 Reserved */ + 0, /* 107 Reserved */ + 0, /* 108 Reserved */ + 0, /* 109 Reserved */ + 0, /* 110 Reserved */ + 0, /* 111 Reserved */ + 0, /* 112 Reserved */ + 0, /* 113 Reserved */ + 0, /* 114 Reserved */ + 0, /* 115 Reserved */ + 0, /* 116 Reserved */ + 0, /* 117 Reserved */ + 0, /* 118 Reserved */ + 0, /* 119 Reserved */ + 0, /* 120 Reserved */ + 0, /* 121 Reserved */ + 0, /* 122 Reserved */ + 0, /* 123 Reserved */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined CMSDK_CM3_VHT + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/CMSDK_CM3_VHT/system_CMSDK_CM3.c b/RTE/Device/CMSDK_CM3_VHT/system_CMSDK_CM3.c new file mode 100644 index 0000000..d83b399 --- /dev/null +++ b/RTE/Device/CMSDK_CM3_VHT/system_CMSDK_CM3.c @@ -0,0 +1,78 @@ +/****************************************************************************** + * @file system_CMSDK_CM3.c + * @brief CMSIS System Source File for CMSDK_M3 Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM3) || defined (CMSDK_CM3_VHT) + #include "CMSDK_CM3.h" +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/CMSDK_CM3_VHT/system_CMSDK_CM3.c.base@1.1.0 b/RTE/Device/CMSDK_CM3_VHT/system_CMSDK_CM3.c.base@1.1.0 new file mode 100644 index 0000000..d83b399 --- /dev/null +++ b/RTE/Device/CMSDK_CM3_VHT/system_CMSDK_CM3.c.base@1.1.0 @@ -0,0 +1,78 @@ +/****************************************************************************** + * @file system_CMSDK_CM3.c + * @brief CMSIS System Source File for CMSDK_M3 Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM3) || defined (CMSDK_CM3_VHT) + #include "CMSDK_CM3.h" +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/CMSDK_CM4_FP_VHT/RTE_Device.h.base@1.0.0 b/RTE/Device/CMSDK_CM4_FP_VHT/RTE_Device.h.base@1.0.0 new file mode 100644 index 0000000..786b74f --- /dev/null +++ b/RTE/Device/CMSDK_CM4_FP_VHT/RTE_Device.h.base@1.0.0 @@ -0,0 +1,50 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 25. April 2016 + * $Revision: V1.0.0 + * + * Project: RTE Device Configuration for ARM CMSDK_CM device + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_USART0 0 + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_UART2 0 + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_UART3 0 + +#endif /* __RTE_DEVICE_H */ diff --git a/RTE/Device/CMSDK_CM4_FP_VHT/ac6_arm.sct b/RTE/Device/CMSDK_CM4_FP_VHT/ac6_arm.sct new file mode 100644 index 0000000..163dc6c --- /dev/null +++ b/RTE/Device/CMSDK_CM4_FP_VHT/ac6_arm.sct @@ -0,0 +1,76 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/RTE/Device/CMSDK_CM4_FP_VHT/ac6_arm.sct.base@1.0.0 b/RTE/Device/CMSDK_CM4_FP_VHT/ac6_arm.sct.base@1.0.0 new file mode 100644 index 0000000..163dc6c --- /dev/null +++ b/RTE/Device/CMSDK_CM4_FP_VHT/ac6_arm.sct.base@1.0.0 @@ -0,0 +1,76 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/RTE/Device/CMSDK_CM4_FP_VHT/gcc_arm.ld b/RTE/Device/CMSDK_CM4_FP_VHT/gcc_arm.ld new file mode 100644 index 0000000..aa2735f --- /dev/null +++ b/RTE/Device/CMSDK_CM4_FP_VHT/gcc_arm.ld @@ -0,0 +1,277 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/CMSDK_CM4_FP_VHT/gcc_arm.ld.base@1.1.0 b/RTE/Device/CMSDK_CM4_FP_VHT/gcc_arm.ld.base@1.1.0 new file mode 100644 index 0000000..aa2735f --- /dev/null +++ b/RTE/Device/CMSDK_CM4_FP_VHT/gcc_arm.ld.base@1.1.0 @@ -0,0 +1,277 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/CMSDK_CM4_FP_VHT/startup_CMSDK_CM4.c b/RTE/Device/CMSDK_CM4_FP_VHT/startup_CMSDK_CM4.c new file mode 100644 index 0000000..8d76cd9 --- /dev/null +++ b/RTE/Device/CMSDK_CM4_FP_VHT/startup_CMSDK_CM4.c @@ -0,0 +1,423 @@ +/****************************************************************************** + * @file startup_CMSDK_CM4.c + * @brief CMSIS Startup File for CMSDK_M4 Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM4) || defined (CMSDK_CM4_VHT) + #include "CMSDK_CM4.h" +#elif defined (CMSDK_CM4_FP) || defined (CMSDK_CM4_FP_VHT) + #include "CMSDK_CM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM4_VHT || defined CMSDK_CM4_FP_VHT +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + UART0RX_Handler, /* 0 UART 0 receive interrupt */ + UART0TX_Handler, /* 1 UART 0 transmit interrupt */ + UART1RX_Handler, /* 2 UART 1 receive interrupt */ + UART1TX_Handler, /* 3 UART 1 transmit interrupt */ + UART2RX_Handler, /* 4 UART 2 receive interrupt */ + UART2TX_Handler, /* 5 UART 2 transmit interrupt */ + GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ + GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ + TIMER0_Handler, /* 8 Timer 0 interrupt */ + TIMER1_Handler, /* 9 Timer 1 interrupt */ + DUALTIMER_Handler, /* 10 Dual Timer interrupt */ + SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ + ETHERNET_Handler, /* 13 Ethernet interrupt */ + I2S_Handler, /* 14 Audio I2S interrupt */ + TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ + GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ + GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ + UART3RX_Handler, /* 18 UART 3 receive interrupt */ + UART3TX_Handler, /* 19 UART 3 transmit interrupt */ + UART4RX_Handler, /* 20 UART 4 receive interrupt */ + UART4TX_Handler, /* 21 UART 4 transmit interrupt */ + SPI_2_Handler, /* 22 SPI 2 interrupt */ + SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ + GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ + GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ + GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ + GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ + GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ + GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ + GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ + GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ + 0, /* 32 Reserved */ + 0, /* 33 Reserved */ + 0, /* 34 Reserved */ + 0, /* 35 Reserved */ + 0, /* 36 Reserved */ + 0, /* 37 Reserved */ + 0, /* 38 Reserved */ + 0, /* 39 Reserved */ + 0, /* 40 Reserved */ + 0, /* 41 Reserved */ + 0, /* 42 Reserved */ + 0, /* 43 Reserved */ + 0, /* 44 Reserved */ + 0, /* 45 Reserved */ + 0, /* 46 Reserved */ + 0, /* 47 Reserved */ + 0, /* 48 Reserved */ + 0, /* 49 Reserved */ + 0, /* 50 Reserved */ + 0, /* 51 Reserved */ + 0, /* 52 Reserved */ + 0, /* 53 Reserved */ + 0, /* 54 Reserved */ + 0, /* 55 Reserved */ + 0, /* 56 Reserved */ + 0, /* 57 Reserved */ + 0, /* 58 Reserved */ + 0, /* 59 Reserved */ + 0, /* 60 Reserved */ + 0, /* 61 Reserved */ + 0, /* 62 Reserved */ + 0, /* 63 Reserved */ + 0, /* 64 Reserved */ + 0, /* 65 Reserved */ + 0, /* 66 Reserved */ + 0, /* 67 Reserved */ + 0, /* 68 Reserved */ + 0, /* 69 Reserved */ + 0, /* 70 Reserved */ + 0, /* 71 Reserved */ + 0, /* 72 Reserved */ + 0, /* 73 Reserved */ + 0, /* 74 Reserved */ + 0, /* 75 Reserved */ + 0, /* 76 Reserved */ + 0, /* 77 Reserved */ + 0, /* 78 Reserved */ + 0, /* 79 Reserved */ + 0, /* 80 Reserved */ + 0, /* 81 Reserved */ + 0, /* 82 Reserved */ + 0, /* 83 Reserved */ + 0, /* 84 Reserved */ + 0, /* 85 Reserved */ + 0, /* 86 Reserved */ + 0, /* 87 Reserved */ + 0, /* 88 Reserved */ + 0, /* 89 Reserved */ + 0, /* 90 Reserved */ + 0, /* 91 Reserved */ + 0, /* 92 Reserved */ + 0, /* 93 Reserved */ + 0, /* 94 Reserved */ + 0, /* 95 Reserved */ + 0, /* 96 Reserved */ + 0, /* 97 Reserved */ + 0, /* 98 Reserved */ + 0, /* 99 Reserved */ + 0, /* 100 Reserved */ + 0, /* 101 Reserved */ + 0, /* 102 Reserved */ + 0, /* 103 Reserved */ + 0, /* 104 Reserved */ + 0, /* 105 Reserved */ + 0, /* 106 Reserved */ + 0, /* 107 Reserved */ + 0, /* 108 Reserved */ + 0, /* 109 Reserved */ + 0, /* 110 Reserved */ + 0, /* 111 Reserved */ + 0, /* 112 Reserved */ + 0, /* 113 Reserved */ + 0, /* 114 Reserved */ + 0, /* 115 Reserved */ + 0, /* 116 Reserved */ + 0, /* 117 Reserved */ + 0, /* 118 Reserved */ + 0, /* 119 Reserved */ + 0, /* 120 Reserved */ + 0, /* 121 Reserved */ + 0, /* 122 Reserved */ + 0, /* 123 Reserved */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined CMSDK_CM4_VHT || defined CMSDK_CM4_FP_VHT + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/CMSDK_CM4_FP_VHT/startup_CMSDK_CM4.c.base@1.1.0 b/RTE/Device/CMSDK_CM4_FP_VHT/startup_CMSDK_CM4.c.base@1.1.0 new file mode 100644 index 0000000..8d76cd9 --- /dev/null +++ b/RTE/Device/CMSDK_CM4_FP_VHT/startup_CMSDK_CM4.c.base@1.1.0 @@ -0,0 +1,423 @@ +/****************************************************************************** + * @file startup_CMSDK_CM4.c + * @brief CMSIS Startup File for CMSDK_M4 Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM4) || defined (CMSDK_CM4_VHT) + #include "CMSDK_CM4.h" +#elif defined (CMSDK_CM4_FP) || defined (CMSDK_CM4_FP_VHT) + #include "CMSDK_CM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM4_VHT || defined CMSDK_CM4_FP_VHT +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + UART0RX_Handler, /* 0 UART 0 receive interrupt */ + UART0TX_Handler, /* 1 UART 0 transmit interrupt */ + UART1RX_Handler, /* 2 UART 1 receive interrupt */ + UART1TX_Handler, /* 3 UART 1 transmit interrupt */ + UART2RX_Handler, /* 4 UART 2 receive interrupt */ + UART2TX_Handler, /* 5 UART 2 transmit interrupt */ + GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ + GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ + TIMER0_Handler, /* 8 Timer 0 interrupt */ + TIMER1_Handler, /* 9 Timer 1 interrupt */ + DUALTIMER_Handler, /* 10 Dual Timer interrupt */ + SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ + ETHERNET_Handler, /* 13 Ethernet interrupt */ + I2S_Handler, /* 14 Audio I2S interrupt */ + TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ + GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ + GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ + UART3RX_Handler, /* 18 UART 3 receive interrupt */ + UART3TX_Handler, /* 19 UART 3 transmit interrupt */ + UART4RX_Handler, /* 20 UART 4 receive interrupt */ + UART4TX_Handler, /* 21 UART 4 transmit interrupt */ + SPI_2_Handler, /* 22 SPI 2 interrupt */ + SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ + GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ + GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ + GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ + GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ + GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ + GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ + GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ + GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ + 0, /* 32 Reserved */ + 0, /* 33 Reserved */ + 0, /* 34 Reserved */ + 0, /* 35 Reserved */ + 0, /* 36 Reserved */ + 0, /* 37 Reserved */ + 0, /* 38 Reserved */ + 0, /* 39 Reserved */ + 0, /* 40 Reserved */ + 0, /* 41 Reserved */ + 0, /* 42 Reserved */ + 0, /* 43 Reserved */ + 0, /* 44 Reserved */ + 0, /* 45 Reserved */ + 0, /* 46 Reserved */ + 0, /* 47 Reserved */ + 0, /* 48 Reserved */ + 0, /* 49 Reserved */ + 0, /* 50 Reserved */ + 0, /* 51 Reserved */ + 0, /* 52 Reserved */ + 0, /* 53 Reserved */ + 0, /* 54 Reserved */ + 0, /* 55 Reserved */ + 0, /* 56 Reserved */ + 0, /* 57 Reserved */ + 0, /* 58 Reserved */ + 0, /* 59 Reserved */ + 0, /* 60 Reserved */ + 0, /* 61 Reserved */ + 0, /* 62 Reserved */ + 0, /* 63 Reserved */ + 0, /* 64 Reserved */ + 0, /* 65 Reserved */ + 0, /* 66 Reserved */ + 0, /* 67 Reserved */ + 0, /* 68 Reserved */ + 0, /* 69 Reserved */ + 0, /* 70 Reserved */ + 0, /* 71 Reserved */ + 0, /* 72 Reserved */ + 0, /* 73 Reserved */ + 0, /* 74 Reserved */ + 0, /* 75 Reserved */ + 0, /* 76 Reserved */ + 0, /* 77 Reserved */ + 0, /* 78 Reserved */ + 0, /* 79 Reserved */ + 0, /* 80 Reserved */ + 0, /* 81 Reserved */ + 0, /* 82 Reserved */ + 0, /* 83 Reserved */ + 0, /* 84 Reserved */ + 0, /* 85 Reserved */ + 0, /* 86 Reserved */ + 0, /* 87 Reserved */ + 0, /* 88 Reserved */ + 0, /* 89 Reserved */ + 0, /* 90 Reserved */ + 0, /* 91 Reserved */ + 0, /* 92 Reserved */ + 0, /* 93 Reserved */ + 0, /* 94 Reserved */ + 0, /* 95 Reserved */ + 0, /* 96 Reserved */ + 0, /* 97 Reserved */ + 0, /* 98 Reserved */ + 0, /* 99 Reserved */ + 0, /* 100 Reserved */ + 0, /* 101 Reserved */ + 0, /* 102 Reserved */ + 0, /* 103 Reserved */ + 0, /* 104 Reserved */ + 0, /* 105 Reserved */ + 0, /* 106 Reserved */ + 0, /* 107 Reserved */ + 0, /* 108 Reserved */ + 0, /* 109 Reserved */ + 0, /* 110 Reserved */ + 0, /* 111 Reserved */ + 0, /* 112 Reserved */ + 0, /* 113 Reserved */ + 0, /* 114 Reserved */ + 0, /* 115 Reserved */ + 0, /* 116 Reserved */ + 0, /* 117 Reserved */ + 0, /* 118 Reserved */ + 0, /* 119 Reserved */ + 0, /* 120 Reserved */ + 0, /* 121 Reserved */ + 0, /* 122 Reserved */ + 0, /* 123 Reserved */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined CMSDK_CM4_VHT || defined CMSDK_CM4_FP_VHT + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/CMSDK_CM4_FP_VHT/system_CMSDK_CM4.c b/RTE/Device/CMSDK_CM4_FP_VHT/system_CMSDK_CM4.c new file mode 100644 index 0000000..27aa0d7 --- /dev/null +++ b/RTE/Device/CMSDK_CM4_FP_VHT/system_CMSDK_CM4.c @@ -0,0 +1,85 @@ +/****************************************************************************** + * @file system_CMSDK_CM4.c + * @brief CMSIS System Source File for CMSDK_M4 Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM4) || defined (CMSDK_CM4_VHT) + #include "CMSDK_CM4.h" +#elif defined (CMSDK_CM4_FP) || defined (CMSDK_CM4_FP_VHT) + #include "CMSDK_CM4_FP.h" +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/CMSDK_CM4_FP_VHT/system_CMSDK_CM4.c.base@1.1.0 b/RTE/Device/CMSDK_CM4_FP_VHT/system_CMSDK_CM4.c.base@1.1.0 new file mode 100644 index 0000000..27aa0d7 --- /dev/null +++ b/RTE/Device/CMSDK_CM4_FP_VHT/system_CMSDK_CM4.c.base@1.1.0 @@ -0,0 +1,85 @@ +/****************************************************************************** + * @file system_CMSDK_CM4.c + * @brief CMSIS System Source File for CMSDK_M4 Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM4) || defined (CMSDK_CM4_VHT) + #include "CMSDK_CM4.h" +#elif defined (CMSDK_CM4_FP) || defined (CMSDK_CM4_FP_VHT) + #include "CMSDK_CM4_FP.h" +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/CMSDK_CM4_VHT/RTE_Device.h.base@1.0.0 b/RTE/Device/CMSDK_CM4_VHT/RTE_Device.h.base@1.0.0 new file mode 100644 index 0000000..786b74f --- /dev/null +++ b/RTE/Device/CMSDK_CM4_VHT/RTE_Device.h.base@1.0.0 @@ -0,0 +1,50 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 25. April 2016 + * $Revision: V1.0.0 + * + * Project: RTE Device Configuration for ARM CMSDK_CM device + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_USART0 0 + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_UART2 0 + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_UART3 0 + +#endif /* __RTE_DEVICE_H */ diff --git a/RTE/Device/CMSDK_CM4_VHT/ac6_arm.sct b/RTE/Device/CMSDK_CM4_VHT/ac6_arm.sct new file mode 100644 index 0000000..163dc6c --- /dev/null +++ b/RTE/Device/CMSDK_CM4_VHT/ac6_arm.sct @@ -0,0 +1,76 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/RTE/Device/CMSDK_CM4_VHT/ac6_arm.sct.base@1.0.0 b/RTE/Device/CMSDK_CM4_VHT/ac6_arm.sct.base@1.0.0 new file mode 100644 index 0000000..163dc6c --- /dev/null +++ b/RTE/Device/CMSDK_CM4_VHT/ac6_arm.sct.base@1.0.0 @@ -0,0 +1,76 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/RTE/Device/CMSDK_CM4_VHT/gcc_arm.ld b/RTE/Device/CMSDK_CM4_VHT/gcc_arm.ld new file mode 100644 index 0000000..aa2735f --- /dev/null +++ b/RTE/Device/CMSDK_CM4_VHT/gcc_arm.ld @@ -0,0 +1,277 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/CMSDK_CM4_VHT/gcc_arm.ld.base@1.1.0 b/RTE/Device/CMSDK_CM4_VHT/gcc_arm.ld.base@1.1.0 new file mode 100644 index 0000000..aa2735f --- /dev/null +++ b/RTE/Device/CMSDK_CM4_VHT/gcc_arm.ld.base@1.1.0 @@ -0,0 +1,277 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/CMSDK_CM4_VHT/startup_CMSDK_CM4.c b/RTE/Device/CMSDK_CM4_VHT/startup_CMSDK_CM4.c new file mode 100644 index 0000000..8d76cd9 --- /dev/null +++ b/RTE/Device/CMSDK_CM4_VHT/startup_CMSDK_CM4.c @@ -0,0 +1,423 @@ +/****************************************************************************** + * @file startup_CMSDK_CM4.c + * @brief CMSIS Startup File for CMSDK_M4 Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM4) || defined (CMSDK_CM4_VHT) + #include "CMSDK_CM4.h" +#elif defined (CMSDK_CM4_FP) || defined (CMSDK_CM4_FP_VHT) + #include "CMSDK_CM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM4_VHT || defined CMSDK_CM4_FP_VHT +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + UART0RX_Handler, /* 0 UART 0 receive interrupt */ + UART0TX_Handler, /* 1 UART 0 transmit interrupt */ + UART1RX_Handler, /* 2 UART 1 receive interrupt */ + UART1TX_Handler, /* 3 UART 1 transmit interrupt */ + UART2RX_Handler, /* 4 UART 2 receive interrupt */ + UART2TX_Handler, /* 5 UART 2 transmit interrupt */ + GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ + GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ + TIMER0_Handler, /* 8 Timer 0 interrupt */ + TIMER1_Handler, /* 9 Timer 1 interrupt */ + DUALTIMER_Handler, /* 10 Dual Timer interrupt */ + SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ + ETHERNET_Handler, /* 13 Ethernet interrupt */ + I2S_Handler, /* 14 Audio I2S interrupt */ + TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ + GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ + GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ + UART3RX_Handler, /* 18 UART 3 receive interrupt */ + UART3TX_Handler, /* 19 UART 3 transmit interrupt */ + UART4RX_Handler, /* 20 UART 4 receive interrupt */ + UART4TX_Handler, /* 21 UART 4 transmit interrupt */ + SPI_2_Handler, /* 22 SPI 2 interrupt */ + SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ + GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ + GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ + GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ + GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ + GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ + GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ + GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ + GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ + 0, /* 32 Reserved */ + 0, /* 33 Reserved */ + 0, /* 34 Reserved */ + 0, /* 35 Reserved */ + 0, /* 36 Reserved */ + 0, /* 37 Reserved */ + 0, /* 38 Reserved */ + 0, /* 39 Reserved */ + 0, /* 40 Reserved */ + 0, /* 41 Reserved */ + 0, /* 42 Reserved */ + 0, /* 43 Reserved */ + 0, /* 44 Reserved */ + 0, /* 45 Reserved */ + 0, /* 46 Reserved */ + 0, /* 47 Reserved */ + 0, /* 48 Reserved */ + 0, /* 49 Reserved */ + 0, /* 50 Reserved */ + 0, /* 51 Reserved */ + 0, /* 52 Reserved */ + 0, /* 53 Reserved */ + 0, /* 54 Reserved */ + 0, /* 55 Reserved */ + 0, /* 56 Reserved */ + 0, /* 57 Reserved */ + 0, /* 58 Reserved */ + 0, /* 59 Reserved */ + 0, /* 60 Reserved */ + 0, /* 61 Reserved */ + 0, /* 62 Reserved */ + 0, /* 63 Reserved */ + 0, /* 64 Reserved */ + 0, /* 65 Reserved */ + 0, /* 66 Reserved */ + 0, /* 67 Reserved */ + 0, /* 68 Reserved */ + 0, /* 69 Reserved */ + 0, /* 70 Reserved */ + 0, /* 71 Reserved */ + 0, /* 72 Reserved */ + 0, /* 73 Reserved */ + 0, /* 74 Reserved */ + 0, /* 75 Reserved */ + 0, /* 76 Reserved */ + 0, /* 77 Reserved */ + 0, /* 78 Reserved */ + 0, /* 79 Reserved */ + 0, /* 80 Reserved */ + 0, /* 81 Reserved */ + 0, /* 82 Reserved */ + 0, /* 83 Reserved */ + 0, /* 84 Reserved */ + 0, /* 85 Reserved */ + 0, /* 86 Reserved */ + 0, /* 87 Reserved */ + 0, /* 88 Reserved */ + 0, /* 89 Reserved */ + 0, /* 90 Reserved */ + 0, /* 91 Reserved */ + 0, /* 92 Reserved */ + 0, /* 93 Reserved */ + 0, /* 94 Reserved */ + 0, /* 95 Reserved */ + 0, /* 96 Reserved */ + 0, /* 97 Reserved */ + 0, /* 98 Reserved */ + 0, /* 99 Reserved */ + 0, /* 100 Reserved */ + 0, /* 101 Reserved */ + 0, /* 102 Reserved */ + 0, /* 103 Reserved */ + 0, /* 104 Reserved */ + 0, /* 105 Reserved */ + 0, /* 106 Reserved */ + 0, /* 107 Reserved */ + 0, /* 108 Reserved */ + 0, /* 109 Reserved */ + 0, /* 110 Reserved */ + 0, /* 111 Reserved */ + 0, /* 112 Reserved */ + 0, /* 113 Reserved */ + 0, /* 114 Reserved */ + 0, /* 115 Reserved */ + 0, /* 116 Reserved */ + 0, /* 117 Reserved */ + 0, /* 118 Reserved */ + 0, /* 119 Reserved */ + 0, /* 120 Reserved */ + 0, /* 121 Reserved */ + 0, /* 122 Reserved */ + 0, /* 123 Reserved */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined CMSDK_CM4_VHT || defined CMSDK_CM4_FP_VHT + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/CMSDK_CM4_VHT/startup_CMSDK_CM4.c.base@1.1.0 b/RTE/Device/CMSDK_CM4_VHT/startup_CMSDK_CM4.c.base@1.1.0 new file mode 100644 index 0000000..8d76cd9 --- /dev/null +++ b/RTE/Device/CMSDK_CM4_VHT/startup_CMSDK_CM4.c.base@1.1.0 @@ -0,0 +1,423 @@ +/****************************************************************************** + * @file startup_CMSDK_CM4.c + * @brief CMSIS Startup File for CMSDK_M4 Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM4) || defined (CMSDK_CM4_VHT) + #include "CMSDK_CM4.h" +#elif defined (CMSDK_CM4_FP) || defined (CMSDK_CM4_FP_VHT) + #include "CMSDK_CM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM4_VHT || defined CMSDK_CM4_FP_VHT +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + UART0RX_Handler, /* 0 UART 0 receive interrupt */ + UART0TX_Handler, /* 1 UART 0 transmit interrupt */ + UART1RX_Handler, /* 2 UART 1 receive interrupt */ + UART1TX_Handler, /* 3 UART 1 transmit interrupt */ + UART2RX_Handler, /* 4 UART 2 receive interrupt */ + UART2TX_Handler, /* 5 UART 2 transmit interrupt */ + GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ + GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ + TIMER0_Handler, /* 8 Timer 0 interrupt */ + TIMER1_Handler, /* 9 Timer 1 interrupt */ + DUALTIMER_Handler, /* 10 Dual Timer interrupt */ + SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ + ETHERNET_Handler, /* 13 Ethernet interrupt */ + I2S_Handler, /* 14 Audio I2S interrupt */ + TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ + GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ + GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ + UART3RX_Handler, /* 18 UART 3 receive interrupt */ + UART3TX_Handler, /* 19 UART 3 transmit interrupt */ + UART4RX_Handler, /* 20 UART 4 receive interrupt */ + UART4TX_Handler, /* 21 UART 4 transmit interrupt */ + SPI_2_Handler, /* 22 SPI 2 interrupt */ + SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ + GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ + GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ + GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ + GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ + GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ + GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ + GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ + GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ + 0, /* 32 Reserved */ + 0, /* 33 Reserved */ + 0, /* 34 Reserved */ + 0, /* 35 Reserved */ + 0, /* 36 Reserved */ + 0, /* 37 Reserved */ + 0, /* 38 Reserved */ + 0, /* 39 Reserved */ + 0, /* 40 Reserved */ + 0, /* 41 Reserved */ + 0, /* 42 Reserved */ + 0, /* 43 Reserved */ + 0, /* 44 Reserved */ + 0, /* 45 Reserved */ + 0, /* 46 Reserved */ + 0, /* 47 Reserved */ + 0, /* 48 Reserved */ + 0, /* 49 Reserved */ + 0, /* 50 Reserved */ + 0, /* 51 Reserved */ + 0, /* 52 Reserved */ + 0, /* 53 Reserved */ + 0, /* 54 Reserved */ + 0, /* 55 Reserved */ + 0, /* 56 Reserved */ + 0, /* 57 Reserved */ + 0, /* 58 Reserved */ + 0, /* 59 Reserved */ + 0, /* 60 Reserved */ + 0, /* 61 Reserved */ + 0, /* 62 Reserved */ + 0, /* 63 Reserved */ + 0, /* 64 Reserved */ + 0, /* 65 Reserved */ + 0, /* 66 Reserved */ + 0, /* 67 Reserved */ + 0, /* 68 Reserved */ + 0, /* 69 Reserved */ + 0, /* 70 Reserved */ + 0, /* 71 Reserved */ + 0, /* 72 Reserved */ + 0, /* 73 Reserved */ + 0, /* 74 Reserved */ + 0, /* 75 Reserved */ + 0, /* 76 Reserved */ + 0, /* 77 Reserved */ + 0, /* 78 Reserved */ + 0, /* 79 Reserved */ + 0, /* 80 Reserved */ + 0, /* 81 Reserved */ + 0, /* 82 Reserved */ + 0, /* 83 Reserved */ + 0, /* 84 Reserved */ + 0, /* 85 Reserved */ + 0, /* 86 Reserved */ + 0, /* 87 Reserved */ + 0, /* 88 Reserved */ + 0, /* 89 Reserved */ + 0, /* 90 Reserved */ + 0, /* 91 Reserved */ + 0, /* 92 Reserved */ + 0, /* 93 Reserved */ + 0, /* 94 Reserved */ + 0, /* 95 Reserved */ + 0, /* 96 Reserved */ + 0, /* 97 Reserved */ + 0, /* 98 Reserved */ + 0, /* 99 Reserved */ + 0, /* 100 Reserved */ + 0, /* 101 Reserved */ + 0, /* 102 Reserved */ + 0, /* 103 Reserved */ + 0, /* 104 Reserved */ + 0, /* 105 Reserved */ + 0, /* 106 Reserved */ + 0, /* 107 Reserved */ + 0, /* 108 Reserved */ + 0, /* 109 Reserved */ + 0, /* 110 Reserved */ + 0, /* 111 Reserved */ + 0, /* 112 Reserved */ + 0, /* 113 Reserved */ + 0, /* 114 Reserved */ + 0, /* 115 Reserved */ + 0, /* 116 Reserved */ + 0, /* 117 Reserved */ + 0, /* 118 Reserved */ + 0, /* 119 Reserved */ + 0, /* 120 Reserved */ + 0, /* 121 Reserved */ + 0, /* 122 Reserved */ + 0, /* 123 Reserved */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined CMSDK_CM4_VHT || defined CMSDK_CM4_FP_VHT + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/CMSDK_CM4_VHT/system_CMSDK_CM4.c b/RTE/Device/CMSDK_CM4_VHT/system_CMSDK_CM4.c new file mode 100644 index 0000000..27aa0d7 --- /dev/null +++ b/RTE/Device/CMSDK_CM4_VHT/system_CMSDK_CM4.c @@ -0,0 +1,85 @@ +/****************************************************************************** + * @file system_CMSDK_CM4.c + * @brief CMSIS System Source File for CMSDK_M4 Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM4) || defined (CMSDK_CM4_VHT) + #include "CMSDK_CM4.h" +#elif defined (CMSDK_CM4_FP) || defined (CMSDK_CM4_FP_VHT) + #include "CMSDK_CM4_FP.h" +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/CMSDK_CM4_VHT/system_CMSDK_CM4.c.base@1.1.0 b/RTE/Device/CMSDK_CM4_VHT/system_CMSDK_CM4.c.base@1.1.0 new file mode 100644 index 0000000..27aa0d7 --- /dev/null +++ b/RTE/Device/CMSDK_CM4_VHT/system_CMSDK_CM4.c.base@1.1.0 @@ -0,0 +1,85 @@ +/****************************************************************************** + * @file system_CMSDK_CM4.c + * @brief CMSIS System Source File for CMSDK_M4 Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM4) || defined (CMSDK_CM4_VHT) + #include "CMSDK_CM4.h" +#elif defined (CMSDK_CM4_FP) || defined (CMSDK_CM4_FP_VHT) + #include "CMSDK_CM4_FP.h" +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/CMSDK_CM7_DP_VHT/RTE_Device.h.base@1.0.0 b/RTE/Device/CMSDK_CM7_DP_VHT/RTE_Device.h.base@1.0.0 new file mode 100644 index 0000000..786b74f --- /dev/null +++ b/RTE/Device/CMSDK_CM7_DP_VHT/RTE_Device.h.base@1.0.0 @@ -0,0 +1,50 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 25. April 2016 + * $Revision: V1.0.0 + * + * Project: RTE Device Configuration for ARM CMSDK_CM device + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_USART0 0 + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_UART2 0 + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_UART3 0 + +#endif /* __RTE_DEVICE_H */ diff --git a/RTE/Device/CMSDK_CM7_DP_VHT/ac6_arm.sct b/RTE/Device/CMSDK_CM7_DP_VHT/ac6_arm.sct new file mode 100644 index 0000000..9e1bb7d --- /dev/null +++ b/RTE/Device/CMSDK_CM7_DP_VHT/ac6_arm.sct @@ -0,0 +1,76 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/RTE/Device/CMSDK_CM7_DP_VHT/ac6_arm.sct.base@1.0.0 b/RTE/Device/CMSDK_CM7_DP_VHT/ac6_arm.sct.base@1.0.0 new file mode 100644 index 0000000..9e1bb7d --- /dev/null +++ b/RTE/Device/CMSDK_CM7_DP_VHT/ac6_arm.sct.base@1.0.0 @@ -0,0 +1,76 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/RTE/Device/CMSDK_CM7_DP_VHT/startup_CMSDK_CM7.c b/RTE/Device/CMSDK_CM7_DP_VHT/startup_CMSDK_CM7.c new file mode 100644 index 0000000..02f2aff --- /dev/null +++ b/RTE/Device/CMSDK_CM7_DP_VHT/startup_CMSDK_CM7.c @@ -0,0 +1,425 @@ +/****************************************************************************** + * @file startup_CMSDK_CM7.c + * @brief CMSIS Startup File for CMSDK_M7 Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) + #include "CMSDK_CM7.h" +#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) + #include "CMSDK_CM7_SP.h" +#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) + #include "CMSDK_CM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + UART0RX_Handler, /* 0 UART 0 receive interrupt */ + UART0TX_Handler, /* 1 UART 0 transmit interrupt */ + UART1RX_Handler, /* 2 UART 1 receive interrupt */ + UART1TX_Handler, /* 3 UART 1 transmit interrupt */ + UART2RX_Handler, /* 4 UART 2 receive interrupt */ + UART2TX_Handler, /* 5 UART 2 transmit interrupt */ + GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ + GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ + TIMER0_Handler, /* 8 Timer 0 interrupt */ + TIMER1_Handler, /* 9 Timer 1 interrupt */ + DUALTIMER_Handler, /* 10 Dual Timer interrupt */ + SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ + ETHERNET_Handler, /* 13 Ethernet interrupt */ + I2S_Handler, /* 14 Audio I2S interrupt */ + TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ + GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ + GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ + UART3RX_Handler, /* 18 UART 3 receive interrupt */ + UART3TX_Handler, /* 19 UART 3 transmit interrupt */ + UART4RX_Handler, /* 20 UART 4 receive interrupt */ + UART4TX_Handler, /* 21 UART 4 transmit interrupt */ + SPI_2_Handler, /* 22 SPI 2 interrupt */ + SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ + GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ + GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ + GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ + GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ + GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ + GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ + GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ + GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ + 0, /* 32 Reserved */ + 0, /* 33 Reserved */ + 0, /* 34 Reserved */ + 0, /* 35 Reserved */ + 0, /* 36 Reserved */ + 0, /* 37 Reserved */ + 0, /* 38 Reserved */ + 0, /* 39 Reserved */ + 0, /* 40 Reserved */ + 0, /* 41 Reserved */ + 0, /* 42 Reserved */ + 0, /* 43 Reserved */ + 0, /* 44 Reserved */ + 0, /* 45 Reserved */ + 0, /* 46 Reserved */ + 0, /* 47 Reserved */ + 0, /* 48 Reserved */ + 0, /* 49 Reserved */ + 0, /* 50 Reserved */ + 0, /* 51 Reserved */ + 0, /* 52 Reserved */ + 0, /* 53 Reserved */ + 0, /* 54 Reserved */ + 0, /* 55 Reserved */ + 0, /* 56 Reserved */ + 0, /* 57 Reserved */ + 0, /* 58 Reserved */ + 0, /* 59 Reserved */ + 0, /* 60 Reserved */ + 0, /* 61 Reserved */ + 0, /* 62 Reserved */ + 0, /* 63 Reserved */ + 0, /* 64 Reserved */ + 0, /* 65 Reserved */ + 0, /* 66 Reserved */ + 0, /* 67 Reserved */ + 0, /* 68 Reserved */ + 0, /* 69 Reserved */ + 0, /* 70 Reserved */ + 0, /* 71 Reserved */ + 0, /* 72 Reserved */ + 0, /* 73 Reserved */ + 0, /* 74 Reserved */ + 0, /* 75 Reserved */ + 0, /* 76 Reserved */ + 0, /* 77 Reserved */ + 0, /* 78 Reserved */ + 0, /* 79 Reserved */ + 0, /* 80 Reserved */ + 0, /* 81 Reserved */ + 0, /* 82 Reserved */ + 0, /* 83 Reserved */ + 0, /* 84 Reserved */ + 0, /* 85 Reserved */ + 0, /* 86 Reserved */ + 0, /* 87 Reserved */ + 0, /* 88 Reserved */ + 0, /* 89 Reserved */ + 0, /* 90 Reserved */ + 0, /* 91 Reserved */ + 0, /* 92 Reserved */ + 0, /* 93 Reserved */ + 0, /* 94 Reserved */ + 0, /* 95 Reserved */ + 0, /* 96 Reserved */ + 0, /* 97 Reserved */ + 0, /* 98 Reserved */ + 0, /* 99 Reserved */ + 0, /* 100 Reserved */ + 0, /* 101 Reserved */ + 0, /* 102 Reserved */ + 0, /* 103 Reserved */ + 0, /* 104 Reserved */ + 0, /* 105 Reserved */ + 0, /* 106 Reserved */ + 0, /* 107 Reserved */ + 0, /* 108 Reserved */ + 0, /* 109 Reserved */ + 0, /* 110 Reserved */ + 0, /* 111 Reserved */ + 0, /* 112 Reserved */ + 0, /* 113 Reserved */ + 0, /* 114 Reserved */ + 0, /* 115 Reserved */ + 0, /* 116 Reserved */ + 0, /* 117 Reserved */ + 0, /* 118 Reserved */ + 0, /* 119 Reserved */ + 0, /* 120 Reserved */ + 0, /* 121 Reserved */ + 0, /* 122 Reserved */ + 0, /* 123 Reserved */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/CMSDK_CM7_DP_VHT/startup_CMSDK_CM7.c.base@1.1.0 b/RTE/Device/CMSDK_CM7_DP_VHT/startup_CMSDK_CM7.c.base@1.1.0 new file mode 100644 index 0000000..02f2aff --- /dev/null +++ b/RTE/Device/CMSDK_CM7_DP_VHT/startup_CMSDK_CM7.c.base@1.1.0 @@ -0,0 +1,425 @@ +/****************************************************************************** + * @file startup_CMSDK_CM7.c + * @brief CMSIS Startup File for CMSDK_M7 Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) + #include "CMSDK_CM7.h" +#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) + #include "CMSDK_CM7_SP.h" +#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) + #include "CMSDK_CM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + UART0RX_Handler, /* 0 UART 0 receive interrupt */ + UART0TX_Handler, /* 1 UART 0 transmit interrupt */ + UART1RX_Handler, /* 2 UART 1 receive interrupt */ + UART1TX_Handler, /* 3 UART 1 transmit interrupt */ + UART2RX_Handler, /* 4 UART 2 receive interrupt */ + UART2TX_Handler, /* 5 UART 2 transmit interrupt */ + GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ + GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ + TIMER0_Handler, /* 8 Timer 0 interrupt */ + TIMER1_Handler, /* 9 Timer 1 interrupt */ + DUALTIMER_Handler, /* 10 Dual Timer interrupt */ + SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ + ETHERNET_Handler, /* 13 Ethernet interrupt */ + I2S_Handler, /* 14 Audio I2S interrupt */ + TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ + GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ + GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ + UART3RX_Handler, /* 18 UART 3 receive interrupt */ + UART3TX_Handler, /* 19 UART 3 transmit interrupt */ + UART4RX_Handler, /* 20 UART 4 receive interrupt */ + UART4TX_Handler, /* 21 UART 4 transmit interrupt */ + SPI_2_Handler, /* 22 SPI 2 interrupt */ + SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ + GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ + GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ + GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ + GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ + GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ + GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ + GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ + GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ + 0, /* 32 Reserved */ + 0, /* 33 Reserved */ + 0, /* 34 Reserved */ + 0, /* 35 Reserved */ + 0, /* 36 Reserved */ + 0, /* 37 Reserved */ + 0, /* 38 Reserved */ + 0, /* 39 Reserved */ + 0, /* 40 Reserved */ + 0, /* 41 Reserved */ + 0, /* 42 Reserved */ + 0, /* 43 Reserved */ + 0, /* 44 Reserved */ + 0, /* 45 Reserved */ + 0, /* 46 Reserved */ + 0, /* 47 Reserved */ + 0, /* 48 Reserved */ + 0, /* 49 Reserved */ + 0, /* 50 Reserved */ + 0, /* 51 Reserved */ + 0, /* 52 Reserved */ + 0, /* 53 Reserved */ + 0, /* 54 Reserved */ + 0, /* 55 Reserved */ + 0, /* 56 Reserved */ + 0, /* 57 Reserved */ + 0, /* 58 Reserved */ + 0, /* 59 Reserved */ + 0, /* 60 Reserved */ + 0, /* 61 Reserved */ + 0, /* 62 Reserved */ + 0, /* 63 Reserved */ + 0, /* 64 Reserved */ + 0, /* 65 Reserved */ + 0, /* 66 Reserved */ + 0, /* 67 Reserved */ + 0, /* 68 Reserved */ + 0, /* 69 Reserved */ + 0, /* 70 Reserved */ + 0, /* 71 Reserved */ + 0, /* 72 Reserved */ + 0, /* 73 Reserved */ + 0, /* 74 Reserved */ + 0, /* 75 Reserved */ + 0, /* 76 Reserved */ + 0, /* 77 Reserved */ + 0, /* 78 Reserved */ + 0, /* 79 Reserved */ + 0, /* 80 Reserved */ + 0, /* 81 Reserved */ + 0, /* 82 Reserved */ + 0, /* 83 Reserved */ + 0, /* 84 Reserved */ + 0, /* 85 Reserved */ + 0, /* 86 Reserved */ + 0, /* 87 Reserved */ + 0, /* 88 Reserved */ + 0, /* 89 Reserved */ + 0, /* 90 Reserved */ + 0, /* 91 Reserved */ + 0, /* 92 Reserved */ + 0, /* 93 Reserved */ + 0, /* 94 Reserved */ + 0, /* 95 Reserved */ + 0, /* 96 Reserved */ + 0, /* 97 Reserved */ + 0, /* 98 Reserved */ + 0, /* 99 Reserved */ + 0, /* 100 Reserved */ + 0, /* 101 Reserved */ + 0, /* 102 Reserved */ + 0, /* 103 Reserved */ + 0, /* 104 Reserved */ + 0, /* 105 Reserved */ + 0, /* 106 Reserved */ + 0, /* 107 Reserved */ + 0, /* 108 Reserved */ + 0, /* 109 Reserved */ + 0, /* 110 Reserved */ + 0, /* 111 Reserved */ + 0, /* 112 Reserved */ + 0, /* 113 Reserved */ + 0, /* 114 Reserved */ + 0, /* 115 Reserved */ + 0, /* 116 Reserved */ + 0, /* 117 Reserved */ + 0, /* 118 Reserved */ + 0, /* 119 Reserved */ + 0, /* 120 Reserved */ + 0, /* 121 Reserved */ + 0, /* 122 Reserved */ + 0, /* 123 Reserved */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/CMSDK_CM7_DP_VHT/system_CMSDK_CM7.c b/RTE/Device/CMSDK_CM7_DP_VHT/system_CMSDK_CM7.c new file mode 100644 index 0000000..fdfec7a --- /dev/null +++ b/RTE/Device/CMSDK_CM7_DP_VHT/system_CMSDK_CM7.c @@ -0,0 +1,87 @@ +/****************************************************************************** + * @file system_CMSDK_CM7.c + * @brief CMSIS System Source File for CMSDK_CM7 Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) + #include "CMSDK_CM7.h" +#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) + #include "CMSDK_CM7_SP.h" +#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) + #include "CMSDK_CM7_DP.h" +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/CMSDK_CM7_DP_VHT/system_CMSDK_CM7.c.base@1.1.0 b/RTE/Device/CMSDK_CM7_DP_VHT/system_CMSDK_CM7.c.base@1.1.0 new file mode 100644 index 0000000..fdfec7a --- /dev/null +++ b/RTE/Device/CMSDK_CM7_DP_VHT/system_CMSDK_CM7.c.base@1.1.0 @@ -0,0 +1,87 @@ +/****************************************************************************** + * @file system_CMSDK_CM7.c + * @brief CMSIS System Source File for CMSDK_CM7 Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) + #include "CMSDK_CM7.h" +#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) + #include "CMSDK_CM7_SP.h" +#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) + #include "CMSDK_CM7_DP.h" +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/CMSDK_CM7_SP_VHT/RTE_Device.h.base@1.0.0 b/RTE/Device/CMSDK_CM7_SP_VHT/RTE_Device.h.base@1.0.0 new file mode 100644 index 0000000..786b74f --- /dev/null +++ b/RTE/Device/CMSDK_CM7_SP_VHT/RTE_Device.h.base@1.0.0 @@ -0,0 +1,50 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 25. April 2016 + * $Revision: V1.0.0 + * + * Project: RTE Device Configuration for ARM CMSDK_CM device + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_USART0 0 + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_UART2 0 + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_UART3 0 + +#endif /* __RTE_DEVICE_H */ diff --git a/RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct b/RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct new file mode 100644 index 0000000..9e1bb7d --- /dev/null +++ b/RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct @@ -0,0 +1,76 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct.base@1.0.0 b/RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct.base@1.0.0 new file mode 100644 index 0000000..9e1bb7d --- /dev/null +++ b/RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct.base@1.0.0 @@ -0,0 +1,76 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c b/RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c new file mode 100644 index 0000000..02f2aff --- /dev/null +++ b/RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c @@ -0,0 +1,425 @@ +/****************************************************************************** + * @file startup_CMSDK_CM7.c + * @brief CMSIS Startup File for CMSDK_M7 Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) + #include "CMSDK_CM7.h" +#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) + #include "CMSDK_CM7_SP.h" +#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) + #include "CMSDK_CM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + UART0RX_Handler, /* 0 UART 0 receive interrupt */ + UART0TX_Handler, /* 1 UART 0 transmit interrupt */ + UART1RX_Handler, /* 2 UART 1 receive interrupt */ + UART1TX_Handler, /* 3 UART 1 transmit interrupt */ + UART2RX_Handler, /* 4 UART 2 receive interrupt */ + UART2TX_Handler, /* 5 UART 2 transmit interrupt */ + GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ + GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ + TIMER0_Handler, /* 8 Timer 0 interrupt */ + TIMER1_Handler, /* 9 Timer 1 interrupt */ + DUALTIMER_Handler, /* 10 Dual Timer interrupt */ + SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ + ETHERNET_Handler, /* 13 Ethernet interrupt */ + I2S_Handler, /* 14 Audio I2S interrupt */ + TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ + GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ + GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ + UART3RX_Handler, /* 18 UART 3 receive interrupt */ + UART3TX_Handler, /* 19 UART 3 transmit interrupt */ + UART4RX_Handler, /* 20 UART 4 receive interrupt */ + UART4TX_Handler, /* 21 UART 4 transmit interrupt */ + SPI_2_Handler, /* 22 SPI 2 interrupt */ + SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ + GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ + GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ + GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ + GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ + GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ + GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ + GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ + GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ + 0, /* 32 Reserved */ + 0, /* 33 Reserved */ + 0, /* 34 Reserved */ + 0, /* 35 Reserved */ + 0, /* 36 Reserved */ + 0, /* 37 Reserved */ + 0, /* 38 Reserved */ + 0, /* 39 Reserved */ + 0, /* 40 Reserved */ + 0, /* 41 Reserved */ + 0, /* 42 Reserved */ + 0, /* 43 Reserved */ + 0, /* 44 Reserved */ + 0, /* 45 Reserved */ + 0, /* 46 Reserved */ + 0, /* 47 Reserved */ + 0, /* 48 Reserved */ + 0, /* 49 Reserved */ + 0, /* 50 Reserved */ + 0, /* 51 Reserved */ + 0, /* 52 Reserved */ + 0, /* 53 Reserved */ + 0, /* 54 Reserved */ + 0, /* 55 Reserved */ + 0, /* 56 Reserved */ + 0, /* 57 Reserved */ + 0, /* 58 Reserved */ + 0, /* 59 Reserved */ + 0, /* 60 Reserved */ + 0, /* 61 Reserved */ + 0, /* 62 Reserved */ + 0, /* 63 Reserved */ + 0, /* 64 Reserved */ + 0, /* 65 Reserved */ + 0, /* 66 Reserved */ + 0, /* 67 Reserved */ + 0, /* 68 Reserved */ + 0, /* 69 Reserved */ + 0, /* 70 Reserved */ + 0, /* 71 Reserved */ + 0, /* 72 Reserved */ + 0, /* 73 Reserved */ + 0, /* 74 Reserved */ + 0, /* 75 Reserved */ + 0, /* 76 Reserved */ + 0, /* 77 Reserved */ + 0, /* 78 Reserved */ + 0, /* 79 Reserved */ + 0, /* 80 Reserved */ + 0, /* 81 Reserved */ + 0, /* 82 Reserved */ + 0, /* 83 Reserved */ + 0, /* 84 Reserved */ + 0, /* 85 Reserved */ + 0, /* 86 Reserved */ + 0, /* 87 Reserved */ + 0, /* 88 Reserved */ + 0, /* 89 Reserved */ + 0, /* 90 Reserved */ + 0, /* 91 Reserved */ + 0, /* 92 Reserved */ + 0, /* 93 Reserved */ + 0, /* 94 Reserved */ + 0, /* 95 Reserved */ + 0, /* 96 Reserved */ + 0, /* 97 Reserved */ + 0, /* 98 Reserved */ + 0, /* 99 Reserved */ + 0, /* 100 Reserved */ + 0, /* 101 Reserved */ + 0, /* 102 Reserved */ + 0, /* 103 Reserved */ + 0, /* 104 Reserved */ + 0, /* 105 Reserved */ + 0, /* 106 Reserved */ + 0, /* 107 Reserved */ + 0, /* 108 Reserved */ + 0, /* 109 Reserved */ + 0, /* 110 Reserved */ + 0, /* 111 Reserved */ + 0, /* 112 Reserved */ + 0, /* 113 Reserved */ + 0, /* 114 Reserved */ + 0, /* 115 Reserved */ + 0, /* 116 Reserved */ + 0, /* 117 Reserved */ + 0, /* 118 Reserved */ + 0, /* 119 Reserved */ + 0, /* 120 Reserved */ + 0, /* 121 Reserved */ + 0, /* 122 Reserved */ + 0, /* 123 Reserved */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c.base@1.1.0 b/RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c.base@1.1.0 new file mode 100644 index 0000000..02f2aff --- /dev/null +++ b/RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c.base@1.1.0 @@ -0,0 +1,425 @@ +/****************************************************************************** + * @file startup_CMSDK_CM7.c + * @brief CMSIS Startup File for CMSDK_M7 Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) + #include "CMSDK_CM7.h" +#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) + #include "CMSDK_CM7_SP.h" +#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) + #include "CMSDK_CM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + UART0RX_Handler, /* 0 UART 0 receive interrupt */ + UART0TX_Handler, /* 1 UART 0 transmit interrupt */ + UART1RX_Handler, /* 2 UART 1 receive interrupt */ + UART1TX_Handler, /* 3 UART 1 transmit interrupt */ + UART2RX_Handler, /* 4 UART 2 receive interrupt */ + UART2TX_Handler, /* 5 UART 2 transmit interrupt */ + GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ + GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ + TIMER0_Handler, /* 8 Timer 0 interrupt */ + TIMER1_Handler, /* 9 Timer 1 interrupt */ + DUALTIMER_Handler, /* 10 Dual Timer interrupt */ + SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ + ETHERNET_Handler, /* 13 Ethernet interrupt */ + I2S_Handler, /* 14 Audio I2S interrupt */ + TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ + GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ + GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ + UART3RX_Handler, /* 18 UART 3 receive interrupt */ + UART3TX_Handler, /* 19 UART 3 transmit interrupt */ + UART4RX_Handler, /* 20 UART 4 receive interrupt */ + UART4TX_Handler, /* 21 UART 4 transmit interrupt */ + SPI_2_Handler, /* 22 SPI 2 interrupt */ + SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ + GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ + GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ + GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ + GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ + GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ + GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ + GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ + GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ + 0, /* 32 Reserved */ + 0, /* 33 Reserved */ + 0, /* 34 Reserved */ + 0, /* 35 Reserved */ + 0, /* 36 Reserved */ + 0, /* 37 Reserved */ + 0, /* 38 Reserved */ + 0, /* 39 Reserved */ + 0, /* 40 Reserved */ + 0, /* 41 Reserved */ + 0, /* 42 Reserved */ + 0, /* 43 Reserved */ + 0, /* 44 Reserved */ + 0, /* 45 Reserved */ + 0, /* 46 Reserved */ + 0, /* 47 Reserved */ + 0, /* 48 Reserved */ + 0, /* 49 Reserved */ + 0, /* 50 Reserved */ + 0, /* 51 Reserved */ + 0, /* 52 Reserved */ + 0, /* 53 Reserved */ + 0, /* 54 Reserved */ + 0, /* 55 Reserved */ + 0, /* 56 Reserved */ + 0, /* 57 Reserved */ + 0, /* 58 Reserved */ + 0, /* 59 Reserved */ + 0, /* 60 Reserved */ + 0, /* 61 Reserved */ + 0, /* 62 Reserved */ + 0, /* 63 Reserved */ + 0, /* 64 Reserved */ + 0, /* 65 Reserved */ + 0, /* 66 Reserved */ + 0, /* 67 Reserved */ + 0, /* 68 Reserved */ + 0, /* 69 Reserved */ + 0, /* 70 Reserved */ + 0, /* 71 Reserved */ + 0, /* 72 Reserved */ + 0, /* 73 Reserved */ + 0, /* 74 Reserved */ + 0, /* 75 Reserved */ + 0, /* 76 Reserved */ + 0, /* 77 Reserved */ + 0, /* 78 Reserved */ + 0, /* 79 Reserved */ + 0, /* 80 Reserved */ + 0, /* 81 Reserved */ + 0, /* 82 Reserved */ + 0, /* 83 Reserved */ + 0, /* 84 Reserved */ + 0, /* 85 Reserved */ + 0, /* 86 Reserved */ + 0, /* 87 Reserved */ + 0, /* 88 Reserved */ + 0, /* 89 Reserved */ + 0, /* 90 Reserved */ + 0, /* 91 Reserved */ + 0, /* 92 Reserved */ + 0, /* 93 Reserved */ + 0, /* 94 Reserved */ + 0, /* 95 Reserved */ + 0, /* 96 Reserved */ + 0, /* 97 Reserved */ + 0, /* 98 Reserved */ + 0, /* 99 Reserved */ + 0, /* 100 Reserved */ + 0, /* 101 Reserved */ + 0, /* 102 Reserved */ + 0, /* 103 Reserved */ + 0, /* 104 Reserved */ + 0, /* 105 Reserved */ + 0, /* 106 Reserved */ + 0, /* 107 Reserved */ + 0, /* 108 Reserved */ + 0, /* 109 Reserved */ + 0, /* 110 Reserved */ + 0, /* 111 Reserved */ + 0, /* 112 Reserved */ + 0, /* 113 Reserved */ + 0, /* 114 Reserved */ + 0, /* 115 Reserved */ + 0, /* 116 Reserved */ + 0, /* 117 Reserved */ + 0, /* 118 Reserved */ + 0, /* 119 Reserved */ + 0, /* 120 Reserved */ + 0, /* 121 Reserved */ + 0, /* 122 Reserved */ + 0, /* 123 Reserved */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c b/RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c new file mode 100644 index 0000000..fdfec7a --- /dev/null +++ b/RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c @@ -0,0 +1,87 @@ +/****************************************************************************** + * @file system_CMSDK_CM7.c + * @brief CMSIS System Source File for CMSDK_CM7 Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) + #include "CMSDK_CM7.h" +#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) + #include "CMSDK_CM7_SP.h" +#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) + #include "CMSDK_CM7_DP.h" +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c.base@1.1.0 b/RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c.base@1.1.0 new file mode 100644 index 0000000..fdfec7a --- /dev/null +++ b/RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c.base@1.1.0 @@ -0,0 +1,87 @@ +/****************************************************************************** + * @file system_CMSDK_CM7.c + * @brief CMSIS System Source File for CMSDK_CM7 Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) + #include "CMSDK_CM7.h" +#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) + #include "CMSDK_CM7_SP.h" +#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) + #include "CMSDK_CM7_DP.h" +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/CMSDK_CM7_VHT/RTE_Device.h.base@1.0.0 b/RTE/Device/CMSDK_CM7_VHT/RTE_Device.h.base@1.0.0 new file mode 100644 index 0000000..786b74f --- /dev/null +++ b/RTE/Device/CMSDK_CM7_VHT/RTE_Device.h.base@1.0.0 @@ -0,0 +1,50 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 25. April 2016 + * $Revision: V1.0.0 + * + * Project: RTE Device Configuration for ARM CMSDK_CM device + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_USART0 0 + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_UART2 0 + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_UART3 0 + +#endif /* __RTE_DEVICE_H */ diff --git a/RTE/Device/CMSDK_CM7_VHT/ac6_arm.sct b/RTE/Device/CMSDK_CM7_VHT/ac6_arm.sct new file mode 100644 index 0000000..9e1bb7d --- /dev/null +++ b/RTE/Device/CMSDK_CM7_VHT/ac6_arm.sct @@ -0,0 +1,76 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/RTE/Device/CMSDK_CM7_VHT/ac6_arm.sct.base@1.0.0 b/RTE/Device/CMSDK_CM7_VHT/ac6_arm.sct.base@1.0.0 new file mode 100644 index 0000000..9e1bb7d --- /dev/null +++ b/RTE/Device/CMSDK_CM7_VHT/ac6_arm.sct.base@1.0.0 @@ -0,0 +1,76 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/RTE/Device/CMSDK_CM7_VHT/gcc_arm.ld b/RTE/Device/CMSDK_CM7_VHT/gcc_arm.ld new file mode 100644 index 0000000..aa2735f --- /dev/null +++ b/RTE/Device/CMSDK_CM7_VHT/gcc_arm.ld @@ -0,0 +1,277 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/CMSDK_CM7_VHT/gcc_arm.ld.base@1.1.0 b/RTE/Device/CMSDK_CM7_VHT/gcc_arm.ld.base@1.1.0 new file mode 100644 index 0000000..aa2735f --- /dev/null +++ b/RTE/Device/CMSDK_CM7_VHT/gcc_arm.ld.base@1.1.0 @@ -0,0 +1,277 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/CMSDK_CM7_VHT/startup_CMSDK_CM7.c b/RTE/Device/CMSDK_CM7_VHT/startup_CMSDK_CM7.c new file mode 100644 index 0000000..02f2aff --- /dev/null +++ b/RTE/Device/CMSDK_CM7_VHT/startup_CMSDK_CM7.c @@ -0,0 +1,425 @@ +/****************************************************************************** + * @file startup_CMSDK_CM7.c + * @brief CMSIS Startup File for CMSDK_M7 Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) + #include "CMSDK_CM7.h" +#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) + #include "CMSDK_CM7_SP.h" +#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) + #include "CMSDK_CM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + UART0RX_Handler, /* 0 UART 0 receive interrupt */ + UART0TX_Handler, /* 1 UART 0 transmit interrupt */ + UART1RX_Handler, /* 2 UART 1 receive interrupt */ + UART1TX_Handler, /* 3 UART 1 transmit interrupt */ + UART2RX_Handler, /* 4 UART 2 receive interrupt */ + UART2TX_Handler, /* 5 UART 2 transmit interrupt */ + GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ + GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ + TIMER0_Handler, /* 8 Timer 0 interrupt */ + TIMER1_Handler, /* 9 Timer 1 interrupt */ + DUALTIMER_Handler, /* 10 Dual Timer interrupt */ + SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ + ETHERNET_Handler, /* 13 Ethernet interrupt */ + I2S_Handler, /* 14 Audio I2S interrupt */ + TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ + GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ + GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ + UART3RX_Handler, /* 18 UART 3 receive interrupt */ + UART3TX_Handler, /* 19 UART 3 transmit interrupt */ + UART4RX_Handler, /* 20 UART 4 receive interrupt */ + UART4TX_Handler, /* 21 UART 4 transmit interrupt */ + SPI_2_Handler, /* 22 SPI 2 interrupt */ + SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ + GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ + GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ + GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ + GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ + GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ + GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ + GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ + GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ + 0, /* 32 Reserved */ + 0, /* 33 Reserved */ + 0, /* 34 Reserved */ + 0, /* 35 Reserved */ + 0, /* 36 Reserved */ + 0, /* 37 Reserved */ + 0, /* 38 Reserved */ + 0, /* 39 Reserved */ + 0, /* 40 Reserved */ + 0, /* 41 Reserved */ + 0, /* 42 Reserved */ + 0, /* 43 Reserved */ + 0, /* 44 Reserved */ + 0, /* 45 Reserved */ + 0, /* 46 Reserved */ + 0, /* 47 Reserved */ + 0, /* 48 Reserved */ + 0, /* 49 Reserved */ + 0, /* 50 Reserved */ + 0, /* 51 Reserved */ + 0, /* 52 Reserved */ + 0, /* 53 Reserved */ + 0, /* 54 Reserved */ + 0, /* 55 Reserved */ + 0, /* 56 Reserved */ + 0, /* 57 Reserved */ + 0, /* 58 Reserved */ + 0, /* 59 Reserved */ + 0, /* 60 Reserved */ + 0, /* 61 Reserved */ + 0, /* 62 Reserved */ + 0, /* 63 Reserved */ + 0, /* 64 Reserved */ + 0, /* 65 Reserved */ + 0, /* 66 Reserved */ + 0, /* 67 Reserved */ + 0, /* 68 Reserved */ + 0, /* 69 Reserved */ + 0, /* 70 Reserved */ + 0, /* 71 Reserved */ + 0, /* 72 Reserved */ + 0, /* 73 Reserved */ + 0, /* 74 Reserved */ + 0, /* 75 Reserved */ + 0, /* 76 Reserved */ + 0, /* 77 Reserved */ + 0, /* 78 Reserved */ + 0, /* 79 Reserved */ + 0, /* 80 Reserved */ + 0, /* 81 Reserved */ + 0, /* 82 Reserved */ + 0, /* 83 Reserved */ + 0, /* 84 Reserved */ + 0, /* 85 Reserved */ + 0, /* 86 Reserved */ + 0, /* 87 Reserved */ + 0, /* 88 Reserved */ + 0, /* 89 Reserved */ + 0, /* 90 Reserved */ + 0, /* 91 Reserved */ + 0, /* 92 Reserved */ + 0, /* 93 Reserved */ + 0, /* 94 Reserved */ + 0, /* 95 Reserved */ + 0, /* 96 Reserved */ + 0, /* 97 Reserved */ + 0, /* 98 Reserved */ + 0, /* 99 Reserved */ + 0, /* 100 Reserved */ + 0, /* 101 Reserved */ + 0, /* 102 Reserved */ + 0, /* 103 Reserved */ + 0, /* 104 Reserved */ + 0, /* 105 Reserved */ + 0, /* 106 Reserved */ + 0, /* 107 Reserved */ + 0, /* 108 Reserved */ + 0, /* 109 Reserved */ + 0, /* 110 Reserved */ + 0, /* 111 Reserved */ + 0, /* 112 Reserved */ + 0, /* 113 Reserved */ + 0, /* 114 Reserved */ + 0, /* 115 Reserved */ + 0, /* 116 Reserved */ + 0, /* 117 Reserved */ + 0, /* 118 Reserved */ + 0, /* 119 Reserved */ + 0, /* 120 Reserved */ + 0, /* 121 Reserved */ + 0, /* 122 Reserved */ + 0, /* 123 Reserved */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/CMSDK_CM7_VHT/startup_CMSDK_CM7.c.base@1.1.0 b/RTE/Device/CMSDK_CM7_VHT/startup_CMSDK_CM7.c.base@1.1.0 new file mode 100644 index 0000000..02f2aff --- /dev/null +++ b/RTE/Device/CMSDK_CM7_VHT/startup_CMSDK_CM7.c.base@1.1.0 @@ -0,0 +1,425 @@ +/****************************************************************************** + * @file startup_CMSDK_CM7.c + * @brief CMSIS Startup File for CMSDK_M7 Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) + #include "CMSDK_CM7.h" +#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) + #include "CMSDK_CM7_SP.h" +#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) + #include "CMSDK_CM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + UART0RX_Handler, /* 0 UART 0 receive interrupt */ + UART0TX_Handler, /* 1 UART 0 transmit interrupt */ + UART1RX_Handler, /* 2 UART 1 receive interrupt */ + UART1TX_Handler, /* 3 UART 1 transmit interrupt */ + UART2RX_Handler, /* 4 UART 2 receive interrupt */ + UART2TX_Handler, /* 5 UART 2 transmit interrupt */ + GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ + GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ + TIMER0_Handler, /* 8 Timer 0 interrupt */ + TIMER1_Handler, /* 9 Timer 1 interrupt */ + DUALTIMER_Handler, /* 10 Dual Timer interrupt */ + SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ + ETHERNET_Handler, /* 13 Ethernet interrupt */ + I2S_Handler, /* 14 Audio I2S interrupt */ + TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ + GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ + GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ + UART3RX_Handler, /* 18 UART 3 receive interrupt */ + UART3TX_Handler, /* 19 UART 3 transmit interrupt */ + UART4RX_Handler, /* 20 UART 4 receive interrupt */ + UART4TX_Handler, /* 21 UART 4 transmit interrupt */ + SPI_2_Handler, /* 22 SPI 2 interrupt */ + SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ + GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ + GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ + GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ + GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ + GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ + GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ + GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ + GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ + 0, /* 32 Reserved */ + 0, /* 33 Reserved */ + 0, /* 34 Reserved */ + 0, /* 35 Reserved */ + 0, /* 36 Reserved */ + 0, /* 37 Reserved */ + 0, /* 38 Reserved */ + 0, /* 39 Reserved */ + 0, /* 40 Reserved */ + 0, /* 41 Reserved */ + 0, /* 42 Reserved */ + 0, /* 43 Reserved */ + 0, /* 44 Reserved */ + 0, /* 45 Reserved */ + 0, /* 46 Reserved */ + 0, /* 47 Reserved */ + 0, /* 48 Reserved */ + 0, /* 49 Reserved */ + 0, /* 50 Reserved */ + 0, /* 51 Reserved */ + 0, /* 52 Reserved */ + 0, /* 53 Reserved */ + 0, /* 54 Reserved */ + 0, /* 55 Reserved */ + 0, /* 56 Reserved */ + 0, /* 57 Reserved */ + 0, /* 58 Reserved */ + 0, /* 59 Reserved */ + 0, /* 60 Reserved */ + 0, /* 61 Reserved */ + 0, /* 62 Reserved */ + 0, /* 63 Reserved */ + 0, /* 64 Reserved */ + 0, /* 65 Reserved */ + 0, /* 66 Reserved */ + 0, /* 67 Reserved */ + 0, /* 68 Reserved */ + 0, /* 69 Reserved */ + 0, /* 70 Reserved */ + 0, /* 71 Reserved */ + 0, /* 72 Reserved */ + 0, /* 73 Reserved */ + 0, /* 74 Reserved */ + 0, /* 75 Reserved */ + 0, /* 76 Reserved */ + 0, /* 77 Reserved */ + 0, /* 78 Reserved */ + 0, /* 79 Reserved */ + 0, /* 80 Reserved */ + 0, /* 81 Reserved */ + 0, /* 82 Reserved */ + 0, /* 83 Reserved */ + 0, /* 84 Reserved */ + 0, /* 85 Reserved */ + 0, /* 86 Reserved */ + 0, /* 87 Reserved */ + 0, /* 88 Reserved */ + 0, /* 89 Reserved */ + 0, /* 90 Reserved */ + 0, /* 91 Reserved */ + 0, /* 92 Reserved */ + 0, /* 93 Reserved */ + 0, /* 94 Reserved */ + 0, /* 95 Reserved */ + 0, /* 96 Reserved */ + 0, /* 97 Reserved */ + 0, /* 98 Reserved */ + 0, /* 99 Reserved */ + 0, /* 100 Reserved */ + 0, /* 101 Reserved */ + 0, /* 102 Reserved */ + 0, /* 103 Reserved */ + 0, /* 104 Reserved */ + 0, /* 105 Reserved */ + 0, /* 106 Reserved */ + 0, /* 107 Reserved */ + 0, /* 108 Reserved */ + 0, /* 109 Reserved */ + 0, /* 110 Reserved */ + 0, /* 111 Reserved */ + 0, /* 112 Reserved */ + 0, /* 113 Reserved */ + 0, /* 114 Reserved */ + 0, /* 115 Reserved */ + 0, /* 116 Reserved */ + 0, /* 117 Reserved */ + 0, /* 118 Reserved */ + 0, /* 119 Reserved */ + 0, /* 120 Reserved */ + 0, /* 121 Reserved */ + 0, /* 122 Reserved */ + 0, /* 123 Reserved */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/CMSDK_CM7_VHT/system_CMSDK_CM7.c b/RTE/Device/CMSDK_CM7_VHT/system_CMSDK_CM7.c new file mode 100644 index 0000000..fdfec7a --- /dev/null +++ b/RTE/Device/CMSDK_CM7_VHT/system_CMSDK_CM7.c @@ -0,0 +1,87 @@ +/****************************************************************************** + * @file system_CMSDK_CM7.c + * @brief CMSIS System Source File for CMSDK_CM7 Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) + #include "CMSDK_CM7.h" +#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) + #include "CMSDK_CM7_SP.h" +#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) + #include "CMSDK_CM7_DP.h" +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/CMSDK_CM7_VHT/system_CMSDK_CM7.c.base@1.1.0 b/RTE/Device/CMSDK_CM7_VHT/system_CMSDK_CM7.c.base@1.1.0 new file mode 100644 index 0000000..fdfec7a --- /dev/null +++ b/RTE/Device/CMSDK_CM7_VHT/system_CMSDK_CM7.c.base@1.1.0 @@ -0,0 +1,87 @@ +/****************************************************************************** + * @file system_CMSDK_CM7.c + * @brief CMSIS System Source File for CMSDK_CM7 Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) + #include "CMSDK_CM7.h" +#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) + #include "CMSDK_CM7_SP.h" +#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) + #include "CMSDK_CM7_DP.h" +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/IOTKit_CM23_VHT/RTE_Device.h.base@1.0.0 b/RTE/Device/IOTKit_CM23_VHT/RTE_Device.h.base@1.0.0 new file mode 100644 index 0000000..786b74f --- /dev/null +++ b/RTE/Device/IOTKit_CM23_VHT/RTE_Device.h.base@1.0.0 @@ -0,0 +1,50 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 25. April 2016 + * $Revision: V1.0.0 + * + * Project: RTE Device Configuration for ARM CMSDK_CM device + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_USART0 0 + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_UART2 0 + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_UART3 0 + +#endif /* __RTE_DEVICE_H */ diff --git a/RTE/Device/IOTKit_CM23_VHT/ac6_arm.sct b/RTE/Device/IOTKit_CM23_VHT/ac6_arm.sct new file mode 100644 index 0000000..dbd2678 --- /dev/null +++ b/RTE/Device/IOTKit_CM23_VHT/ac6_arm.sct @@ -0,0 +1,119 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc +; command above MUST be in first line (no comment above!) + +;Note: Add '-mcmse' to first line if your software model is "Secure Mode". +; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse + + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x10000000 +#define __ROM_SIZE 0x00200000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x38000000 +#define __RAM_SIZE 0x00200000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00000C00 + +/*--------------------- CMSE Venner Configuration --------------------------- +; CMSE Venner Configuration +; CMSE Venner Size (in Bytes) <0x0-0xFFFFFFFF:32> +; + *----------------------------------------------------------------------------*/ +#define __CMSEVENEER_SIZE 0x200 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + + +/*---------------------------------------------------------------------------- + Region base & size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) +#define __CV_SIZE ( __CMSEVENEER_SIZE ) +#else +#define __CV_SIZE ( 0 ) +#endif + +#define __RO_BASE ( __ROM_BASE ) +#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) + +#define __RW_BASE ( __RAM_BASE ) +#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) + + +/*---------------------------------------------------------------------------- + Scatter Region definition + *----------------------------------------------------------------------------*/ +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Venners + ER_CMSE_VENEER __CV_BASE __CV_SIZE { + *(Veneer$$CMSE) + } +} +#endif diff --git a/RTE/Device/IOTKit_CM23_VHT/ac6_arm.sct.base@1.0.0 b/RTE/Device/IOTKit_CM23_VHT/ac6_arm.sct.base@1.0.0 new file mode 100644 index 0000000..dbd2678 --- /dev/null +++ b/RTE/Device/IOTKit_CM23_VHT/ac6_arm.sct.base@1.0.0 @@ -0,0 +1,119 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc +; command above MUST be in first line (no comment above!) + +;Note: Add '-mcmse' to first line if your software model is "Secure Mode". +; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse + + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x10000000 +#define __ROM_SIZE 0x00200000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x38000000 +#define __RAM_SIZE 0x00200000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00000C00 + +/*--------------------- CMSE Venner Configuration --------------------------- +; CMSE Venner Configuration +; CMSE Venner Size (in Bytes) <0x0-0xFFFFFFFF:32> +; + *----------------------------------------------------------------------------*/ +#define __CMSEVENEER_SIZE 0x200 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + + +/*---------------------------------------------------------------------------- + Region base & size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) +#define __CV_SIZE ( __CMSEVENEER_SIZE ) +#else +#define __CV_SIZE ( 0 ) +#endif + +#define __RO_BASE ( __ROM_BASE ) +#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) + +#define __RW_BASE ( __RAM_BASE ) +#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) + + +/*---------------------------------------------------------------------------- + Scatter Region definition + *----------------------------------------------------------------------------*/ +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Venners + ER_CMSE_VENEER __CV_BASE __CV_SIZE { + *(Veneer$$CMSE) + } +} +#endif diff --git a/RTE/Device/IOTKit_CM23_VHT/partition_IOTKit_CM23.h b/RTE/Device/IOTKit_CM23_VHT/partition_IOTKit_CM23.h new file mode 100644 index 0000000..c35d740 --- /dev/null +++ b/RTE/Device/IOTKit_CM23_VHT/partition_IOTKit_CM23.h @@ -0,0 +1,585 @@ +/****************************************************************************** + * @file partition_IOTKit_CM23.h + * @brief CMSIS-Core Initial Setup for Secure / Non-Secure Zones for IOTKit_CM23 + ******************************************************************************/ +/* Copyright (c) 2015 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifndef PARTITION_IOTKit_CM23_H +#define PARTITION_IOTKit_CM23_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x10000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x101FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x003FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x28200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x283FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x403FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 0 + +/* +// Interrupts 0..31 +// Non-Secure Watchdog Reset Request <0=> Secure state <1=> Non-Secure state +// Non-Secure Watchdog interrupt <0=> Secure state <1=> Non-Secure state +// S32K Timer interrupt <0=> Secure state <1=> Non-Secure state +// Timer 0 interrupt <0=> Secure state <1=> Non-Secure state +// Timer 1 interrupt <0=> Secure state <1=> Non-Secure state +// Dual Timer interrupt <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 0 + +/* +// Interrupts 32..63 +// UART 0 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 0 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 1 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 1 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 2 teceive interrupt <0=> Secure state <1=> Non-Secure state +// UART 2 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 3 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 3 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 4 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 4 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 0 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 1 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 2 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 3 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 4 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 0, 1, 2, 3, 4 overflow interrupt <0=> Secure state <1=> Non-Secure state +// Ethernet interrupt <0=> Secure state <1=> Non-Secure state +// Audio I2S interrupt <0=> Secure state <1=> Non-Secure state +// Touch Screen interrupt <0=> Secure state <1=> Non-Secure state +// SPI 0 (SPI Header) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 1 (CLCD) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 2 (Shield ADC) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 3 (Shield 0 SPI) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 4 (Shield 1 SPI) interrupt <0=> Secure state <1=> Non-Secure state +// DMA 0 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 0 terminal count interrupt <0=> Secure state <1=> Non-Secure state +// DMA 0 combined interrupt <0=> Secure state <1=> Non-Secure state +// DMA 1 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 1 terminal count interrupt <0=> Secure state <1=> Non-Secure state +// DMA 1 combined interrupt <0=> Secure state <1=> Non-Secure state +// DMA 2 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 2 terminal count interrupt <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// DMA 2 combined interrupt <0=> Secure state <1=> Non-Secure state +// DMA 3 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 3 terminal count interrupt <0=> Secure state <1=> Non-Secure state +// DMA 3 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 0 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 1 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 2 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 3 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (10) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (11) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (12) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (13) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (14) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (15) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// GPIO 1 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (10) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (11) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (12) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (13) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (14) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (15) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (10) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (11) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (12) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (13) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (14) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (15) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif /* PARTITION_IOTKit_CM23_H */ diff --git a/RTE/Device/IOTKit_CM23_VHT/partition_IOTKit_CM23.h.base@1.0.0 b/RTE/Device/IOTKit_CM23_VHT/partition_IOTKit_CM23.h.base@1.0.0 new file mode 100644 index 0000000..c35d740 --- /dev/null +++ b/RTE/Device/IOTKit_CM23_VHT/partition_IOTKit_CM23.h.base@1.0.0 @@ -0,0 +1,585 @@ +/****************************************************************************** + * @file partition_IOTKit_CM23.h + * @brief CMSIS-Core Initial Setup for Secure / Non-Secure Zones for IOTKit_CM23 + ******************************************************************************/ +/* Copyright (c) 2015 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifndef PARTITION_IOTKit_CM23_H +#define PARTITION_IOTKit_CM23_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x10000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x101FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x003FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x28200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x283FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x403FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 0 + +/* +// Interrupts 0..31 +// Non-Secure Watchdog Reset Request <0=> Secure state <1=> Non-Secure state +// Non-Secure Watchdog interrupt <0=> Secure state <1=> Non-Secure state +// S32K Timer interrupt <0=> Secure state <1=> Non-Secure state +// Timer 0 interrupt <0=> Secure state <1=> Non-Secure state +// Timer 1 interrupt <0=> Secure state <1=> Non-Secure state +// Dual Timer interrupt <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 0 + +/* +// Interrupts 32..63 +// UART 0 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 0 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 1 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 1 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 2 teceive interrupt <0=> Secure state <1=> Non-Secure state +// UART 2 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 3 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 3 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 4 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 4 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 0 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 1 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 2 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 3 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 4 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 0, 1, 2, 3, 4 overflow interrupt <0=> Secure state <1=> Non-Secure state +// Ethernet interrupt <0=> Secure state <1=> Non-Secure state +// Audio I2S interrupt <0=> Secure state <1=> Non-Secure state +// Touch Screen interrupt <0=> Secure state <1=> Non-Secure state +// SPI 0 (SPI Header) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 1 (CLCD) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 2 (Shield ADC) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 3 (Shield 0 SPI) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 4 (Shield 1 SPI) interrupt <0=> Secure state <1=> Non-Secure state +// DMA 0 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 0 terminal count interrupt <0=> Secure state <1=> Non-Secure state +// DMA 0 combined interrupt <0=> Secure state <1=> Non-Secure state +// DMA 1 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 1 terminal count interrupt <0=> Secure state <1=> Non-Secure state +// DMA 1 combined interrupt <0=> Secure state <1=> Non-Secure state +// DMA 2 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 2 terminal count interrupt <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// DMA 2 combined interrupt <0=> Secure state <1=> Non-Secure state +// DMA 3 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 3 terminal count interrupt <0=> Secure state <1=> Non-Secure state +// DMA 3 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 0 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 1 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 2 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 3 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (10) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (11) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (12) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (13) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (14) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (15) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// GPIO 1 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (10) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (11) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (12) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (13) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (14) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (15) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (10) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (11) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (12) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (13) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (14) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (15) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif /* PARTITION_IOTKit_CM23_H */ diff --git a/RTE/Device/IOTKit_CM23_VHT/startup_IOTKit_CM23.c b/RTE/Device/IOTKit_CM23_VHT/startup_IOTKit_CM23.c new file mode 100644 index 0000000..c71b36b --- /dev/null +++ b/RTE/Device/IOTKit_CM23_VHT/startup_IOTKit_CM23.c @@ -0,0 +1,506 @@ +/****************************************************************************** + * @file startup_IOTKit_CM23.c + * @brief CMSIS Startup File for IOTKit_CM23 Device + ******************************************************************************/ +/* Copyright (c) 2015 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (IOTKit_CM23) || defined (IOTKit_CM23_VHT) + #include "IOTKit_CM23.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Core IoT Interrupts */ +void NONSEC_WATCHDOG_RESET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void NONSEC_WATCHDOG_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void S32K_TIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BRIDGE_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* External Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UARTOVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA0_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA0_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA1_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA1_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA3_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA3_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* VSI Interrupts */ +#if defined (IOTKit_CM23_VHT) +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Core IoT Interrupts */ + NONSEC_WATCHDOG_RESET_Handler, /* 0 Non-Secure Watchdog Reset Handler */ + NONSEC_WATCHDOG_Handler, /* 1 Non-Secure Watchdog Handler */ + S32K_TIMER_Handler, /* 2 S32K Timer Handler */ + TIMER0_Handler, /* 3 TIMER 0 Handler */ + TIMER1_Handler, /* 4 TIMER 1 Handler */ + DUALTIMER_Handler, /* 5 Dual Timer Handler */ + 0, /* 6 Reserved */ + 0, /* 7 Reserved */ + 0, /* 8 Reserved */ + MPC_Handler, /* 9 MPC Combined (Secure) Handler */ + PPC_Handler, /* 10 PPC Combined (Secure) Handler */ + MSC_Handler, /* 11 MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12 Bridge Error Combined (Secure) Handler */ + 0, /* 13 Reserved */ + 0, /* 14 Reserved */ + 0, /* 15 Reserved */ + 0, /* 16 Reserved */ + 0, /* 17 Reserved */ + 0, /* 18 Reserved */ + 0, /* 19 Reserved */ + 0, /* 20 Reserved */ + 0, /* 21 Reserved */ + 0, /* 22 Reserved */ + 0, /* 23 Reserved */ + 0, /* 24 Reserved */ + 0, /* 25 Reserved */ + 0, /* 26 Reserved */ + 0, /* 27 Reserved */ + 0, /* 28 Reserved */ + 0, /* 29 Reserved */ + 0, /* 30 Reserved */ + 0, /* 31 Reserved */ + + /* External Interrupts */ + UART0RX_Handler, /* 32 UART 0 RX Handler */ + UART0TX_Handler, /* 33 UART 0 TX Handler */ + UART1RX_Handler, /* 34 UART 1 RX Handler */ + UART1TX_Handler, /* 35 UART 1 TX Handler */ + UART2RX_Handler, /* 36 UART 2 RX Handler */ + UART2TX_Handler, /* 37 UART 2 TX Handler */ + UART3RX_Handler, /* 38 UART 2 RX Handler */ + UART3TX_Handler, /* 39 UART 2 TX Handler */ + UART4RX_Handler, /* 40 UART 2 RX Handler */ + UART4TX_Handler, /* 41 UART 2 TX Handler */ + UART0_Handler, /* 42 UART 0 combined Handler */ + UART1_Handler, /* 43 UART 1 combined Handler */ + UART2_Handler, /* 44 UART 2 combined Handler */ + UART3_Handler, /* 45 UART 3 combined Handler */ + UART4_Handler, /* 46 UART 4 combined Handler */ + UARTOVF_Handler, /* 47 UART 0,1,2,3,4 Overflow Handler */ + ETHERNET_Handler , /* 48 Ethernet Handler */ + I2S_Handler, /* 49 I2S Handler */ + TSC_Handler, /* 50 Touch Screen Handler */ + SPI0_Handler, /* 51 SPI 0 Handler */ + SPI1_Handler, /* 52 SPI 1 Handler */ + SPI2_Handler, /* 53 SPI 2 Handler */ + SPI3_Handler, /* 54 SPI 3 Handler */ + SPI4_Handler, /* 55 SPI 4 Handler */ + DMA0_ERROR_Handler, /* 56 DMA 0 Error Handler */ + DMA0_TC_Handler, /* 57 DMA 0 Terminal Count Handler */ + DMA0_Handler, /* 58 DMA 0 Combined Handler */ + DMA1_ERROR_Handler, /* 59 DMA 1 Error Handler */ + DMA1_TC_Handler, /* 60 DMA 1 Terminal Count Handler */ + DMA1_Handler, /* 61 DMA 1 Combined Handler */ + DMA2_ERROR_Handler, /* 62 DMA 2 Error Handler */ + DMA2_TC_Handler, /* 63 DMA 2 Terminal Count Handler */ + DMA2_Handler, /* 64 DMA 2 Combined Handler */ + DMA3_ERROR_Handler, /* 65 DMA 3 Error Handler */ + DMA3_TC_Handler, /* 66 DMA 3 Terminal Count Handler */ + DMA3_Handler, /* 67 DMA 3 Combined Handler */ + GPIO0_Handler, /* 68 GPIO 0 Combined Handler */ + GPIO1_Handler, /* 69 GPIO 1 Combined Handler */ + GPIO2_Handler, /* 70 GPIO 2 Combined Handler */ + GPIO3_Handler, /* 71 GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 72 */ /* All P0 I/O pins used as irq source */ + GPIO0_1_Handler, /* 73 */ /* There are 16 pins in total */ + GPIO0_2_Handler, /* 74 */ + GPIO0_3_Handler, /* 75 */ + GPIO0_4_Handler, /* 76 */ + GPIO0_5_Handler, /* 77 */ + GPIO0_6_Handler, /* 78 */ + GPIO0_7_Handler, /* 79 */ + GPIO0_8_Handler, /* 80 */ + GPIO0_9_Handler, /* 81 */ + GPIO0_10_Handler, /* 82 */ + GPIO0_11_Handler, /* 83 */ + GPIO0_12_Handler, /* 84 */ + GPIO0_13_Handler, /* 85 */ + GPIO0_14_Handler, /* 86 */ + GPIO0_15_Handler, /* 87 */ + GPIO1_0_Handler, /* 88 */ /* All P1 I/O pins used as irq source */ + GPIO1_1_Handler, /* 89 */ /* There are 16 pins in total */ + GPIO1_2_Handler, /* 90 */ + GPIO1_3_Handler, /* 91 */ + GPIO1_4_Handler, /* 92 */ + GPIO1_5_Handler, /* 93 */ + GPIO1_6_Handler, /* 94 */ + GPIO1_7_Handler, /* 95 */ + GPIO1_8_Handler, /* 96 */ + GPIO1_9_Handler, /* 97 */ + GPIO1_10_Handler, /* 98 */ + GPIO1_11_Handler, /* 99 */ + GPIO1_12_Handler, /* 100 */ + GPIO1_13_Handler, /* 101 */ + GPIO1_14_Handler, /* 102 */ + GPIO1_15_Handler, /* 103 */ + GPIO2_0_Handler, /* 104 */ /* All P2 I/O pins used as irq source */ + GPIO2_1_Handler, /* 105 */ /* There are 16 pins in total */ + GPIO2_2_Handler, /* 106 */ + GPIO2_3_Handler, /* 107 */ + GPIO2_4_Handler, /* 108 */ + GPIO2_5_Handler, /* 109 */ + GPIO2_6_Handler, /* 110 */ + GPIO2_7_Handler, /* 111 */ + GPIO2_8_Handler, /* 112 */ + GPIO2_9_Handler, /* 113 */ + GPIO2_10_Handler, /* 114 */ + GPIO2_11_Handler, /* 115 */ + GPIO2_12_Handler, /* 116 */ + GPIO2_13_Handler, /* 117 */ + GPIO2_14_Handler, /* 118 */ + GPIO2_15_Handler, /* 119 */ + GPIO3_0_Handler, /* 120 */ /* All P3 I/O pins used as irq source */ + GPIO3_1_Handler, /* 121 */ /* There are 4 pins in total */ + GPIO3_2_Handler, /* 122 */ + GPIO3_3_Handler, /* 123 */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined (IOTKit_CM23_VHT) + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/IOTKit_CM23_VHT/startup_IOTKit_CM23.c.base@1.2.0 b/RTE/Device/IOTKit_CM23_VHT/startup_IOTKit_CM23.c.base@1.2.0 new file mode 100644 index 0000000..c71b36b --- /dev/null +++ b/RTE/Device/IOTKit_CM23_VHT/startup_IOTKit_CM23.c.base@1.2.0 @@ -0,0 +1,506 @@ +/****************************************************************************** + * @file startup_IOTKit_CM23.c + * @brief CMSIS Startup File for IOTKit_CM23 Device + ******************************************************************************/ +/* Copyright (c) 2015 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (IOTKit_CM23) || defined (IOTKit_CM23_VHT) + #include "IOTKit_CM23.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Core IoT Interrupts */ +void NONSEC_WATCHDOG_RESET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void NONSEC_WATCHDOG_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void S32K_TIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BRIDGE_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* External Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UARTOVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA0_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA0_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA1_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA1_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA3_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA3_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* VSI Interrupts */ +#if defined (IOTKit_CM23_VHT) +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Core IoT Interrupts */ + NONSEC_WATCHDOG_RESET_Handler, /* 0 Non-Secure Watchdog Reset Handler */ + NONSEC_WATCHDOG_Handler, /* 1 Non-Secure Watchdog Handler */ + S32K_TIMER_Handler, /* 2 S32K Timer Handler */ + TIMER0_Handler, /* 3 TIMER 0 Handler */ + TIMER1_Handler, /* 4 TIMER 1 Handler */ + DUALTIMER_Handler, /* 5 Dual Timer Handler */ + 0, /* 6 Reserved */ + 0, /* 7 Reserved */ + 0, /* 8 Reserved */ + MPC_Handler, /* 9 MPC Combined (Secure) Handler */ + PPC_Handler, /* 10 PPC Combined (Secure) Handler */ + MSC_Handler, /* 11 MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12 Bridge Error Combined (Secure) Handler */ + 0, /* 13 Reserved */ + 0, /* 14 Reserved */ + 0, /* 15 Reserved */ + 0, /* 16 Reserved */ + 0, /* 17 Reserved */ + 0, /* 18 Reserved */ + 0, /* 19 Reserved */ + 0, /* 20 Reserved */ + 0, /* 21 Reserved */ + 0, /* 22 Reserved */ + 0, /* 23 Reserved */ + 0, /* 24 Reserved */ + 0, /* 25 Reserved */ + 0, /* 26 Reserved */ + 0, /* 27 Reserved */ + 0, /* 28 Reserved */ + 0, /* 29 Reserved */ + 0, /* 30 Reserved */ + 0, /* 31 Reserved */ + + /* External Interrupts */ + UART0RX_Handler, /* 32 UART 0 RX Handler */ + UART0TX_Handler, /* 33 UART 0 TX Handler */ + UART1RX_Handler, /* 34 UART 1 RX Handler */ + UART1TX_Handler, /* 35 UART 1 TX Handler */ + UART2RX_Handler, /* 36 UART 2 RX Handler */ + UART2TX_Handler, /* 37 UART 2 TX Handler */ + UART3RX_Handler, /* 38 UART 2 RX Handler */ + UART3TX_Handler, /* 39 UART 2 TX Handler */ + UART4RX_Handler, /* 40 UART 2 RX Handler */ + UART4TX_Handler, /* 41 UART 2 TX Handler */ + UART0_Handler, /* 42 UART 0 combined Handler */ + UART1_Handler, /* 43 UART 1 combined Handler */ + UART2_Handler, /* 44 UART 2 combined Handler */ + UART3_Handler, /* 45 UART 3 combined Handler */ + UART4_Handler, /* 46 UART 4 combined Handler */ + UARTOVF_Handler, /* 47 UART 0,1,2,3,4 Overflow Handler */ + ETHERNET_Handler , /* 48 Ethernet Handler */ + I2S_Handler, /* 49 I2S Handler */ + TSC_Handler, /* 50 Touch Screen Handler */ + SPI0_Handler, /* 51 SPI 0 Handler */ + SPI1_Handler, /* 52 SPI 1 Handler */ + SPI2_Handler, /* 53 SPI 2 Handler */ + SPI3_Handler, /* 54 SPI 3 Handler */ + SPI4_Handler, /* 55 SPI 4 Handler */ + DMA0_ERROR_Handler, /* 56 DMA 0 Error Handler */ + DMA0_TC_Handler, /* 57 DMA 0 Terminal Count Handler */ + DMA0_Handler, /* 58 DMA 0 Combined Handler */ + DMA1_ERROR_Handler, /* 59 DMA 1 Error Handler */ + DMA1_TC_Handler, /* 60 DMA 1 Terminal Count Handler */ + DMA1_Handler, /* 61 DMA 1 Combined Handler */ + DMA2_ERROR_Handler, /* 62 DMA 2 Error Handler */ + DMA2_TC_Handler, /* 63 DMA 2 Terminal Count Handler */ + DMA2_Handler, /* 64 DMA 2 Combined Handler */ + DMA3_ERROR_Handler, /* 65 DMA 3 Error Handler */ + DMA3_TC_Handler, /* 66 DMA 3 Terminal Count Handler */ + DMA3_Handler, /* 67 DMA 3 Combined Handler */ + GPIO0_Handler, /* 68 GPIO 0 Combined Handler */ + GPIO1_Handler, /* 69 GPIO 1 Combined Handler */ + GPIO2_Handler, /* 70 GPIO 2 Combined Handler */ + GPIO3_Handler, /* 71 GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 72 */ /* All P0 I/O pins used as irq source */ + GPIO0_1_Handler, /* 73 */ /* There are 16 pins in total */ + GPIO0_2_Handler, /* 74 */ + GPIO0_3_Handler, /* 75 */ + GPIO0_4_Handler, /* 76 */ + GPIO0_5_Handler, /* 77 */ + GPIO0_6_Handler, /* 78 */ + GPIO0_7_Handler, /* 79 */ + GPIO0_8_Handler, /* 80 */ + GPIO0_9_Handler, /* 81 */ + GPIO0_10_Handler, /* 82 */ + GPIO0_11_Handler, /* 83 */ + GPIO0_12_Handler, /* 84 */ + GPIO0_13_Handler, /* 85 */ + GPIO0_14_Handler, /* 86 */ + GPIO0_15_Handler, /* 87 */ + GPIO1_0_Handler, /* 88 */ /* All P1 I/O pins used as irq source */ + GPIO1_1_Handler, /* 89 */ /* There are 16 pins in total */ + GPIO1_2_Handler, /* 90 */ + GPIO1_3_Handler, /* 91 */ + GPIO1_4_Handler, /* 92 */ + GPIO1_5_Handler, /* 93 */ + GPIO1_6_Handler, /* 94 */ + GPIO1_7_Handler, /* 95 */ + GPIO1_8_Handler, /* 96 */ + GPIO1_9_Handler, /* 97 */ + GPIO1_10_Handler, /* 98 */ + GPIO1_11_Handler, /* 99 */ + GPIO1_12_Handler, /* 100 */ + GPIO1_13_Handler, /* 101 */ + GPIO1_14_Handler, /* 102 */ + GPIO1_15_Handler, /* 103 */ + GPIO2_0_Handler, /* 104 */ /* All P2 I/O pins used as irq source */ + GPIO2_1_Handler, /* 105 */ /* There are 16 pins in total */ + GPIO2_2_Handler, /* 106 */ + GPIO2_3_Handler, /* 107 */ + GPIO2_4_Handler, /* 108 */ + GPIO2_5_Handler, /* 109 */ + GPIO2_6_Handler, /* 110 */ + GPIO2_7_Handler, /* 111 */ + GPIO2_8_Handler, /* 112 */ + GPIO2_9_Handler, /* 113 */ + GPIO2_10_Handler, /* 114 */ + GPIO2_11_Handler, /* 115 */ + GPIO2_12_Handler, /* 116 */ + GPIO2_13_Handler, /* 117 */ + GPIO2_14_Handler, /* 118 */ + GPIO2_15_Handler, /* 119 */ + GPIO3_0_Handler, /* 120 */ /* All P3 I/O pins used as irq source */ + GPIO3_1_Handler, /* 121 */ /* There are 4 pins in total */ + GPIO3_2_Handler, /* 122 */ + GPIO3_3_Handler, /* 123 */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined (IOTKit_CM23_VHT) + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/IOTKit_CM23_VHT/system_IOTKit_CM23.c b/RTE/Device/IOTKit_CM23_VHT/system_IOTKit_CM23.c new file mode 100644 index 0000000..ee8f3d7 --- /dev/null +++ b/RTE/Device/IOTKit_CM23_VHT/system_IOTKit_CM23.c @@ -0,0 +1,132 @@ +/****************************************************************************** + * @file system_IOTKit_CM23.c + * @brief CMSIS Device System Source File for IOTKit_CM23 Device + ******************************************************************************/ +/* Copyright (c) 2015 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (IOTKit_CM23) || defined (IOTKit_CM23_VHT) + #include "IOTKit_CM23.h" +#else + #error device not specified! +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_IOTKit_CM23.h" +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +// uint32_t blk_cfg, blk_max, blk_size, blk_cnt; +#endif + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* start IOT Green configuration ------------------------- */ + + /* configure MPC --------------- */ + + /* configure unsecure code area MPSSSRAM1 (0x00200000 - 0x003FFFFF) */ +// blk_max = IOTKIT_MPCSSRAM1->BLK_MAX; /* = 0x1 */ +// blk_cfg = IOTKIT_MPCSSRAM1->BLK_CFG; /* = 0xC */ +// blk_size = 1UL << (blk_cfg + 5U); /* = 0x20000 */ +// blk_cnt = 0x200000U / blk_size; /* = 0x10 */ + + IOTKIT_MPCSSRAM1->CTRL &= ~(1UL << 8U); /* clear auto increment */ + IOTKIT_MPCSSRAM1->BLK_IDX = 0; /* write LUT index */ + IOTKIT_MPCSSRAM1->BLK_LUT = 0xFFFF0000UL; /* configure blocks */ + + + /* configure unsecure data area MPSSSRAM3 (0x28200000 - 0x283FFFFF) */ +// blk_max = IOTKIT_MPCSSRAM3->BLK_MAX; /* = 0x1 */ +// blk_cfg = IOTKIT_MPCSSRAM3->BLK_CFG; /* = 0xB */ +// blk_size = 1UL << (blk_cfg + 5U); /* = 0x10000 */ +// blk_cnt = 0x200000U / blk_size; /* = 0x20 */ + + IOTKIT_MPCSSRAM3->CTRL &= ~(1UL << 8U); /* clear auto increment */ + IOTKIT_MPCSSRAM3->BLK_IDX = 1; /* write LUT index */ + IOTKIT_MPCSSRAM3->BLK_LUT = 0xFFFFFFFFUL; /* configure blocks */ + + + + /* enable the Non Secure Callable Configuration for IDAU (NSCCFG register) */ + IOTKIT_SPC->NSCCFG |= 1U; + + + /* configure PPC --------------- */ +#if !defined (__USE_SECURE) + /* Allow Non-secure access for SCC/FPGAIO registers */ + IOTKIT_SPC->APBNSPPCEXP[2U] |= ((1UL << 0U) | + (1UL << 2U) ); + /* Allow Non-secure access for SPI1/UART0 registers */ + IOTKIT_SPC->APBNSPPCEXP[1U] |= ((1UL << 1U) | + (1UL << 5U) ); +#endif + +/* end IOT Green configuration --------------------------- */ + + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/IOTKit_CM23_VHT/system_IOTKit_CM23.c.base@1.2.0 b/RTE/Device/IOTKit_CM23_VHT/system_IOTKit_CM23.c.base@1.2.0 new file mode 100644 index 0000000..ee8f3d7 --- /dev/null +++ b/RTE/Device/IOTKit_CM23_VHT/system_IOTKit_CM23.c.base@1.2.0 @@ -0,0 +1,132 @@ +/****************************************************************************** + * @file system_IOTKit_CM23.c + * @brief CMSIS Device System Source File for IOTKit_CM23 Device + ******************************************************************************/ +/* Copyright (c) 2015 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (IOTKit_CM23) || defined (IOTKit_CM23_VHT) + #include "IOTKit_CM23.h" +#else + #error device not specified! +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_IOTKit_CM23.h" +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +// uint32_t blk_cfg, blk_max, blk_size, blk_cnt; +#endif + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* start IOT Green configuration ------------------------- */ + + /* configure MPC --------------- */ + + /* configure unsecure code area MPSSSRAM1 (0x00200000 - 0x003FFFFF) */ +// blk_max = IOTKIT_MPCSSRAM1->BLK_MAX; /* = 0x1 */ +// blk_cfg = IOTKIT_MPCSSRAM1->BLK_CFG; /* = 0xC */ +// blk_size = 1UL << (blk_cfg + 5U); /* = 0x20000 */ +// blk_cnt = 0x200000U / blk_size; /* = 0x10 */ + + IOTKIT_MPCSSRAM1->CTRL &= ~(1UL << 8U); /* clear auto increment */ + IOTKIT_MPCSSRAM1->BLK_IDX = 0; /* write LUT index */ + IOTKIT_MPCSSRAM1->BLK_LUT = 0xFFFF0000UL; /* configure blocks */ + + + /* configure unsecure data area MPSSSRAM3 (0x28200000 - 0x283FFFFF) */ +// blk_max = IOTKIT_MPCSSRAM3->BLK_MAX; /* = 0x1 */ +// blk_cfg = IOTKIT_MPCSSRAM3->BLK_CFG; /* = 0xB */ +// blk_size = 1UL << (blk_cfg + 5U); /* = 0x10000 */ +// blk_cnt = 0x200000U / blk_size; /* = 0x20 */ + + IOTKIT_MPCSSRAM3->CTRL &= ~(1UL << 8U); /* clear auto increment */ + IOTKIT_MPCSSRAM3->BLK_IDX = 1; /* write LUT index */ + IOTKIT_MPCSSRAM3->BLK_LUT = 0xFFFFFFFFUL; /* configure blocks */ + + + + /* enable the Non Secure Callable Configuration for IDAU (NSCCFG register) */ + IOTKIT_SPC->NSCCFG |= 1U; + + + /* configure PPC --------------- */ +#if !defined (__USE_SECURE) + /* Allow Non-secure access for SCC/FPGAIO registers */ + IOTKIT_SPC->APBNSPPCEXP[2U] |= ((1UL << 0U) | + (1UL << 2U) ); + /* Allow Non-secure access for SPI1/UART0 registers */ + IOTKIT_SPC->APBNSPPCEXP[1U] |= ((1UL << 1U) | + (1UL << 5U) ); +#endif + +/* end IOT Green configuration --------------------------- */ + + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/IOTKit_CM33_FP_VHT/RTE_Device.h.base@1.0.0 b/RTE/Device/IOTKit_CM33_FP_VHT/RTE_Device.h.base@1.0.0 new file mode 100644 index 0000000..786b74f --- /dev/null +++ b/RTE/Device/IOTKit_CM33_FP_VHT/RTE_Device.h.base@1.0.0 @@ -0,0 +1,50 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 25. April 2016 + * $Revision: V1.0.0 + * + * Project: RTE Device Configuration for ARM CMSDK_CM device + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_USART0 0 + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_UART2 0 + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_UART3 0 + +#endif /* __RTE_DEVICE_H */ diff --git a/RTE/Device/IOTKit_CM33_FP_VHT/ac6_arm.sct b/RTE/Device/IOTKit_CM33_FP_VHT/ac6_arm.sct new file mode 100644 index 0000000..2682594 --- /dev/null +++ b/RTE/Device/IOTKit_CM33_FP_VHT/ac6_arm.sct @@ -0,0 +1,119 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc +; command above MUST be in first line (no comment above!) + +;Note: Add '-mcmse' to first line if your software model is "Secure Mode". +; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse + + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x10000000 +#define __ROM_SIZE 0x00200000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x38000000 +#define __RAM_SIZE 0x00200000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00000C00 + +/*--------------------- CMSE Venner Configuration --------------------------- +; CMSE Venner Configuration +; CMSE Venner Size (in Bytes) <0x0-0xFFFFFFFF:32> +; + *----------------------------------------------------------------------------*/ +#define __CMSEVENEER_SIZE 0x200 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + + +/*---------------------------------------------------------------------------- + Region base & size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) +#define __CV_SIZE ( __CMSEVENEER_SIZE ) +#else +#define __CV_SIZE ( 0 ) +#endif + +#define __RO_BASE ( __ROM_BASE ) +#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) + +#define __RW_BASE ( __RAM_BASE ) +#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) + + +/*---------------------------------------------------------------------------- + Scatter Region definition + *----------------------------------------------------------------------------*/ +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Venners + ER_CMSE_VENEER __CV_BASE __CV_SIZE { + *(Veneer$$CMSE) + } +} +#endif diff --git a/RTE/Device/IOTKit_CM33_FP_VHT/ac6_arm.sct.base@1.0.0 b/RTE/Device/IOTKit_CM33_FP_VHT/ac6_arm.sct.base@1.0.0 new file mode 100644 index 0000000..2682594 --- /dev/null +++ b/RTE/Device/IOTKit_CM33_FP_VHT/ac6_arm.sct.base@1.0.0 @@ -0,0 +1,119 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc +; command above MUST be in first line (no comment above!) + +;Note: Add '-mcmse' to first line if your software model is "Secure Mode". +; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse + + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x10000000 +#define __ROM_SIZE 0x00200000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x38000000 +#define __RAM_SIZE 0x00200000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00000C00 + +/*--------------------- CMSE Venner Configuration --------------------------- +; CMSE Venner Configuration +; CMSE Venner Size (in Bytes) <0x0-0xFFFFFFFF:32> +; + *----------------------------------------------------------------------------*/ +#define __CMSEVENEER_SIZE 0x200 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + + +/*---------------------------------------------------------------------------- + Region base & size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) +#define __CV_SIZE ( __CMSEVENEER_SIZE ) +#else +#define __CV_SIZE ( 0 ) +#endif + +#define __RO_BASE ( __ROM_BASE ) +#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) + +#define __RW_BASE ( __RAM_BASE ) +#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) + + +/*---------------------------------------------------------------------------- + Scatter Region definition + *----------------------------------------------------------------------------*/ +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Venners + ER_CMSE_VENEER __CV_BASE __CV_SIZE { + *(Veneer$$CMSE) + } +} +#endif diff --git a/RTE/Device/IOTKit_CM33_FP_VHT/partition_IOTKit_CM33.h b/RTE/Device/IOTKit_CM33_FP_VHT/partition_IOTKit_CM33.h new file mode 100644 index 0000000..45cb6ed --- /dev/null +++ b/RTE/Device/IOTKit_CM33_FP_VHT/partition_IOTKit_CM33.h @@ -0,0 +1,637 @@ +/****************************************************************************** + * @file partition_IOTKit_CM33.h + * @brief CMSIS-Core Initial Setup for Secure / Non-Secure Zones for IOTKit_CM33 + ******************************************************************************/ +/* Copyright (c) 2015 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifndef PARTITION_IOTKit_CM33_H +#define PARTITION_IOTKit_CM33_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x10000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x101FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x003FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x28200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x283FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x403FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 0 + +/* +// Interrupts 0..31 +// Non-Secure Watchdog Reset Request <0=> Secure state <1=> Non-Secure state +// Non-Secure Watchdog interrupt <0=> Secure state <1=> Non-Secure state +// S32K Timer interrupt <0=> Secure state <1=> Non-Secure state +// Timer 0 interrupt <0=> Secure state <1=> Non-Secure state +// Timer 1 interrupt <0=> Secure state <1=> Non-Secure state +// Dual Timer interrupt <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 0 + +/* +// Interrupts 32..63 +// UART 0 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 0 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 1 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 1 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 2 teceive interrupt <0=> Secure state <1=> Non-Secure state +// UART 2 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 3 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 3 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 4 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 4 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 0 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 1 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 2 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 3 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 4 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 0, 1, 2, 3, 4 overflow interrupt <0=> Secure state <1=> Non-Secure state +// Ethernet interrupt <0=> Secure state <1=> Non-Secure state +// Audio I2S interrupt <0=> Secure state <1=> Non-Secure state +// Touch Screen interrupt <0=> Secure state <1=> Non-Secure state +// SPI 0 (SPI Header) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 1 (CLCD) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 2 (Shield ADC) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 3 (Shield 0 SPI) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 4 (Shield 1 SPI) interrupt <0=> Secure state <1=> Non-Secure state +// DMA 0 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 0 terminal count interrupt <0=> Secure state <1=> Non-Secure state +// DMA 0 combined interrupt <0=> Secure state <1=> Non-Secure state +// DMA 1 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 1 terminal count interrupt <0=> Secure state <1=> Non-Secure state +// DMA 1 combined interrupt <0=> Secure state <1=> Non-Secure state +// DMA 2 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 2 terminal count interrupt <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// DMA 2 combined interrupt <0=> Secure state <1=> Non-Secure state +// DMA 3 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 3 terminal count interrupt <0=> Secure state <1=> Non-Secure state +// DMA 3 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 0 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 1 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 2 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 3 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (10) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (11) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (12) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (13) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (14) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (15) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// GPIO 1 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (10) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (11) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (12) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (13) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (14) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (15) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (10) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (11) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (12) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (13) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (14) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (15) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif /* PARTITION_IOTKit_CM33_H */ diff --git a/RTE/Device/IOTKit_CM33_FP_VHT/partition_IOTKit_CM33.h.base@1.0.0 b/RTE/Device/IOTKit_CM33_FP_VHT/partition_IOTKit_CM33.h.base@1.0.0 new file mode 100644 index 0000000..45cb6ed --- /dev/null +++ b/RTE/Device/IOTKit_CM33_FP_VHT/partition_IOTKit_CM33.h.base@1.0.0 @@ -0,0 +1,637 @@ +/****************************************************************************** + * @file partition_IOTKit_CM33.h + * @brief CMSIS-Core Initial Setup for Secure / Non-Secure Zones for IOTKit_CM33 + ******************************************************************************/ +/* Copyright (c) 2015 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifndef PARTITION_IOTKit_CM33_H +#define PARTITION_IOTKit_CM33_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x10000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x101FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x003FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x28200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x283FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x403FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 0 + +/* +// Interrupts 0..31 +// Non-Secure Watchdog Reset Request <0=> Secure state <1=> Non-Secure state +// Non-Secure Watchdog interrupt <0=> Secure state <1=> Non-Secure state +// S32K Timer interrupt <0=> Secure state <1=> Non-Secure state +// Timer 0 interrupt <0=> Secure state <1=> Non-Secure state +// Timer 1 interrupt <0=> Secure state <1=> Non-Secure state +// Dual Timer interrupt <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 0 + +/* +// Interrupts 32..63 +// UART 0 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 0 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 1 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 1 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 2 teceive interrupt <0=> Secure state <1=> Non-Secure state +// UART 2 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 3 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 3 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 4 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 4 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 0 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 1 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 2 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 3 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 4 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 0, 1, 2, 3, 4 overflow interrupt <0=> Secure state <1=> Non-Secure state +// Ethernet interrupt <0=> Secure state <1=> Non-Secure state +// Audio I2S interrupt <0=> Secure state <1=> Non-Secure state +// Touch Screen interrupt <0=> Secure state <1=> Non-Secure state +// SPI 0 (SPI Header) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 1 (CLCD) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 2 (Shield ADC) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 3 (Shield 0 SPI) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 4 (Shield 1 SPI) interrupt <0=> Secure state <1=> Non-Secure state +// DMA 0 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 0 terminal count interrupt <0=> Secure state <1=> Non-Secure state +// DMA 0 combined interrupt <0=> Secure state <1=> Non-Secure state +// DMA 1 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 1 terminal count interrupt <0=> Secure state <1=> Non-Secure state +// DMA 1 combined interrupt <0=> Secure state <1=> Non-Secure state +// DMA 2 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 2 terminal count interrupt <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// DMA 2 combined interrupt <0=> Secure state <1=> Non-Secure state +// DMA 3 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 3 terminal count interrupt <0=> Secure state <1=> Non-Secure state +// DMA 3 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 0 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 1 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 2 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 3 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (10) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (11) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (12) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (13) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (14) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (15) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// GPIO 1 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (10) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (11) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (12) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (13) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (14) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (15) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (10) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (11) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (12) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (13) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (14) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (15) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif /* PARTITION_IOTKit_CM33_H */ diff --git a/RTE/Device/IOTKit_CM33_FP_VHT/startup_IOTKit_CM33.c b/RTE/Device/IOTKit_CM33_FP_VHT/startup_IOTKit_CM33.c new file mode 100644 index 0000000..bb3e1af --- /dev/null +++ b/RTE/Device/IOTKit_CM33_FP_VHT/startup_IOTKit_CM33.c @@ -0,0 +1,513 @@ +/****************************************************************************** + * @file startup_IOTKit_CM33.c + * @brief CMSIS Startup File for IOTKit_CM33 Device + ******************************************************************************/ +/* Copyright (c) 2015 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (IOTKit_CM33) || defined (IOTKit_CM33_VHT) + #include "IOTKit_CM33.h" +#elif defined (IOTKit_CM33_FP) || defined (IOTKit_CM33_FP_VHT) + #include "IOTKit_CM33_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Core IoT Interrupts */ +void NONSEC_WATCHDOG_RESET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void NONSEC_WATCHDOG_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void S32K_TIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BRIDGE_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* External Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UARTOVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA0_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA0_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA1_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA1_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA3_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA3_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* VSI Interrupts */ +#if defined (IOTKit_CM33_VHT) || defined (IOTKit_CM33_FP_VHT) +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Core IoT Interrupts */ + NONSEC_WATCHDOG_RESET_Handler, /* 0 Non-Secure Watchdog Reset Handler */ + NONSEC_WATCHDOG_Handler, /* 1 Non-Secure Watchdog Handler */ + S32K_TIMER_Handler, /* 2 S32K Timer Handler */ + TIMER0_Handler, /* 3 TIMER 0 Handler */ + TIMER1_Handler, /* 4 TIMER 1 Handler */ + DUALTIMER_Handler, /* 5 Dual Timer Handler */ + 0, /* 6 Reserved */ + 0, /* 7 Reserved */ + 0, /* 8 Reserved */ + MPC_Handler, /* 9 MPC Combined (Secure) Handler */ + PPC_Handler, /* 10 PPC Combined (Secure) Handler */ + MSC_Handler, /* 11 MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12 Bridge Error Combined (Secure) Handler */ + 0, /* 13 Reserved */ + 0, /* 14 Reserved */ + 0, /* 15 Reserved */ + 0, /* 16 Reserved */ + 0, /* 17 Reserved */ + 0, /* 18 Reserved */ + 0, /* 19 Reserved */ + 0, /* 20 Reserved */ + 0, /* 21 Reserved */ + 0, /* 22 Reserved */ + 0, /* 23 Reserved */ + 0, /* 24 Reserved */ + 0, /* 25 Reserved */ + 0, /* 26 Reserved */ + 0, /* 27 Reserved */ + 0, /* 28 Reserved */ + 0, /* 29 Reserved */ + 0, /* 30 Reserved */ + 0, /* 31 Reserved */ + + /* External Interrupts */ + UART0RX_Handler, /* 32 UART 0 RX Handler */ + UART0TX_Handler, /* 33 UART 0 TX Handler */ + UART1RX_Handler, /* 34 UART 1 RX Handler */ + UART1TX_Handler, /* 35 UART 1 TX Handler */ + UART2RX_Handler, /* 36 UART 2 RX Handler */ + UART2TX_Handler, /* 37 UART 2 TX Handler */ + UART3RX_Handler, /* 38 UART 2 RX Handler */ + UART3TX_Handler, /* 39 UART 2 TX Handler */ + UART4RX_Handler, /* 40 UART 2 RX Handler */ + UART4TX_Handler, /* 41 UART 2 TX Handler */ + UART0_Handler, /* 42 UART 0 combined Handler */ + UART1_Handler, /* 43 UART 1 combined Handler */ + UART2_Handler, /* 44 UART 2 combined Handler */ + UART3_Handler, /* 45 UART 3 combined Handler */ + UART4_Handler, /* 46 UART 4 combined Handler */ + UARTOVF_Handler, /* 47 UART 0,1,2,3,4 Overflow Handler */ + ETHERNET_Handler , /* 48 Ethernet Handler */ + I2S_Handler, /* 49 I2S Handler */ + TSC_Handler, /* 50 Touch Screen Handler */ + SPI0_Handler, /* 51 SPI 0 Handler */ + SPI1_Handler, /* 52 SPI 1 Handler */ + SPI2_Handler, /* 53 SPI 2 Handler */ + SPI3_Handler, /* 54 SPI 3 Handler */ + SPI4_Handler, /* 55 SPI 4 Handler */ + DMA0_ERROR_Handler, /* 56 DMA 0 Error Handler */ + DMA0_TC_Handler, /* 57 DMA 0 Terminal Count Handler */ + DMA0_Handler, /* 58 DMA 0 Combined Handler */ + DMA1_ERROR_Handler, /* 59 DMA 1 Error Handler */ + DMA1_TC_Handler, /* 60 DMA 1 Terminal Count Handler */ + DMA1_Handler, /* 61 DMA 1 Combined Handler */ + DMA2_ERROR_Handler, /* 62 DMA 2 Error Handler */ + DMA2_TC_Handler, /* 63 DMA 2 Terminal Count Handler */ + DMA2_Handler, /* 64 DMA 2 Combined Handler */ + DMA3_ERROR_Handler, /* 65 DMA 3 Error Handler */ + DMA3_TC_Handler, /* 66 DMA 3 Terminal Count Handler */ + DMA3_Handler, /* 67 DMA 3 Combined Handler */ + GPIO0_Handler, /* 68 GPIO 0 Combined Handler */ + GPIO1_Handler, /* 69 GPIO 1 Combined Handler */ + GPIO2_Handler, /* 70 GPIO 2 Combined Handler */ + GPIO3_Handler, /* 71 GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 72 */ /* All P0 I/O pins used as irq source */ + GPIO0_1_Handler, /* 73 */ /* There are 16 pins in total */ + GPIO0_2_Handler, /* 74 */ + GPIO0_3_Handler, /* 75 */ + GPIO0_4_Handler, /* 76 */ + GPIO0_5_Handler, /* 77 */ + GPIO0_6_Handler, /* 78 */ + GPIO0_7_Handler, /* 79 */ + GPIO0_8_Handler, /* 80 */ + GPIO0_9_Handler, /* 81 */ + GPIO0_10_Handler, /* 82 */ + GPIO0_11_Handler, /* 83 */ + GPIO0_12_Handler, /* 84 */ + GPIO0_13_Handler, /* 85 */ + GPIO0_14_Handler, /* 86 */ + GPIO0_15_Handler, /* 87 */ + GPIO1_0_Handler, /* 88 */ /* All P1 I/O pins used as irq source */ + GPIO1_1_Handler, /* 89 */ /* There are 16 pins in total */ + GPIO1_2_Handler, /* 90 */ + GPIO1_3_Handler, /* 91 */ + GPIO1_4_Handler, /* 92 */ + GPIO1_5_Handler, /* 93 */ + GPIO1_6_Handler, /* 94 */ + GPIO1_7_Handler, /* 95 */ + GPIO1_8_Handler, /* 96 */ + GPIO1_9_Handler, /* 97 */ + GPIO1_10_Handler, /* 98 */ + GPIO1_11_Handler, /* 99 */ + GPIO1_12_Handler, /* 100 */ + GPIO1_13_Handler, /* 101 */ + GPIO1_14_Handler, /* 102 */ + GPIO1_15_Handler, /* 103 */ + GPIO2_0_Handler, /* 104 */ /* All P2 I/O pins used as irq source */ + GPIO2_1_Handler, /* 105 */ /* There are 16 pins in total */ + GPIO2_2_Handler, /* 106 */ + GPIO2_3_Handler, /* 107 */ + GPIO2_4_Handler, /* 108 */ + GPIO2_5_Handler, /* 109 */ + GPIO2_6_Handler, /* 110 */ + GPIO2_7_Handler, /* 111 */ + GPIO2_8_Handler, /* 112 */ + GPIO2_9_Handler, /* 113 */ + GPIO2_10_Handler, /* 114 */ + GPIO2_11_Handler, /* 115 */ + GPIO2_12_Handler, /* 116 */ + GPIO2_13_Handler, /* 117 */ + GPIO2_14_Handler, /* 118 */ + GPIO2_15_Handler, /* 119 */ + GPIO3_0_Handler, /* 120 */ /* All P3 I/O pins used as irq source */ + GPIO3_1_Handler, /* 121 */ /* There are 4 pins in total */ + GPIO3_2_Handler, /* 122 */ + GPIO3_3_Handler, /* 123 */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined (IOTKit_CM33_VHT) || defined (IOTKit_CM33_FP_VHT) + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/IOTKit_CM33_FP_VHT/startup_IOTKit_CM33.c.base@1.2.0 b/RTE/Device/IOTKit_CM33_FP_VHT/startup_IOTKit_CM33.c.base@1.2.0 new file mode 100644 index 0000000..bb3e1af --- /dev/null +++ b/RTE/Device/IOTKit_CM33_FP_VHT/startup_IOTKit_CM33.c.base@1.2.0 @@ -0,0 +1,513 @@ +/****************************************************************************** + * @file startup_IOTKit_CM33.c + * @brief CMSIS Startup File for IOTKit_CM33 Device + ******************************************************************************/ +/* Copyright (c) 2015 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (IOTKit_CM33) || defined (IOTKit_CM33_VHT) + #include "IOTKit_CM33.h" +#elif defined (IOTKit_CM33_FP) || defined (IOTKit_CM33_FP_VHT) + #include "IOTKit_CM33_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Core IoT Interrupts */ +void NONSEC_WATCHDOG_RESET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void NONSEC_WATCHDOG_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void S32K_TIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BRIDGE_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* External Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UARTOVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA0_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA0_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA1_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA1_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA3_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA3_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* VSI Interrupts */ +#if defined (IOTKit_CM33_VHT) || defined (IOTKit_CM33_FP_VHT) +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Core IoT Interrupts */ + NONSEC_WATCHDOG_RESET_Handler, /* 0 Non-Secure Watchdog Reset Handler */ + NONSEC_WATCHDOG_Handler, /* 1 Non-Secure Watchdog Handler */ + S32K_TIMER_Handler, /* 2 S32K Timer Handler */ + TIMER0_Handler, /* 3 TIMER 0 Handler */ + TIMER1_Handler, /* 4 TIMER 1 Handler */ + DUALTIMER_Handler, /* 5 Dual Timer Handler */ + 0, /* 6 Reserved */ + 0, /* 7 Reserved */ + 0, /* 8 Reserved */ + MPC_Handler, /* 9 MPC Combined (Secure) Handler */ + PPC_Handler, /* 10 PPC Combined (Secure) Handler */ + MSC_Handler, /* 11 MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12 Bridge Error Combined (Secure) Handler */ + 0, /* 13 Reserved */ + 0, /* 14 Reserved */ + 0, /* 15 Reserved */ + 0, /* 16 Reserved */ + 0, /* 17 Reserved */ + 0, /* 18 Reserved */ + 0, /* 19 Reserved */ + 0, /* 20 Reserved */ + 0, /* 21 Reserved */ + 0, /* 22 Reserved */ + 0, /* 23 Reserved */ + 0, /* 24 Reserved */ + 0, /* 25 Reserved */ + 0, /* 26 Reserved */ + 0, /* 27 Reserved */ + 0, /* 28 Reserved */ + 0, /* 29 Reserved */ + 0, /* 30 Reserved */ + 0, /* 31 Reserved */ + + /* External Interrupts */ + UART0RX_Handler, /* 32 UART 0 RX Handler */ + UART0TX_Handler, /* 33 UART 0 TX Handler */ + UART1RX_Handler, /* 34 UART 1 RX Handler */ + UART1TX_Handler, /* 35 UART 1 TX Handler */ + UART2RX_Handler, /* 36 UART 2 RX Handler */ + UART2TX_Handler, /* 37 UART 2 TX Handler */ + UART3RX_Handler, /* 38 UART 2 RX Handler */ + UART3TX_Handler, /* 39 UART 2 TX Handler */ + UART4RX_Handler, /* 40 UART 2 RX Handler */ + UART4TX_Handler, /* 41 UART 2 TX Handler */ + UART0_Handler, /* 42 UART 0 combined Handler */ + UART1_Handler, /* 43 UART 1 combined Handler */ + UART2_Handler, /* 44 UART 2 combined Handler */ + UART3_Handler, /* 45 UART 3 combined Handler */ + UART4_Handler, /* 46 UART 4 combined Handler */ + UARTOVF_Handler, /* 47 UART 0,1,2,3,4 Overflow Handler */ + ETHERNET_Handler , /* 48 Ethernet Handler */ + I2S_Handler, /* 49 I2S Handler */ + TSC_Handler, /* 50 Touch Screen Handler */ + SPI0_Handler, /* 51 SPI 0 Handler */ + SPI1_Handler, /* 52 SPI 1 Handler */ + SPI2_Handler, /* 53 SPI 2 Handler */ + SPI3_Handler, /* 54 SPI 3 Handler */ + SPI4_Handler, /* 55 SPI 4 Handler */ + DMA0_ERROR_Handler, /* 56 DMA 0 Error Handler */ + DMA0_TC_Handler, /* 57 DMA 0 Terminal Count Handler */ + DMA0_Handler, /* 58 DMA 0 Combined Handler */ + DMA1_ERROR_Handler, /* 59 DMA 1 Error Handler */ + DMA1_TC_Handler, /* 60 DMA 1 Terminal Count Handler */ + DMA1_Handler, /* 61 DMA 1 Combined Handler */ + DMA2_ERROR_Handler, /* 62 DMA 2 Error Handler */ + DMA2_TC_Handler, /* 63 DMA 2 Terminal Count Handler */ + DMA2_Handler, /* 64 DMA 2 Combined Handler */ + DMA3_ERROR_Handler, /* 65 DMA 3 Error Handler */ + DMA3_TC_Handler, /* 66 DMA 3 Terminal Count Handler */ + DMA3_Handler, /* 67 DMA 3 Combined Handler */ + GPIO0_Handler, /* 68 GPIO 0 Combined Handler */ + GPIO1_Handler, /* 69 GPIO 1 Combined Handler */ + GPIO2_Handler, /* 70 GPIO 2 Combined Handler */ + GPIO3_Handler, /* 71 GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 72 */ /* All P0 I/O pins used as irq source */ + GPIO0_1_Handler, /* 73 */ /* There are 16 pins in total */ + GPIO0_2_Handler, /* 74 */ + GPIO0_3_Handler, /* 75 */ + GPIO0_4_Handler, /* 76 */ + GPIO0_5_Handler, /* 77 */ + GPIO0_6_Handler, /* 78 */ + GPIO0_7_Handler, /* 79 */ + GPIO0_8_Handler, /* 80 */ + GPIO0_9_Handler, /* 81 */ + GPIO0_10_Handler, /* 82 */ + GPIO0_11_Handler, /* 83 */ + GPIO0_12_Handler, /* 84 */ + GPIO0_13_Handler, /* 85 */ + GPIO0_14_Handler, /* 86 */ + GPIO0_15_Handler, /* 87 */ + GPIO1_0_Handler, /* 88 */ /* All P1 I/O pins used as irq source */ + GPIO1_1_Handler, /* 89 */ /* There are 16 pins in total */ + GPIO1_2_Handler, /* 90 */ + GPIO1_3_Handler, /* 91 */ + GPIO1_4_Handler, /* 92 */ + GPIO1_5_Handler, /* 93 */ + GPIO1_6_Handler, /* 94 */ + GPIO1_7_Handler, /* 95 */ + GPIO1_8_Handler, /* 96 */ + GPIO1_9_Handler, /* 97 */ + GPIO1_10_Handler, /* 98 */ + GPIO1_11_Handler, /* 99 */ + GPIO1_12_Handler, /* 100 */ + GPIO1_13_Handler, /* 101 */ + GPIO1_14_Handler, /* 102 */ + GPIO1_15_Handler, /* 103 */ + GPIO2_0_Handler, /* 104 */ /* All P2 I/O pins used as irq source */ + GPIO2_1_Handler, /* 105 */ /* There are 16 pins in total */ + GPIO2_2_Handler, /* 106 */ + GPIO2_3_Handler, /* 107 */ + GPIO2_4_Handler, /* 108 */ + GPIO2_5_Handler, /* 109 */ + GPIO2_6_Handler, /* 110 */ + GPIO2_7_Handler, /* 111 */ + GPIO2_8_Handler, /* 112 */ + GPIO2_9_Handler, /* 113 */ + GPIO2_10_Handler, /* 114 */ + GPIO2_11_Handler, /* 115 */ + GPIO2_12_Handler, /* 116 */ + GPIO2_13_Handler, /* 117 */ + GPIO2_14_Handler, /* 118 */ + GPIO2_15_Handler, /* 119 */ + GPIO3_0_Handler, /* 120 */ /* All P3 I/O pins used as irq source */ + GPIO3_1_Handler, /* 121 */ /* There are 4 pins in total */ + GPIO3_2_Handler, /* 122 */ + GPIO3_3_Handler, /* 123 */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined (IOTKit_CM33_VHT) || defined (IOTKit_CM33_FP_VHT) + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/IOTKit_CM33_FP_VHT/system_IOTKit_CM33.c b/RTE/Device/IOTKit_CM33_FP_VHT/system_IOTKit_CM33.c new file mode 100644 index 0000000..2c1d14c --- /dev/null +++ b/RTE/Device/IOTKit_CM33_FP_VHT/system_IOTKit_CM33.c @@ -0,0 +1,149 @@ +/****************************************************************************** + * @file system_IOTKit_CM33.c + * @brief CMSIS System Source File for IOTKit_CM33 Device + ******************************************************************************/ +/* Copyright (c) 2015 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (IOTKit_CM33) || defined (IOTKit_CM33_VHT) + #include "IOTKit_CM33.h" +#elif defined (IOTKit_CM33_FP) || defined (IOTKit_CM33_FP_VHT) + #include "IOTKit_CM33_FP.h" +#else + #error device not specified! +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_IOTKit_CM33.h" +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +// uint32_t blk_cfg, blk_max, blk_size, blk_cnt; +#endif + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* start IOT Green configuration ------------------------- */ + + /* Enable BusFault, UsageFault, MemManageFault and SecureFault to ease diagnostic */ + SCB->SHCSR |= (SCB_SHCSR_USGFAULTENA_Msk | + SCB_SHCSR_BUSFAULTENA_Msk | + SCB_SHCSR_MEMFAULTENA_Msk | + SCB_SHCSR_SECUREFAULTENA_Msk); + + /* BFSR register setting to enable precise errors */ + SCB->CFSR |= SCB_CFSR_PRECISERR_Msk; + + + /* configure MPC --------------- */ + + /* configure unsecure code area MPSSSRAM1 (0x00200000 - 0x003FFFFF) */ +// blk_max = IOTKIT_MPCSSRAM1->BLK_MAX; /* = 0x1 */ +// blk_cfg = IOTKIT_MPCSSRAM1->BLK_CFG; /* = 0xC */ +// blk_size = 1UL << (blk_cfg + 5U); /* = 0x20000 */ +// blk_cnt = 0x200000U / blk_size; /* = 0x10 */ + + IOTKIT_MPCSSRAM1->CTRL &= ~(1UL << 8U); /* clear auto increment */ + IOTKIT_MPCSSRAM1->BLK_IDX = 0; /* write LUT index */ + IOTKIT_MPCSSRAM1->BLK_LUT = 0xFFFF0000UL; /* configure blocks */ + + + /* configure unsecure data area MPSSSRAM3 (0x28200000 - 0x283FFFFF) */ +// blk_max = IOTKIT_MPCSSRAM3->BLK_MAX; /* = 0x1 */ +// blk_cfg = IOTKIT_MPCSSRAM3->BLK_CFG; /* = 0xB */ +// blk_size = 1UL << (blk_cfg + 5U); /* = 0x10000 */ +// blk_cnt = 0x200000U / blk_size; /* = 0x20 */ + + IOTKIT_MPCSSRAM3->CTRL &= ~(1UL << 8U); /* clear auto increment */ + IOTKIT_MPCSSRAM3->BLK_IDX = 1; /* write LUT index */ + IOTKIT_MPCSSRAM3->BLK_LUT = 0xFFFFFFFFUL; /* configure blocks */ + + + + /* enable the Non Secure Callable Configuration for IDAU (NSCCFG register) */ + IOTKIT_SPC->NSCCFG |= 1U; + + + /* configure PPC --------------- */ +#if !defined (__USE_SECURE) + /* Allow Non-secure access for SCC/FPGAIO registers */ + IOTKIT_SPC->APBNSPPCEXP[2U] |= ((1UL << 0U) | + (1UL << 2U) ); + /* Allow Non-secure access for SPI1/UART0 registers */ + IOTKIT_SPC->APBNSPPCEXP[1U] |= ((1UL << 1U) | + (1UL << 5U) ); +#endif + +/* end IOT Green configuration --------------------------- */ + + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/IOTKit_CM33_FP_VHT/system_IOTKit_CM33.c.base@1.2.0 b/RTE/Device/IOTKit_CM33_FP_VHT/system_IOTKit_CM33.c.base@1.2.0 new file mode 100644 index 0000000..2c1d14c --- /dev/null +++ b/RTE/Device/IOTKit_CM33_FP_VHT/system_IOTKit_CM33.c.base@1.2.0 @@ -0,0 +1,149 @@ +/****************************************************************************** + * @file system_IOTKit_CM33.c + * @brief CMSIS System Source File for IOTKit_CM33 Device + ******************************************************************************/ +/* Copyright (c) 2015 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (IOTKit_CM33) || defined (IOTKit_CM33_VHT) + #include "IOTKit_CM33.h" +#elif defined (IOTKit_CM33_FP) || defined (IOTKit_CM33_FP_VHT) + #include "IOTKit_CM33_FP.h" +#else + #error device not specified! +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_IOTKit_CM33.h" +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +// uint32_t blk_cfg, blk_max, blk_size, blk_cnt; +#endif + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* start IOT Green configuration ------------------------- */ + + /* Enable BusFault, UsageFault, MemManageFault and SecureFault to ease diagnostic */ + SCB->SHCSR |= (SCB_SHCSR_USGFAULTENA_Msk | + SCB_SHCSR_BUSFAULTENA_Msk | + SCB_SHCSR_MEMFAULTENA_Msk | + SCB_SHCSR_SECUREFAULTENA_Msk); + + /* BFSR register setting to enable precise errors */ + SCB->CFSR |= SCB_CFSR_PRECISERR_Msk; + + + /* configure MPC --------------- */ + + /* configure unsecure code area MPSSSRAM1 (0x00200000 - 0x003FFFFF) */ +// blk_max = IOTKIT_MPCSSRAM1->BLK_MAX; /* = 0x1 */ +// blk_cfg = IOTKIT_MPCSSRAM1->BLK_CFG; /* = 0xC */ +// blk_size = 1UL << (blk_cfg + 5U); /* = 0x20000 */ +// blk_cnt = 0x200000U / blk_size; /* = 0x10 */ + + IOTKIT_MPCSSRAM1->CTRL &= ~(1UL << 8U); /* clear auto increment */ + IOTKIT_MPCSSRAM1->BLK_IDX = 0; /* write LUT index */ + IOTKIT_MPCSSRAM1->BLK_LUT = 0xFFFF0000UL; /* configure blocks */ + + + /* configure unsecure data area MPSSSRAM3 (0x28200000 - 0x283FFFFF) */ +// blk_max = IOTKIT_MPCSSRAM3->BLK_MAX; /* = 0x1 */ +// blk_cfg = IOTKIT_MPCSSRAM3->BLK_CFG; /* = 0xB */ +// blk_size = 1UL << (blk_cfg + 5U); /* = 0x10000 */ +// blk_cnt = 0x200000U / blk_size; /* = 0x20 */ + + IOTKIT_MPCSSRAM3->CTRL &= ~(1UL << 8U); /* clear auto increment */ + IOTKIT_MPCSSRAM3->BLK_IDX = 1; /* write LUT index */ + IOTKIT_MPCSSRAM3->BLK_LUT = 0xFFFFFFFFUL; /* configure blocks */ + + + + /* enable the Non Secure Callable Configuration for IDAU (NSCCFG register) */ + IOTKIT_SPC->NSCCFG |= 1U; + + + /* configure PPC --------------- */ +#if !defined (__USE_SECURE) + /* Allow Non-secure access for SCC/FPGAIO registers */ + IOTKIT_SPC->APBNSPPCEXP[2U] |= ((1UL << 0U) | + (1UL << 2U) ); + /* Allow Non-secure access for SPI1/UART0 registers */ + IOTKIT_SPC->APBNSPPCEXP[1U] |= ((1UL << 1U) | + (1UL << 5U) ); +#endif + +/* end IOT Green configuration --------------------------- */ + + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/IOTKit_CM33_VHT/RTE_Device.h.base@1.0.0 b/RTE/Device/IOTKit_CM33_VHT/RTE_Device.h.base@1.0.0 new file mode 100644 index 0000000..786b74f --- /dev/null +++ b/RTE/Device/IOTKit_CM33_VHT/RTE_Device.h.base@1.0.0 @@ -0,0 +1,50 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 25. April 2016 + * $Revision: V1.0.0 + * + * Project: RTE Device Configuration for ARM CMSDK_CM device + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_USART0 0 + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_UART2 0 + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_UART3 0 + +#endif /* __RTE_DEVICE_H */ diff --git a/RTE/Device/IOTKit_CM33_VHT/ac6_arm.sct b/RTE/Device/IOTKit_CM33_VHT/ac6_arm.sct new file mode 100644 index 0000000..2682594 --- /dev/null +++ b/RTE/Device/IOTKit_CM33_VHT/ac6_arm.sct @@ -0,0 +1,119 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc +; command above MUST be in first line (no comment above!) + +;Note: Add '-mcmse' to first line if your software model is "Secure Mode". +; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse + + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x10000000 +#define __ROM_SIZE 0x00200000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x38000000 +#define __RAM_SIZE 0x00200000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00000C00 + +/*--------------------- CMSE Venner Configuration --------------------------- +; CMSE Venner Configuration +; CMSE Venner Size (in Bytes) <0x0-0xFFFFFFFF:32> +; + *----------------------------------------------------------------------------*/ +#define __CMSEVENEER_SIZE 0x200 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + + +/*---------------------------------------------------------------------------- + Region base & size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) +#define __CV_SIZE ( __CMSEVENEER_SIZE ) +#else +#define __CV_SIZE ( 0 ) +#endif + +#define __RO_BASE ( __ROM_BASE ) +#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) + +#define __RW_BASE ( __RAM_BASE ) +#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) + + +/*---------------------------------------------------------------------------- + Scatter Region definition + *----------------------------------------------------------------------------*/ +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Venners + ER_CMSE_VENEER __CV_BASE __CV_SIZE { + *(Veneer$$CMSE) + } +} +#endif diff --git a/RTE/Device/IOTKit_CM33_VHT/ac6_arm.sct.base@1.0.0 b/RTE/Device/IOTKit_CM33_VHT/ac6_arm.sct.base@1.0.0 new file mode 100644 index 0000000..2682594 --- /dev/null +++ b/RTE/Device/IOTKit_CM33_VHT/ac6_arm.sct.base@1.0.0 @@ -0,0 +1,119 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc +; command above MUST be in first line (no comment above!) + +;Note: Add '-mcmse' to first line if your software model is "Secure Mode". +; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse + + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x10000000 +#define __ROM_SIZE 0x00200000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x38000000 +#define __RAM_SIZE 0x00200000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00000C00 + +/*--------------------- CMSE Venner Configuration --------------------------- +; CMSE Venner Configuration +; CMSE Venner Size (in Bytes) <0x0-0xFFFFFFFF:32> +; + *----------------------------------------------------------------------------*/ +#define __CMSEVENEER_SIZE 0x200 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + + +/*---------------------------------------------------------------------------- + Region base & size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) +#define __CV_SIZE ( __CMSEVENEER_SIZE ) +#else +#define __CV_SIZE ( 0 ) +#endif + +#define __RO_BASE ( __ROM_BASE ) +#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) + +#define __RW_BASE ( __RAM_BASE ) +#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) + + +/*---------------------------------------------------------------------------- + Scatter Region definition + *----------------------------------------------------------------------------*/ +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Venners + ER_CMSE_VENEER __CV_BASE __CV_SIZE { + *(Veneer$$CMSE) + } +} +#endif diff --git a/RTE/Device/IOTKit_CM33_VHT/partition_IOTKit_CM33.h b/RTE/Device/IOTKit_CM33_VHT/partition_IOTKit_CM33.h new file mode 100644 index 0000000..45cb6ed --- /dev/null +++ b/RTE/Device/IOTKit_CM33_VHT/partition_IOTKit_CM33.h @@ -0,0 +1,637 @@ +/****************************************************************************** + * @file partition_IOTKit_CM33.h + * @brief CMSIS-Core Initial Setup for Secure / Non-Secure Zones for IOTKit_CM33 + ******************************************************************************/ +/* Copyright (c) 2015 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifndef PARTITION_IOTKit_CM33_H +#define PARTITION_IOTKit_CM33_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x10000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x101FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x003FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x28200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x283FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x403FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 0 + +/* +// Interrupts 0..31 +// Non-Secure Watchdog Reset Request <0=> Secure state <1=> Non-Secure state +// Non-Secure Watchdog interrupt <0=> Secure state <1=> Non-Secure state +// S32K Timer interrupt <0=> Secure state <1=> Non-Secure state +// Timer 0 interrupt <0=> Secure state <1=> Non-Secure state +// Timer 1 interrupt <0=> Secure state <1=> Non-Secure state +// Dual Timer interrupt <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 0 + +/* +// Interrupts 32..63 +// UART 0 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 0 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 1 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 1 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 2 teceive interrupt <0=> Secure state <1=> Non-Secure state +// UART 2 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 3 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 3 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 4 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 4 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 0 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 1 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 2 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 3 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 4 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 0, 1, 2, 3, 4 overflow interrupt <0=> Secure state <1=> Non-Secure state +// Ethernet interrupt <0=> Secure state <1=> Non-Secure state +// Audio I2S interrupt <0=> Secure state <1=> Non-Secure state +// Touch Screen interrupt <0=> Secure state <1=> Non-Secure state +// SPI 0 (SPI Header) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 1 (CLCD) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 2 (Shield ADC) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 3 (Shield 0 SPI) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 4 (Shield 1 SPI) interrupt <0=> Secure state <1=> Non-Secure state +// DMA 0 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 0 terminal count interrupt <0=> Secure state <1=> Non-Secure state +// DMA 0 combined interrupt <0=> Secure state <1=> Non-Secure state +// DMA 1 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 1 terminal count interrupt <0=> Secure state <1=> Non-Secure state +// DMA 1 combined interrupt <0=> Secure state <1=> Non-Secure state +// DMA 2 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 2 terminal count interrupt <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// DMA 2 combined interrupt <0=> Secure state <1=> Non-Secure state +// DMA 3 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 3 terminal count interrupt <0=> Secure state <1=> Non-Secure state +// DMA 3 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 0 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 1 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 2 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 3 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (10) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (11) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (12) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (13) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (14) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (15) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// GPIO 1 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (10) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (11) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (12) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (13) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (14) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (15) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (10) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (11) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (12) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (13) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (14) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (15) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif /* PARTITION_IOTKit_CM33_H */ diff --git a/RTE/Device/IOTKit_CM33_VHT/partition_IOTKit_CM33.h.base@1.0.0 b/RTE/Device/IOTKit_CM33_VHT/partition_IOTKit_CM33.h.base@1.0.0 new file mode 100644 index 0000000..45cb6ed --- /dev/null +++ b/RTE/Device/IOTKit_CM33_VHT/partition_IOTKit_CM33.h.base@1.0.0 @@ -0,0 +1,637 @@ +/****************************************************************************** + * @file partition_IOTKit_CM33.h + * @brief CMSIS-Core Initial Setup for Secure / Non-Secure Zones for IOTKit_CM33 + ******************************************************************************/ +/* Copyright (c) 2015 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifndef PARTITION_IOTKit_CM33_H +#define PARTITION_IOTKit_CM33_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x10000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x101FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x003FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x28200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x283FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x403FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 0 + +/* +// Interrupts 0..31 +// Non-Secure Watchdog Reset Request <0=> Secure state <1=> Non-Secure state +// Non-Secure Watchdog interrupt <0=> Secure state <1=> Non-Secure state +// S32K Timer interrupt <0=> Secure state <1=> Non-Secure state +// Timer 0 interrupt <0=> Secure state <1=> Non-Secure state +// Timer 1 interrupt <0=> Secure state <1=> Non-Secure state +// Dual Timer interrupt <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 0 + +/* +// Interrupts 32..63 +// UART 0 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 0 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 1 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 1 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 2 teceive interrupt <0=> Secure state <1=> Non-Secure state +// UART 2 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 3 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 3 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 4 receive interrupt <0=> Secure state <1=> Non-Secure state +// UART 4 transmit interrupt <0=> Secure state <1=> Non-Secure state +// UART 0 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 1 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 2 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 3 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 4 combined interrupt <0=> Secure state <1=> Non-Secure state +// UART 0, 1, 2, 3, 4 overflow interrupt <0=> Secure state <1=> Non-Secure state +// Ethernet interrupt <0=> Secure state <1=> Non-Secure state +// Audio I2S interrupt <0=> Secure state <1=> Non-Secure state +// Touch Screen interrupt <0=> Secure state <1=> Non-Secure state +// SPI 0 (SPI Header) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 1 (CLCD) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 2 (Shield ADC) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 3 (Shield 0 SPI) interrupt <0=> Secure state <1=> Non-Secure state +// SPI 4 (Shield 1 SPI) interrupt <0=> Secure state <1=> Non-Secure state +// DMA 0 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 0 terminal count interrupt <0=> Secure state <1=> Non-Secure state +// DMA 0 combined interrupt <0=> Secure state <1=> Non-Secure state +// DMA 1 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 1 terminal count interrupt <0=> Secure state <1=> Non-Secure state +// DMA 1 combined interrupt <0=> Secure state <1=> Non-Secure state +// DMA 2 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 2 terminal count interrupt <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// DMA 2 combined interrupt <0=> Secure state <1=> Non-Secure state +// DMA 3 error interrupt <0=> Secure state <1=> Non-Secure state +// DMA 3 terminal count interrupt <0=> Secure state <1=> Non-Secure state +// DMA 3 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 0 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 1 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 2 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 3 combined interrupt <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (10) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (11) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (12) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (13) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (14) <0=> Secure state <1=> Non-Secure state +// GPIO 0 individual interrupt (15) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// GPIO 1 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (10) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (11) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (12) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (13) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (14) <0=> Secure state <1=> Non-Secure state +// GPIO 1 individual interrupt (15) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (10) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (11) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (12) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (13) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (14) <0=> Secure state <1=> Non-Secure state +// GPIO 2 individual interrupt (15) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state +// GPIO 3 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif /* PARTITION_IOTKit_CM33_H */ diff --git a/RTE/Device/IOTKit_CM33_VHT/startup_IOTKit_CM33.c b/RTE/Device/IOTKit_CM33_VHT/startup_IOTKit_CM33.c new file mode 100644 index 0000000..bb3e1af --- /dev/null +++ b/RTE/Device/IOTKit_CM33_VHT/startup_IOTKit_CM33.c @@ -0,0 +1,513 @@ +/****************************************************************************** + * @file startup_IOTKit_CM33.c + * @brief CMSIS Startup File for IOTKit_CM33 Device + ******************************************************************************/ +/* Copyright (c) 2015 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (IOTKit_CM33) || defined (IOTKit_CM33_VHT) + #include "IOTKit_CM33.h" +#elif defined (IOTKit_CM33_FP) || defined (IOTKit_CM33_FP_VHT) + #include "IOTKit_CM33_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Core IoT Interrupts */ +void NONSEC_WATCHDOG_RESET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void NONSEC_WATCHDOG_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void S32K_TIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BRIDGE_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* External Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UARTOVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA0_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA0_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA1_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA1_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA3_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA3_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* VSI Interrupts */ +#if defined (IOTKit_CM33_VHT) || defined (IOTKit_CM33_FP_VHT) +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Core IoT Interrupts */ + NONSEC_WATCHDOG_RESET_Handler, /* 0 Non-Secure Watchdog Reset Handler */ + NONSEC_WATCHDOG_Handler, /* 1 Non-Secure Watchdog Handler */ + S32K_TIMER_Handler, /* 2 S32K Timer Handler */ + TIMER0_Handler, /* 3 TIMER 0 Handler */ + TIMER1_Handler, /* 4 TIMER 1 Handler */ + DUALTIMER_Handler, /* 5 Dual Timer Handler */ + 0, /* 6 Reserved */ + 0, /* 7 Reserved */ + 0, /* 8 Reserved */ + MPC_Handler, /* 9 MPC Combined (Secure) Handler */ + PPC_Handler, /* 10 PPC Combined (Secure) Handler */ + MSC_Handler, /* 11 MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12 Bridge Error Combined (Secure) Handler */ + 0, /* 13 Reserved */ + 0, /* 14 Reserved */ + 0, /* 15 Reserved */ + 0, /* 16 Reserved */ + 0, /* 17 Reserved */ + 0, /* 18 Reserved */ + 0, /* 19 Reserved */ + 0, /* 20 Reserved */ + 0, /* 21 Reserved */ + 0, /* 22 Reserved */ + 0, /* 23 Reserved */ + 0, /* 24 Reserved */ + 0, /* 25 Reserved */ + 0, /* 26 Reserved */ + 0, /* 27 Reserved */ + 0, /* 28 Reserved */ + 0, /* 29 Reserved */ + 0, /* 30 Reserved */ + 0, /* 31 Reserved */ + + /* External Interrupts */ + UART0RX_Handler, /* 32 UART 0 RX Handler */ + UART0TX_Handler, /* 33 UART 0 TX Handler */ + UART1RX_Handler, /* 34 UART 1 RX Handler */ + UART1TX_Handler, /* 35 UART 1 TX Handler */ + UART2RX_Handler, /* 36 UART 2 RX Handler */ + UART2TX_Handler, /* 37 UART 2 TX Handler */ + UART3RX_Handler, /* 38 UART 2 RX Handler */ + UART3TX_Handler, /* 39 UART 2 TX Handler */ + UART4RX_Handler, /* 40 UART 2 RX Handler */ + UART4TX_Handler, /* 41 UART 2 TX Handler */ + UART0_Handler, /* 42 UART 0 combined Handler */ + UART1_Handler, /* 43 UART 1 combined Handler */ + UART2_Handler, /* 44 UART 2 combined Handler */ + UART3_Handler, /* 45 UART 3 combined Handler */ + UART4_Handler, /* 46 UART 4 combined Handler */ + UARTOVF_Handler, /* 47 UART 0,1,2,3,4 Overflow Handler */ + ETHERNET_Handler , /* 48 Ethernet Handler */ + I2S_Handler, /* 49 I2S Handler */ + TSC_Handler, /* 50 Touch Screen Handler */ + SPI0_Handler, /* 51 SPI 0 Handler */ + SPI1_Handler, /* 52 SPI 1 Handler */ + SPI2_Handler, /* 53 SPI 2 Handler */ + SPI3_Handler, /* 54 SPI 3 Handler */ + SPI4_Handler, /* 55 SPI 4 Handler */ + DMA0_ERROR_Handler, /* 56 DMA 0 Error Handler */ + DMA0_TC_Handler, /* 57 DMA 0 Terminal Count Handler */ + DMA0_Handler, /* 58 DMA 0 Combined Handler */ + DMA1_ERROR_Handler, /* 59 DMA 1 Error Handler */ + DMA1_TC_Handler, /* 60 DMA 1 Terminal Count Handler */ + DMA1_Handler, /* 61 DMA 1 Combined Handler */ + DMA2_ERROR_Handler, /* 62 DMA 2 Error Handler */ + DMA2_TC_Handler, /* 63 DMA 2 Terminal Count Handler */ + DMA2_Handler, /* 64 DMA 2 Combined Handler */ + DMA3_ERROR_Handler, /* 65 DMA 3 Error Handler */ + DMA3_TC_Handler, /* 66 DMA 3 Terminal Count Handler */ + DMA3_Handler, /* 67 DMA 3 Combined Handler */ + GPIO0_Handler, /* 68 GPIO 0 Combined Handler */ + GPIO1_Handler, /* 69 GPIO 1 Combined Handler */ + GPIO2_Handler, /* 70 GPIO 2 Combined Handler */ + GPIO3_Handler, /* 71 GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 72 */ /* All P0 I/O pins used as irq source */ + GPIO0_1_Handler, /* 73 */ /* There are 16 pins in total */ + GPIO0_2_Handler, /* 74 */ + GPIO0_3_Handler, /* 75 */ + GPIO0_4_Handler, /* 76 */ + GPIO0_5_Handler, /* 77 */ + GPIO0_6_Handler, /* 78 */ + GPIO0_7_Handler, /* 79 */ + GPIO0_8_Handler, /* 80 */ + GPIO0_9_Handler, /* 81 */ + GPIO0_10_Handler, /* 82 */ + GPIO0_11_Handler, /* 83 */ + GPIO0_12_Handler, /* 84 */ + GPIO0_13_Handler, /* 85 */ + GPIO0_14_Handler, /* 86 */ + GPIO0_15_Handler, /* 87 */ + GPIO1_0_Handler, /* 88 */ /* All P1 I/O pins used as irq source */ + GPIO1_1_Handler, /* 89 */ /* There are 16 pins in total */ + GPIO1_2_Handler, /* 90 */ + GPIO1_3_Handler, /* 91 */ + GPIO1_4_Handler, /* 92 */ + GPIO1_5_Handler, /* 93 */ + GPIO1_6_Handler, /* 94 */ + GPIO1_7_Handler, /* 95 */ + GPIO1_8_Handler, /* 96 */ + GPIO1_9_Handler, /* 97 */ + GPIO1_10_Handler, /* 98 */ + GPIO1_11_Handler, /* 99 */ + GPIO1_12_Handler, /* 100 */ + GPIO1_13_Handler, /* 101 */ + GPIO1_14_Handler, /* 102 */ + GPIO1_15_Handler, /* 103 */ + GPIO2_0_Handler, /* 104 */ /* All P2 I/O pins used as irq source */ + GPIO2_1_Handler, /* 105 */ /* There are 16 pins in total */ + GPIO2_2_Handler, /* 106 */ + GPIO2_3_Handler, /* 107 */ + GPIO2_4_Handler, /* 108 */ + GPIO2_5_Handler, /* 109 */ + GPIO2_6_Handler, /* 110 */ + GPIO2_7_Handler, /* 111 */ + GPIO2_8_Handler, /* 112 */ + GPIO2_9_Handler, /* 113 */ + GPIO2_10_Handler, /* 114 */ + GPIO2_11_Handler, /* 115 */ + GPIO2_12_Handler, /* 116 */ + GPIO2_13_Handler, /* 117 */ + GPIO2_14_Handler, /* 118 */ + GPIO2_15_Handler, /* 119 */ + GPIO3_0_Handler, /* 120 */ /* All P3 I/O pins used as irq source */ + GPIO3_1_Handler, /* 121 */ /* There are 4 pins in total */ + GPIO3_2_Handler, /* 122 */ + GPIO3_3_Handler, /* 123 */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined (IOTKit_CM33_VHT) || defined (IOTKit_CM33_FP_VHT) + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/IOTKit_CM33_VHT/startup_IOTKit_CM33.c.base@1.2.0 b/RTE/Device/IOTKit_CM33_VHT/startup_IOTKit_CM33.c.base@1.2.0 new file mode 100644 index 0000000..bb3e1af --- /dev/null +++ b/RTE/Device/IOTKit_CM33_VHT/startup_IOTKit_CM33.c.base@1.2.0 @@ -0,0 +1,513 @@ +/****************************************************************************** + * @file startup_IOTKit_CM33.c + * @brief CMSIS Startup File for IOTKit_CM33 Device + ******************************************************************************/ +/* Copyright (c) 2015 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (IOTKit_CM33) || defined (IOTKit_CM33_VHT) + #include "IOTKit_CM33.h" +#elif defined (IOTKit_CM33_FP) || defined (IOTKit_CM33_FP_VHT) + #include "IOTKit_CM33_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Core IoT Interrupts */ +void NONSEC_WATCHDOG_RESET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void NONSEC_WATCHDOG_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void S32K_TIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BRIDGE_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* External Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UARTOVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA0_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA0_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA1_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA1_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA3_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA3_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DMA3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* VSI Interrupts */ +#if defined (IOTKit_CM33_VHT) || defined (IOTKit_CM33_FP_VHT) +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Core IoT Interrupts */ + NONSEC_WATCHDOG_RESET_Handler, /* 0 Non-Secure Watchdog Reset Handler */ + NONSEC_WATCHDOG_Handler, /* 1 Non-Secure Watchdog Handler */ + S32K_TIMER_Handler, /* 2 S32K Timer Handler */ + TIMER0_Handler, /* 3 TIMER 0 Handler */ + TIMER1_Handler, /* 4 TIMER 1 Handler */ + DUALTIMER_Handler, /* 5 Dual Timer Handler */ + 0, /* 6 Reserved */ + 0, /* 7 Reserved */ + 0, /* 8 Reserved */ + MPC_Handler, /* 9 MPC Combined (Secure) Handler */ + PPC_Handler, /* 10 PPC Combined (Secure) Handler */ + MSC_Handler, /* 11 MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12 Bridge Error Combined (Secure) Handler */ + 0, /* 13 Reserved */ + 0, /* 14 Reserved */ + 0, /* 15 Reserved */ + 0, /* 16 Reserved */ + 0, /* 17 Reserved */ + 0, /* 18 Reserved */ + 0, /* 19 Reserved */ + 0, /* 20 Reserved */ + 0, /* 21 Reserved */ + 0, /* 22 Reserved */ + 0, /* 23 Reserved */ + 0, /* 24 Reserved */ + 0, /* 25 Reserved */ + 0, /* 26 Reserved */ + 0, /* 27 Reserved */ + 0, /* 28 Reserved */ + 0, /* 29 Reserved */ + 0, /* 30 Reserved */ + 0, /* 31 Reserved */ + + /* External Interrupts */ + UART0RX_Handler, /* 32 UART 0 RX Handler */ + UART0TX_Handler, /* 33 UART 0 TX Handler */ + UART1RX_Handler, /* 34 UART 1 RX Handler */ + UART1TX_Handler, /* 35 UART 1 TX Handler */ + UART2RX_Handler, /* 36 UART 2 RX Handler */ + UART2TX_Handler, /* 37 UART 2 TX Handler */ + UART3RX_Handler, /* 38 UART 2 RX Handler */ + UART3TX_Handler, /* 39 UART 2 TX Handler */ + UART4RX_Handler, /* 40 UART 2 RX Handler */ + UART4TX_Handler, /* 41 UART 2 TX Handler */ + UART0_Handler, /* 42 UART 0 combined Handler */ + UART1_Handler, /* 43 UART 1 combined Handler */ + UART2_Handler, /* 44 UART 2 combined Handler */ + UART3_Handler, /* 45 UART 3 combined Handler */ + UART4_Handler, /* 46 UART 4 combined Handler */ + UARTOVF_Handler, /* 47 UART 0,1,2,3,4 Overflow Handler */ + ETHERNET_Handler , /* 48 Ethernet Handler */ + I2S_Handler, /* 49 I2S Handler */ + TSC_Handler, /* 50 Touch Screen Handler */ + SPI0_Handler, /* 51 SPI 0 Handler */ + SPI1_Handler, /* 52 SPI 1 Handler */ + SPI2_Handler, /* 53 SPI 2 Handler */ + SPI3_Handler, /* 54 SPI 3 Handler */ + SPI4_Handler, /* 55 SPI 4 Handler */ + DMA0_ERROR_Handler, /* 56 DMA 0 Error Handler */ + DMA0_TC_Handler, /* 57 DMA 0 Terminal Count Handler */ + DMA0_Handler, /* 58 DMA 0 Combined Handler */ + DMA1_ERROR_Handler, /* 59 DMA 1 Error Handler */ + DMA1_TC_Handler, /* 60 DMA 1 Terminal Count Handler */ + DMA1_Handler, /* 61 DMA 1 Combined Handler */ + DMA2_ERROR_Handler, /* 62 DMA 2 Error Handler */ + DMA2_TC_Handler, /* 63 DMA 2 Terminal Count Handler */ + DMA2_Handler, /* 64 DMA 2 Combined Handler */ + DMA3_ERROR_Handler, /* 65 DMA 3 Error Handler */ + DMA3_TC_Handler, /* 66 DMA 3 Terminal Count Handler */ + DMA3_Handler, /* 67 DMA 3 Combined Handler */ + GPIO0_Handler, /* 68 GPIO 0 Combined Handler */ + GPIO1_Handler, /* 69 GPIO 1 Combined Handler */ + GPIO2_Handler, /* 70 GPIO 2 Combined Handler */ + GPIO3_Handler, /* 71 GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 72 */ /* All P0 I/O pins used as irq source */ + GPIO0_1_Handler, /* 73 */ /* There are 16 pins in total */ + GPIO0_2_Handler, /* 74 */ + GPIO0_3_Handler, /* 75 */ + GPIO0_4_Handler, /* 76 */ + GPIO0_5_Handler, /* 77 */ + GPIO0_6_Handler, /* 78 */ + GPIO0_7_Handler, /* 79 */ + GPIO0_8_Handler, /* 80 */ + GPIO0_9_Handler, /* 81 */ + GPIO0_10_Handler, /* 82 */ + GPIO0_11_Handler, /* 83 */ + GPIO0_12_Handler, /* 84 */ + GPIO0_13_Handler, /* 85 */ + GPIO0_14_Handler, /* 86 */ + GPIO0_15_Handler, /* 87 */ + GPIO1_0_Handler, /* 88 */ /* All P1 I/O pins used as irq source */ + GPIO1_1_Handler, /* 89 */ /* There are 16 pins in total */ + GPIO1_2_Handler, /* 90 */ + GPIO1_3_Handler, /* 91 */ + GPIO1_4_Handler, /* 92 */ + GPIO1_5_Handler, /* 93 */ + GPIO1_6_Handler, /* 94 */ + GPIO1_7_Handler, /* 95 */ + GPIO1_8_Handler, /* 96 */ + GPIO1_9_Handler, /* 97 */ + GPIO1_10_Handler, /* 98 */ + GPIO1_11_Handler, /* 99 */ + GPIO1_12_Handler, /* 100 */ + GPIO1_13_Handler, /* 101 */ + GPIO1_14_Handler, /* 102 */ + GPIO1_15_Handler, /* 103 */ + GPIO2_0_Handler, /* 104 */ /* All P2 I/O pins used as irq source */ + GPIO2_1_Handler, /* 105 */ /* There are 16 pins in total */ + GPIO2_2_Handler, /* 106 */ + GPIO2_3_Handler, /* 107 */ + GPIO2_4_Handler, /* 108 */ + GPIO2_5_Handler, /* 109 */ + GPIO2_6_Handler, /* 110 */ + GPIO2_7_Handler, /* 111 */ + GPIO2_8_Handler, /* 112 */ + GPIO2_9_Handler, /* 113 */ + GPIO2_10_Handler, /* 114 */ + GPIO2_11_Handler, /* 115 */ + GPIO2_12_Handler, /* 116 */ + GPIO2_13_Handler, /* 117 */ + GPIO2_14_Handler, /* 118 */ + GPIO2_15_Handler, /* 119 */ + GPIO3_0_Handler, /* 120 */ /* All P3 I/O pins used as irq source */ + GPIO3_1_Handler, /* 121 */ /* There are 4 pins in total */ + GPIO3_2_Handler, /* 122 */ + GPIO3_3_Handler, /* 123 */ + 0, /* 124 Reserved */ + 0, /* 125 Reserved */ + 0, /* 126 Reserved */ + 0, /* 127 Reserved */ + 0, /* 128 Reserved */ + 0, /* 129 Reserved */ + 0, /* 130 Reserved */ + 0, /* 131 Reserved */ + 0, /* 132 Reserved */ + 0, /* 133 Reserved */ + 0, /* 134 Reserved */ + 0, /* 135 Reserved */ + 0, /* 136 Reserved */ + 0, /* 137 Reserved */ + 0, /* 138 Reserved */ + 0, /* 139 Reserved */ + 0, /* 140 Reserved */ + 0, /* 141 Reserved */ + 0, /* 142 Reserved */ + 0, /* 143 Reserved */ + 0, /* 144 Reserved */ + 0, /* 145 Reserved */ + 0, /* 146 Reserved */ + 0, /* 147 Reserved */ + 0, /* 148 Reserved */ + 0, /* 149 Reserved */ + 0, /* 150 Reserved */ + 0, /* 151 Reserved */ + 0, /* 152 Reserved */ + 0, /* 153 Reserved */ + 0, /* 154 Reserved */ + 0, /* 155 Reserved */ + 0, /* 156 Reserved */ + 0, /* 157 Reserved */ + 0, /* 158 Reserved */ + 0, /* 159 Reserved */ + 0, /* 160 Reserved */ + 0, /* 161 Reserved */ + 0, /* 162 Reserved */ + 0, /* 163 Reserved */ + 0, /* 164 Reserved */ + 0, /* 165 Reserved */ + 0, /* 166 Reserved */ + 0, /* 167 Reserved */ + 0, /* 168 Reserved */ + 0, /* 169 Reserved */ + 0, /* 170 Reserved */ + 0, /* 171 Reserved */ + 0, /* 172 Reserved */ + 0, /* 173 Reserved */ + 0, /* 174 Reserved */ + 0, /* 175 Reserved */ + 0, /* 176 Reserved */ + 0, /* 177 Reserved */ + 0, /* 178 Reserved */ + 0, /* 179 Reserved */ + 0, /* 180 Reserved */ + 0, /* 181 Reserved */ + 0, /* 182 Reserved */ + 0, /* 183 Reserved */ + 0, /* 184 Reserved */ + 0, /* 185 Reserved */ + 0, /* 186 Reserved */ + 0, /* 187 Reserved */ + 0, /* 188 Reserved */ + 0, /* 189 Reserved */ + 0, /* 190 Reserved */ + 0, /* 191 Reserved */ + 0, /* 192 Reserved */ + 0, /* 193 Reserved */ + 0, /* 194 Reserved */ + 0, /* 195 Reserved */ + 0, /* 196 Reserved */ + 0, /* 197 Reserved */ + 0, /* 198 Reserved */ + 0, /* 199 Reserved */ + 0, /* 200 Reserved */ + 0, /* 201 Reserved */ + 0, /* 202 Reserved */ + 0, /* 203 Reserved */ + 0, /* 204 Reserved */ + 0, /* 205 Reserved */ + 0, /* 206 Reserved */ + 0, /* 207 Reserved */ + 0, /* 208 Reserved */ + 0, /* 209 Reserved */ + 0, /* 210 Reserved */ + 0, /* 211 Reserved */ + 0, /* 212 Reserved */ + 0, /* 213 Reserved */ + 0, /* 214 Reserved */ + 0, /* 215 Reserved */ + 0, /* 216 Reserved */ + 0, /* 217 Reserved */ + 0, /* 218 Reserved */ + 0, /* 219 Reserved */ + 0, /* 220 Reserved */ + 0, /* 221 Reserved */ + 0, /* 222 Reserved */ + 0, /* 223 Reserved */ +#if defined (IOTKit_CM33_VHT) || defined (IOTKit_CM33_FP_VHT) + ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ + ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ + ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ + ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ + ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ + ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ + ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ + ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +#else + 0, /* 224 Reserved */ + 0, /* 225 Reserved */ + 0, /* 226 Reserved */ + 0, /* 227 Reserved */ + 0, /* 228 Reserved */ + 0, /* 229 Reserved */ + 0, /* 230 Reserved */ + 0 /* 231 Reserved */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/RTE/Device/IOTKit_CM33_VHT/system_IOTKit_CM33.c b/RTE/Device/IOTKit_CM33_VHT/system_IOTKit_CM33.c new file mode 100644 index 0000000..2c1d14c --- /dev/null +++ b/RTE/Device/IOTKit_CM33_VHT/system_IOTKit_CM33.c @@ -0,0 +1,149 @@ +/****************************************************************************** + * @file system_IOTKit_CM33.c + * @brief CMSIS System Source File for IOTKit_CM33 Device + ******************************************************************************/ +/* Copyright (c) 2015 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (IOTKit_CM33) || defined (IOTKit_CM33_VHT) + #include "IOTKit_CM33.h" +#elif defined (IOTKit_CM33_FP) || defined (IOTKit_CM33_FP_VHT) + #include "IOTKit_CM33_FP.h" +#else + #error device not specified! +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_IOTKit_CM33.h" +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +// uint32_t blk_cfg, blk_max, blk_size, blk_cnt; +#endif + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* start IOT Green configuration ------------------------- */ + + /* Enable BusFault, UsageFault, MemManageFault and SecureFault to ease diagnostic */ + SCB->SHCSR |= (SCB_SHCSR_USGFAULTENA_Msk | + SCB_SHCSR_BUSFAULTENA_Msk | + SCB_SHCSR_MEMFAULTENA_Msk | + SCB_SHCSR_SECUREFAULTENA_Msk); + + /* BFSR register setting to enable precise errors */ + SCB->CFSR |= SCB_CFSR_PRECISERR_Msk; + + + /* configure MPC --------------- */ + + /* configure unsecure code area MPSSSRAM1 (0x00200000 - 0x003FFFFF) */ +// blk_max = IOTKIT_MPCSSRAM1->BLK_MAX; /* = 0x1 */ +// blk_cfg = IOTKIT_MPCSSRAM1->BLK_CFG; /* = 0xC */ +// blk_size = 1UL << (blk_cfg + 5U); /* = 0x20000 */ +// blk_cnt = 0x200000U / blk_size; /* = 0x10 */ + + IOTKIT_MPCSSRAM1->CTRL &= ~(1UL << 8U); /* clear auto increment */ + IOTKIT_MPCSSRAM1->BLK_IDX = 0; /* write LUT index */ + IOTKIT_MPCSSRAM1->BLK_LUT = 0xFFFF0000UL; /* configure blocks */ + + + /* configure unsecure data area MPSSSRAM3 (0x28200000 - 0x283FFFFF) */ +// blk_max = IOTKIT_MPCSSRAM3->BLK_MAX; /* = 0x1 */ +// blk_cfg = IOTKIT_MPCSSRAM3->BLK_CFG; /* = 0xB */ +// blk_size = 1UL << (blk_cfg + 5U); /* = 0x10000 */ +// blk_cnt = 0x200000U / blk_size; /* = 0x20 */ + + IOTKIT_MPCSSRAM3->CTRL &= ~(1UL << 8U); /* clear auto increment */ + IOTKIT_MPCSSRAM3->BLK_IDX = 1; /* write LUT index */ + IOTKIT_MPCSSRAM3->BLK_LUT = 0xFFFFFFFFUL; /* configure blocks */ + + + + /* enable the Non Secure Callable Configuration for IDAU (NSCCFG register) */ + IOTKIT_SPC->NSCCFG |= 1U; + + + /* configure PPC --------------- */ +#if !defined (__USE_SECURE) + /* Allow Non-secure access for SCC/FPGAIO registers */ + IOTKIT_SPC->APBNSPPCEXP[2U] |= ((1UL << 0U) | + (1UL << 2U) ); + /* Allow Non-secure access for SPI1/UART0 registers */ + IOTKIT_SPC->APBNSPPCEXP[1U] |= ((1UL << 1U) | + (1UL << 5U) ); +#endif + +/* end IOT Green configuration --------------------------- */ + + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/IOTKit_CM33_VHT/system_IOTKit_CM33.c.base@1.2.0 b/RTE/Device/IOTKit_CM33_VHT/system_IOTKit_CM33.c.base@1.2.0 new file mode 100644 index 0000000..2c1d14c --- /dev/null +++ b/RTE/Device/IOTKit_CM33_VHT/system_IOTKit_CM33.c.base@1.2.0 @@ -0,0 +1,149 @@ +/****************************************************************************** + * @file system_IOTKit_CM33.c + * @brief CMSIS System Source File for IOTKit_CM33 Device + ******************************************************************************/ +/* Copyright (c) 2015 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined (IOTKit_CM33) || defined (IOTKit_CM33_VHT) + #include "IOTKit_CM33.h" +#elif defined (IOTKit_CM33_FP) || defined (IOTKit_CM33_FP_VHT) + #include "IOTKit_CM33_FP.h" +#else + #error device not specified! +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_IOTKit_CM33.h" +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +// uint32_t blk_cfg, blk_max, blk_size, blk_cnt; +#endif + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* start IOT Green configuration ------------------------- */ + + /* Enable BusFault, UsageFault, MemManageFault and SecureFault to ease diagnostic */ + SCB->SHCSR |= (SCB_SHCSR_USGFAULTENA_Msk | + SCB_SHCSR_BUSFAULTENA_Msk | + SCB_SHCSR_MEMFAULTENA_Msk | + SCB_SHCSR_SECUREFAULTENA_Msk); + + /* BFSR register setting to enable precise errors */ + SCB->CFSR |= SCB_CFSR_PRECISERR_Msk; + + + /* configure MPC --------------- */ + + /* configure unsecure code area MPSSSRAM1 (0x00200000 - 0x003FFFFF) */ +// blk_max = IOTKIT_MPCSSRAM1->BLK_MAX; /* = 0x1 */ +// blk_cfg = IOTKIT_MPCSSRAM1->BLK_CFG; /* = 0xC */ +// blk_size = 1UL << (blk_cfg + 5U); /* = 0x20000 */ +// blk_cnt = 0x200000U / blk_size; /* = 0x10 */ + + IOTKIT_MPCSSRAM1->CTRL &= ~(1UL << 8U); /* clear auto increment */ + IOTKIT_MPCSSRAM1->BLK_IDX = 0; /* write LUT index */ + IOTKIT_MPCSSRAM1->BLK_LUT = 0xFFFF0000UL; /* configure blocks */ + + + /* configure unsecure data area MPSSSRAM3 (0x28200000 - 0x283FFFFF) */ +// blk_max = IOTKIT_MPCSSRAM3->BLK_MAX; /* = 0x1 */ +// blk_cfg = IOTKIT_MPCSSRAM3->BLK_CFG; /* = 0xB */ +// blk_size = 1UL << (blk_cfg + 5U); /* = 0x10000 */ +// blk_cnt = 0x200000U / blk_size; /* = 0x20 */ + + IOTKIT_MPCSSRAM3->CTRL &= ~(1UL << 8U); /* clear auto increment */ + IOTKIT_MPCSSRAM3->BLK_IDX = 1; /* write LUT index */ + IOTKIT_MPCSSRAM3->BLK_LUT = 0xFFFFFFFFUL; /* configure blocks */ + + + + /* enable the Non Secure Callable Configuration for IDAU (NSCCFG register) */ + IOTKIT_SPC->NSCCFG |= 1U; + + + /* configure PPC --------------- */ +#if !defined (__USE_SECURE) + /* Allow Non-secure access for SCC/FPGAIO registers */ + IOTKIT_SPC->APBNSPPCEXP[2U] |= ((1UL << 0U) | + (1UL << 2U) ); + /* Allow Non-secure access for SPI1/UART0 registers */ + IOTKIT_SPC->APBNSPPCEXP[1U] |= ((1UL << 1U) | + (1UL << 5U) ); +#endif + +/* end IOT Green configuration --------------------------- */ + + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src b/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src new file mode 100644 index 0000000..7820e1f --- /dev/null +++ b/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE 8 +#else +#define __STACKSEAL_SIZE 0 +#endif + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +LR_ROM0 __ROM0_BASE __ROM0_SIZE { + + ER_ROM0 __ROM0_BASE __ROM0_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + *(+RO +XO) + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) { + *(Veneer$$CMSE) + } +#endif + + RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { + *.o(.bss.noinit) + *.o(.bss.noinit.*) + } + + RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if __STACKSEAL_SIZE > 0 + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif + +#if __RAM1_SIZE > 0 + RW_RAM1 __RAM1_BASE __RAM1_SIZE { + .ANY (+RW +ZI) + } +#endif + +#if __RAM2_SIZE > 0 + RW_RAM2 __RAM2_BASE __RAM2_SIZE { + .ANY (+RW +ZI) + } +#endif + +#if __RAM3_SIZE > 0 + RW_RAM3 __RAM3_BASE __RAM3_SIZE { + .ANY (+RW +ZI) + } +#endif +} + +#if __ROM1_SIZE > 0 +LR_ROM1 __ROM1_BASE __ROM1_SIZE { + ER_ROM1 +0 __ROM1_SIZE { + .ANY (+RO +XO) + } +} +#endif + +#if __ROM2_SIZE > 0 +LR_ROM2 __ROM2_BASE __ROM2_SIZE { + ER_ROM2 +0 __ROM2_SIZE { + .ANY (+RO +XO) + } +} +#endif + +#if __ROM3_SIZE > 0 +LR_ROM3 __ROM3_BASE __ROM3_SIZE { + ER_ROM3 +0 __ROM3_SIZE { + .ANY (+RO +XO) + } +} +#endif diff --git a/RTE/Device/SSE-300-MPS3/device_cfg.h b/RTE/Device/SSE-300-MPS3/device_cfg.h new file mode 100644 index 0000000..0e9746a --- /dev/null +++ b/RTE/Device/SSE-300-MPS3/device_cfg.h @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2020-2024 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S + +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + +/* ARM UART Controller PL011 */ +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S + +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S + +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S + +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +/** System Counter Armv8-M */ +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u + +/* System timer */ +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) + +/* CMSDK GPIO driver structures */ +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S + +/* System Watchdogs */ +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S + +/* ARM MPC SIE 300 driver structures */ +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S + +/* ARM PPC driver structures */ +#define PPC_SSE300_MAIN0_S +#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S +#define PPC_SSE300_MAIN_EXP0_S +#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S +#define PPC_SSE300_MAIN_EXP1_S +#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S +#define PPC_SSE300_MAIN_EXP2_S +#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S +#define PPC_SSE300_MAIN_EXP3_S +#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S +#define PPC_SSE300_PERIPH0_S +#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S +#define PPC_SSE300_PERIPH1_S +#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S +#define PPC_SSE300_PERIPH_EXP0_S +#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S +#define PPC_SSE300_PERIPH_EXP1_S +#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S +#define PPC_SSE300_PERIPH_EXP2_S +#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S +#define PPC_SSE300_PERIPH_EXP3_S +#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S + +#endif /* __DEVICE_CFG_H__ */ diff --git a/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.4 b/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.4 new file mode 100644 index 0000000..0e9746a --- /dev/null +++ b/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.4 @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2020-2024 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S + +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + +/* ARM UART Controller PL011 */ +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S + +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S + +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S + +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +/** System Counter Armv8-M */ +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u + +/* System timer */ +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) + +/* CMSDK GPIO driver structures */ +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S + +/* System Watchdogs */ +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S + +/* ARM MPC SIE 300 driver structures */ +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S + +/* ARM PPC driver structures */ +#define PPC_SSE300_MAIN0_S +#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S +#define PPC_SSE300_MAIN_EXP0_S +#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S +#define PPC_SSE300_MAIN_EXP1_S +#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S +#define PPC_SSE300_MAIN_EXP2_S +#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S +#define PPC_SSE300_MAIN_EXP3_S +#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S +#define PPC_SSE300_PERIPH0_S +#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S +#define PPC_SSE300_PERIPH1_S +#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S +#define PPC_SSE300_PERIPH_EXP0_S +#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S +#define PPC_SSE300_PERIPH_EXP1_S +#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S +#define PPC_SSE300_PERIPH_EXP2_S +#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S +#define PPC_SSE300_PERIPH_EXP3_S +#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S + +#endif /* __DEVICE_CFG_H__ */ diff --git a/RTE/Device/SSE-300-MPS3/regions_SSE-300-MPS3.h b/RTE/Device/SSE-300-MPS3/regions_SSE-300-MPS3.h new file mode 100644 index 0000000..cd583f5 --- /dev/null +++ b/RTE/Device/SSE-300-MPS3/regions_SSE-300-MPS3.h @@ -0,0 +1,366 @@ +#ifndef REGIONS_SSE_300_MPS3_H +#define REGIONS_SSE_300_MPS3_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Device pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 +// Device pack used to generate this file + +// ROM Configuration +// ======================= +// IROM1=<__ROM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x10000000 +#define __ROM0_BASE 0x10000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __ROM0_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __ROM0_DEFAULT 1 +// Startup +// Selects region to be used for startup code. +#define __ROM0_STARTUP 1 +// + +// + +// RAM Configuration +// ======================= +// IRAM1=<__RAM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x30000000 +#define __RAM0_BASE 0x30000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM0_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM0_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM0_NOINIT 0 +// + +// ITCM_NS=<__RAM1> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00000000 +#define __RAM1_BASE 0x00000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00080000 +#define __RAM1_SIZE 0x00080000 +// Default region +// Enables memory region globally for the application. +#define __RAM1_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM1_NOINIT 0 +// + +// SRAM_NS=<__RAM2> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x01000000 +#define __RAM2_BASE 0x01000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00100000 +#define __RAM2_SIZE 0x00100000 +// Default region +// Enables memory region globally for the application. +#define __RAM2_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM2_NOINIT 0 +// + +// DTCM0_NS=<__RAM3> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20000000 +#define __RAM3_BASE 0x20000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM3_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM3_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM3_NOINIT 0 +// + +// DTCM1_NS=<__RAM4> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20020000 +#define __RAM4_BASE 0x20020000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM4_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM4_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM4_NOINIT 0 +// + +// DTCM2_NS=<__RAM5> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20040000 +#define __RAM5_BASE 0x20040000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM5_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM5_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM5_NOINIT 0 +// + +// DTCM3_NS=<__RAM6> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20060000 +#define __RAM6_BASE 0x20060000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM6_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM6_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM6_NOINIT 0 +// + +// ISRAM0_NS=<__RAM7> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x21000000 +#define __RAM7_BASE 0x21000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00100000 +#define __RAM7_SIZE 0x00100000 +// Default region +// Enables memory region globally for the application. +#define __RAM7_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM7_NOINIT 0 +// + +// ISRAM1_NS=<__RAM8> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x21100000 +#define __RAM8_BASE 0x21100000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00100000 +#define __RAM8_SIZE 0x00100000 +// Default region +// Enables memory region globally for the application. +#define __RAM8_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM8_NOINIT 0 +// + +// QSPI_SRAM_NS=<__RAM9> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x28000000 +#define __RAM9_BASE 0x28000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00800000 +#define __RAM9_SIZE 0x00800000 +// Default region +// Enables memory region globally for the application. +#define __RAM9_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM9_NOINIT 0 +// + +// ITCM_S=<__RAM10> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x10000000 +#define __RAM10_BASE 0x10000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00080000 +#define __RAM10_SIZE 0x00080000 +// Default region +// Enables memory region globally for the application. +#define __RAM10_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM10_NOINIT 0 +// + +// SRAM_S=<__RAM11> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x11000000 +#define __RAM11_BASE 0x11000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00100000 +#define __RAM11_SIZE 0x00100000 +// Default region +// Enables memory region globally for the application. +#define __RAM11_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM11_NOINIT 0 +// + +// DTCM0_S=<__RAM12> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x30000000 +#define __RAM12_BASE 0x30000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM12_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM12_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM12_NOINIT 0 +// + +// DTCM1_S=<__RAM13> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x30020000 +#define __RAM13_BASE 0x30020000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM13_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM13_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM13_NOINIT 0 +// + +// DTCM2_S=<__RAM14> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x30040000 +#define __RAM14_BASE 0x30040000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM14_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM14_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM14_NOINIT 0 +// + +// DTCM3_S=<__RAM15> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x30060000 +#define __RAM15_BASE 0x30060000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM15_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM15_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM15_NOINIT 0 +// + +// ISRAM0_S=<__RAM16> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x31000000 +#define __RAM16_BASE 0x31000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00100000 +#define __RAM16_SIZE 0x00100000 +// Default region +// Enables memory region globally for the application. +#define __RAM16_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM16_NOINIT 0 +// + +// ISRAM1_S=<__RAM17> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x31100000 +#define __RAM17_BASE 0x31100000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00100000 +#define __RAM17_SIZE 0x00100000 +// Default region +// Enables memory region globally for the application. +#define __RAM17_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM17_NOINIT 0 +// + +// QSPI_SRAM_S=<__RAM18> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x38000000 +#define __RAM18_BASE 0x38000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00800000 +#define __RAM18_SIZE 0x00800000 +// Default region +// Enables memory region globally for the application. +#define __RAM18_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM18_NOINIT 0 +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 +// + + +#endif /* REGIONS_SSE_300_MPS3_H */ diff --git a/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c b/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c new file mode 100644 index 0000000..b29bff1 --- /dev/null +++ b/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c @@ -0,0 +1,487 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __NO_RETURN __WEAK handler_name(void); \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +#ifdef CORSTONE300_AN547 +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Handler) +#ifdef CORSTONE300_FVP +DEFAULT_IRQ_HANDLER(ARM_VSI0_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI1_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI2_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI3_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI4_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI5_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI6_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI7_Handler) +#endif +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ +#ifdef CORSTONE300_AN547 + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#else + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Handler, /* 127: UART 5 combined Interrupt */ + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ +#ifdef CORSTONE300_FVP + 0, /* 131: Reserved */ + 0, /* 132: Reserved */ + 0, /* 133: Reserved */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + ARM_VSI0_Handler, /* 224: VSI 0 Handler */ + ARM_VSI1_Handler, /* 225: VSI 1 Handler */ + ARM_VSI2_Handler, /* 226: VSI 2 Handler */ + ARM_VSI3_Handler, /* 227: VSI 3 Handler */ + ARM_VSI4_Handler, /* 228: VSI 4 Handler */ + ARM_VSI5_Handler, /* 229: VSI 5 Handler */ + ARM_VSI6_Handler, /* 230: VSI 6 Handler */ + ARM_VSI7_Handler, /* 231: VSI 7 Handler */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 b/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 new file mode 100644 index 0000000..b29bff1 --- /dev/null +++ b/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 @@ -0,0 +1,487 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __NO_RETURN __WEAK handler_name(void); \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +#ifdef CORSTONE300_AN547 +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Handler) +#ifdef CORSTONE300_FVP +DEFAULT_IRQ_HANDLER(ARM_VSI0_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI1_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI2_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI3_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI4_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI5_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI6_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI7_Handler) +#endif +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ +#ifdef CORSTONE300_AN547 + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#else + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Handler, /* 127: UART 5 combined Interrupt */ + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ +#ifdef CORSTONE300_FVP + 0, /* 131: Reserved */ + 0, /* 132: Reserved */ + 0, /* 133: Reserved */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + ARM_VSI0_Handler, /* 224: VSI 0 Handler */ + ARM_VSI1_Handler, /* 225: VSI 1 Handler */ + ARM_VSI2_Handler, /* 226: VSI 2 Handler */ + ARM_VSI3_Handler, /* 227: VSI 3 Handler */ + ARM_VSI4_Handler, /* 228: VSI 4 Handler */ + ARM_VSI5_Handler, /* 229: VSI 5 Handler */ + ARM_VSI6_Handler, /* 230: VSI 6 Handler */ + ARM_VSI7_Handler, /* 231: VSI 7 Handler */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c b/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c new file mode 100644 index 0000000..20b624e --- /dev/null +++ b/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (32000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + + /* Disable cache, because of BL2->Secure change. + If cache is enabled, then code decompression can fail or cause uncertain + behaviour after switching to main. + If cache needed to be Enabled before decompression, make sure to Clean + and Invalidate it at the begining of main(..)! + + If so, use: + SCB_InvalidateICache(); // I cache cannot be cleaned + SCB_CleanInvalidateDCache(); + */ + SCB_DisableICache(); + SCB_DisableDCache(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 b/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 new file mode 100644 index 0000000..20b624e --- /dev/null +++ b/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (32000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + + /* Disable cache, because of BL2->Secure change. + If cache is enabled, then code decompression can fail or cause uncertain + behaviour after switching to main. + If cache needed to be Enabled before decompression, make sure to Clean + and Invalidate it at the begining of main(..)! + + If so, use: + SCB_InvalidateICache(); // I cache cannot be cleaned + SCB_CleanInvalidateDCache(); + */ + SCB_DisableICache(); + SCB_DisableDCache(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/RTE/Device/SSE-310-MPS3_FVP/ac6_linker_script.sct.src b/RTE/Device/SSE-310-MPS3_FVP/ac6_linker_script.sct.src new file mode 100644 index 0000000..7820e1f --- /dev/null +++ b/RTE/Device/SSE-310-MPS3_FVP/ac6_linker_script.sct.src @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE 8 +#else +#define __STACKSEAL_SIZE 0 +#endif + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +LR_ROM0 __ROM0_BASE __ROM0_SIZE { + + ER_ROM0 __ROM0_BASE __ROM0_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + *(+RO +XO) + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) { + *(Veneer$$CMSE) + } +#endif + + RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { + *.o(.bss.noinit) + *.o(.bss.noinit.*) + } + + RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if __STACKSEAL_SIZE > 0 + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif + +#if __RAM1_SIZE > 0 + RW_RAM1 __RAM1_BASE __RAM1_SIZE { + .ANY (+RW +ZI) + } +#endif + +#if __RAM2_SIZE > 0 + RW_RAM2 __RAM2_BASE __RAM2_SIZE { + .ANY (+RW +ZI) + } +#endif + +#if __RAM3_SIZE > 0 + RW_RAM3 __RAM3_BASE __RAM3_SIZE { + .ANY (+RW +ZI) + } +#endif +} + +#if __ROM1_SIZE > 0 +LR_ROM1 __ROM1_BASE __ROM1_SIZE { + ER_ROM1 +0 __ROM1_SIZE { + .ANY (+RO +XO) + } +} +#endif + +#if __ROM2_SIZE > 0 +LR_ROM2 __ROM2_BASE __ROM2_SIZE { + ER_ROM2 +0 __ROM2_SIZE { + .ANY (+RO +XO) + } +} +#endif + +#if __ROM3_SIZE > 0 +LR_ROM3 __ROM3_BASE __ROM3_SIZE { + ER_ROM3 +0 __ROM3_SIZE { + .ANY (+RO +XO) + } +} +#endif diff --git a/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h b/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h new file mode 100644 index 0000000..af47122 --- /dev/null +++ b/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2020-2024 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +#include "RTE_Components.h" + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#ifdef RTE_MPS3_IO +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S +#endif + +/* I2C_SBCon */ +#ifdef RTE_I2C0 +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S +#endif + +/* I2S */ +#ifdef RTE_I2S +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S +#endif + +/* ARM UART Controller CMSDK */ +#ifdef RTE_USART0 +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#endif +#ifdef RTE_USART1 +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S +#endif + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#ifdef RTE_ISRAM0_MPC +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_ISRAM1_MPC +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_SRAM_MPC +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S +#endif + +#ifdef RTE_QSPI_MPC +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S +#endif + +/** System Counter Armv8-M */ +#ifdef RTE_SYSCOUNTER +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u +#endif + +/* System timer */ +#ifdef RTE_TIMEOUT +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#endif + +/* CMSDK GPIO driver structures */ +#ifdef RTE_GPIO +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S +#endif + +/* System Watchdogs */ +#ifdef RTE_WATCHDOG +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S +#endif + +/* ARM MPC SIE 310 driver structures */ +#ifdef RTE_VM0_MPC +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#endif +#ifdef RTE_VM1_MPC +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#endif +#ifdef RTE_SSRAM2_MPC +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#endif +#ifdef RTE_SSRAM3_MPC +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S +#endif + +/* ARM PPC driver structures */ +#ifdef RTE_MAIN0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN0_S +#define PPC_CORSTONE310_MAIN0_DEV PPC_CORSTONE310_MAIN0_DEV_S +#endif +#ifdef RTE_MAIN_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP0_S +#define PPC_CORSTONE310_MAIN_EXP0_DEV PPC_CORSTONE310_MAIN_EXP0_DEV_S +#endif +#ifdef RTE_MAIN_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP1_S +#define PPC_CORSTONE310_MAIN_EXP1_DEV PPC_CORSTONE310_MAIN_EXP1_DEV_S +#endif +#ifdef RTE_MAIN_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP2_S +#define PPC_CORSTONE310_MAIN_EXP2_DEV PPC_CORSTONE310_MAIN_EXP2_DEV_S +#endif +#ifdef RTE_MAIN_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP3_S +#define PPC_CORSTONE310_MAIN_EXP3_DEV PPC_CORSTONE310_MAIN_EXP3_DEV_S +#endif +#ifdef RTE_PERIPH0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH0_S +#define PPC_CORSTONE310_PERIPH0_DEV PPC_CORSTONE310_PERIPH0_DEV_S +#endif +#ifdef RTE_PERIPH1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH1_S +#define PPC_CORSTONE310_PERIPH1_DEV PPC_CORSTONE310_PERIPH1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP0_S +#define PPC_CORSTONE310_PERIPH_EXP0_DEV PPC_CORSTONE310_PERIPH_EXP0_DEV_S +#endif +#ifdef RTE_PERIPH_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP1_S +#define PPC_CORSTONE310_PERIPH_EXP1_DEV PPC_CORSTONE310_PERIPH_EXP1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP2_S +#define PPC_CORSTONE310_PERIPH_EXP2_DEV PPC_CORSTONE310_PERIPH_EXP2_DEV_S +#endif +#ifdef RTE_PERIPH_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP3_S +#define PPC_CORSTONE310_PERIPH_EXP3_DEV PPC_CORSTONE310_PERIPH_EXP3_DEV_S +#endif + +/* DMA350 */ +#ifdef RTE_DMA350 +#define DMA350_DMA0_S +#define DMA350_DMA0_DEV DMA350_DMA0_DEV_S + +#define DMA350_CH0_S +#define DMA350_DMA0_CH0_S +#define DMA350_CH1_S +#define DMA350_DMA0_CH1_S +#endif + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#ifdef RTE_SPI1 +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S +#endif + +#endif /* __DEVICE_CFG_H__ */ diff --git a/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.1.0 b/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.1.0 new file mode 100644 index 0000000..af47122 --- /dev/null +++ b/RTE/Device/SSE-310-MPS3_FVP/device_cfg.h.base@1.1.0 @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2020-2024 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +#include "RTE_Components.h" + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#ifdef RTE_MPS3_IO +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S +#endif + +/* I2C_SBCon */ +#ifdef RTE_I2C0 +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S +#endif + +/* I2S */ +#ifdef RTE_I2S +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S +#endif + +/* ARM UART Controller CMSDK */ +#ifdef RTE_USART0 +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#endif +#ifdef RTE_USART1 +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S +#endif + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#ifdef RTE_ISRAM0_MPC +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_ISRAM1_MPC +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_SRAM_MPC +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S +#endif + +#ifdef RTE_QSPI_MPC +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S +#endif + +/** System Counter Armv8-M */ +#ifdef RTE_SYSCOUNTER +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u +#endif + +/* System timer */ +#ifdef RTE_TIMEOUT +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#endif + +/* CMSDK GPIO driver structures */ +#ifdef RTE_GPIO +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S +#endif + +/* System Watchdogs */ +#ifdef RTE_WATCHDOG +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S +#endif + +/* ARM MPC SIE 310 driver structures */ +#ifdef RTE_VM0_MPC +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#endif +#ifdef RTE_VM1_MPC +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#endif +#ifdef RTE_SSRAM2_MPC +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#endif +#ifdef RTE_SSRAM3_MPC +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S +#endif + +/* ARM PPC driver structures */ +#ifdef RTE_MAIN0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN0_S +#define PPC_CORSTONE310_MAIN0_DEV PPC_CORSTONE310_MAIN0_DEV_S +#endif +#ifdef RTE_MAIN_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP0_S +#define PPC_CORSTONE310_MAIN_EXP0_DEV PPC_CORSTONE310_MAIN_EXP0_DEV_S +#endif +#ifdef RTE_MAIN_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP1_S +#define PPC_CORSTONE310_MAIN_EXP1_DEV PPC_CORSTONE310_MAIN_EXP1_DEV_S +#endif +#ifdef RTE_MAIN_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP2_S +#define PPC_CORSTONE310_MAIN_EXP2_DEV PPC_CORSTONE310_MAIN_EXP2_DEV_S +#endif +#ifdef RTE_MAIN_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_MAIN_EXP3_S +#define PPC_CORSTONE310_MAIN_EXP3_DEV PPC_CORSTONE310_MAIN_EXP3_DEV_S +#endif +#ifdef RTE_PERIPH0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH0_S +#define PPC_CORSTONE310_PERIPH0_DEV PPC_CORSTONE310_PERIPH0_DEV_S +#endif +#ifdef RTE_PERIPH1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH1_S +#define PPC_CORSTONE310_PERIPH1_DEV PPC_CORSTONE310_PERIPH1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP0_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP0_S +#define PPC_CORSTONE310_PERIPH_EXP0_DEV PPC_CORSTONE310_PERIPH_EXP0_DEV_S +#endif +#ifdef RTE_PERIPH_EXP1_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP1_S +#define PPC_CORSTONE310_PERIPH_EXP1_DEV PPC_CORSTONE310_PERIPH_EXP1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP2_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP2_S +#define PPC_CORSTONE310_PERIPH_EXP2_DEV PPC_CORSTONE310_PERIPH_EXP2_DEV_S +#endif +#ifdef RTE_PERIPH_EXP3_PPC_CORSTONE310 +#define PPC_CORSTONE310_PERIPH_EXP3_S +#define PPC_CORSTONE310_PERIPH_EXP3_DEV PPC_CORSTONE310_PERIPH_EXP3_DEV_S +#endif + +/* DMA350 */ +#ifdef RTE_DMA350 +#define DMA350_DMA0_S +#define DMA350_DMA0_DEV DMA350_DMA0_DEV_S + +#define DMA350_CH0_S +#define DMA350_DMA0_CH0_S +#define DMA350_CH1_S +#define DMA350_DMA0_CH1_S +#endif + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#ifdef RTE_SPI1 +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S +#endif + +#endif /* __DEVICE_CFG_H__ */ diff --git a/RTE/Device/SSE-310-MPS3_FVP/regions_SSE-310-MPS3_FVP.h b/RTE/Device/SSE-310-MPS3_FVP/regions_SSE-310-MPS3_FVP.h new file mode 100644 index 0000000..f8c31ac --- /dev/null +++ b/RTE/Device/SSE-310-MPS3_FVP/regions_SSE-310-MPS3_FVP.h @@ -0,0 +1,366 @@ +#ifndef REGIONS_SSE_310_MPS3_FVP_H +#define REGIONS_SSE_310_MPS3_FVP_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Device pack: ARM::V2M_MPS3_SSE_310_BSP@1.4.0 +// Device pack used to generate this file + +// ROM Configuration +// ======================= +// IROM1=<__ROM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x11000000 +#define __ROM0_BASE 0x11000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __ROM0_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __ROM0_DEFAULT 1 +// Startup +// Selects region to be used for startup code. +#define __ROM0_STARTUP 1 +// + +// + +// RAM Configuration +// ======================= +// IRAM1=<__RAM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x31000000 +#define __RAM0_BASE 0x31000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM0_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM0_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM0_NOINIT 0 +// + +// ITCM_NS=<__RAM1> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00000000 +#define __RAM1_BASE 0x00000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00008000 +#define __RAM1_SIZE 0x00008000 +// Default region +// Enables memory region globally for the application. +#define __RAM1_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM1_NOINIT 0 +// + +// SRAM_NS=<__RAM2> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x01000000 +#define __RAM2_BASE 0x01000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __RAM2_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM2_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM2_NOINIT 0 +// + +// DTCM0_NS=<__RAM3> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20000000 +#define __RAM3_BASE 0x20000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00002000 +#define __RAM3_SIZE 0x00002000 +// Default region +// Enables memory region globally for the application. +#define __RAM3_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM3_NOINIT 0 +// + +// DTCM1_NS=<__RAM4> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20002000 +#define __RAM4_BASE 0x20002000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00002000 +#define __RAM4_SIZE 0x00002000 +// Default region +// Enables memory region globally for the application. +#define __RAM4_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM4_NOINIT 0 +// + +// DTCM2_NS=<__RAM5> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20004000 +#define __RAM5_BASE 0x20004000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00002000 +#define __RAM5_SIZE 0x00002000 +// Default region +// Enables memory region globally for the application. +#define __RAM5_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM5_NOINIT 0 +// + +// DTCM3_NS=<__RAM6> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20006000 +#define __RAM6_BASE 0x20006000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00002000 +#define __RAM6_SIZE 0x00002000 +// Default region +// Enables memory region globally for the application. +#define __RAM6_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM6_NOINIT 0 +// + +// ISRAM0_NS=<__RAM7> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x21000000 +#define __RAM7_BASE 0x21000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __RAM7_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM7_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM7_NOINIT 0 +// + +// ISRAM1_NS=<__RAM8> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x21200000 +#define __RAM8_BASE 0x21200000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __RAM8_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM8_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM8_NOINIT 0 +// + +// QSPI_SRAM_NS=<__RAM9> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x28000000 +#define __RAM9_BASE 0x28000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00800000 +#define __RAM9_SIZE 0x00800000 +// Default region +// Enables memory region globally for the application. +#define __RAM9_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM9_NOINIT 0 +// + +// ITCM_S=<__RAM10> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x10000000 +#define __RAM10_BASE 0x10000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00008000 +#define __RAM10_SIZE 0x00008000 +// Default region +// Enables memory region globally for the application. +#define __RAM10_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM10_NOINIT 0 +// + +// SRAM_S=<__RAM11> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x11000000 +#define __RAM11_BASE 0x11000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __RAM11_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM11_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM11_NOINIT 0 +// + +// DTCM0_S=<__RAM12> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x30000000 +#define __RAM12_BASE 0x30000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00002000 +#define __RAM12_SIZE 0x00002000 +// Default region +// Enables memory region globally for the application. +#define __RAM12_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM12_NOINIT 0 +// + +// DTCM1_S=<__RAM13> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x30002000 +#define __RAM13_BASE 0x30002000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00002000 +#define __RAM13_SIZE 0x00002000 +// Default region +// Enables memory region globally for the application. +#define __RAM13_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM13_NOINIT 0 +// + +// DTCM2_S=<__RAM14> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x30004000 +#define __RAM14_BASE 0x30004000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00002000 +#define __RAM14_SIZE 0x00002000 +// Default region +// Enables memory region globally for the application. +#define __RAM14_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM14_NOINIT 0 +// + +// DTCM3_S=<__RAM15> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x30006000 +#define __RAM15_BASE 0x30006000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00002000 +#define __RAM15_SIZE 0x00002000 +// Default region +// Enables memory region globally for the application. +#define __RAM15_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM15_NOINIT 0 +// + +// ISRAM0_S=<__RAM16> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x31000000 +#define __RAM16_BASE 0x31000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __RAM16_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM16_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM16_NOINIT 0 +// + +// ISRAM1_S=<__RAM17> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x31200000 +#define __RAM17_BASE 0x31200000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __RAM17_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM17_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM17_NOINIT 0 +// + +// QSPI_SRAM_S=<__RAM18> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x38000000 +#define __RAM18_BASE 0x38000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00800000 +#define __RAM18_SIZE 0x00800000 +// Default region +// Enables memory region globally for the application. +#define __RAM18_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM18_NOINIT 0 +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 +// + + +#endif /* REGIONS_SSE_310_MPS3_FVP_H */ diff --git a/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c b/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c new file mode 100644 index 0000000..5d0b5ae --- /dev/null +++ b/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" +#include "system_SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __NO_RETURN __WEAK handler_name(void); \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(COMBINED_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(DMA_Channel_0_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_1_Handler) +#else +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(NPU0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Combined_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(ARM_VSI0_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI1_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI2_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI3_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI4_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI5_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI6_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI7_Handler) +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + COMBINED_PPU_Handler, /* 14: Combined PPU Handler */ + 0, /* 15: Reserved */ + NPU0_Handler, /* 16: NPU0 Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + 0, /* 26: Reserved */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + 0, /* 56: Reserved */ +#ifdef CORSTONE310_FVP + DMA_Channel_0_Handler, /* 57: DMA (DMA350) Channel 0 Handler */ + DMA_Channel_1_Handler, /* 58: DMA (DMA350) Channel 1 Handler */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#else + DMA_Ch_0_Error_Handler, /* 57: DMA Ch0 Error Handler */ + DMA_Ch_0_Terminal_Count_Handler, /* 58: DMA Ch0 Terminal Count Handler */ + DMA_Ch_0_Combined_Handler, /* 59: DMA Ch0 Combined Handler */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Combined_Handler, /* 127: UART 5 combined Interrupt */ +#ifdef CORSTONE310_FVP + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ + 0, /* 131: Reserved */ + 0, /* 132: Reserved */ + 0, /* 133: Reserved */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + ARM_VSI0_Handler, /* 224: VSI 0 Handler */ + ARM_VSI1_Handler, /* 225: VSI 1 Handler */ + ARM_VSI2_Handler, /* 226: VSI 2 Handler */ + ARM_VSI3_Handler, /* 227: VSI 3 Handler */ + ARM_VSI4_Handler, /* 228: VSI 4 Handler */ + ARM_VSI5_Handler, /* 229: VSI 5 Handler */ + ARM_VSI6_Handler, /* 230: VSI 6 Handler */ + ARM_VSI7_Handler, /* 231: VSI 7 Handler */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 b/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 new file mode 100644 index 0000000..5d0b5ae --- /dev/null +++ b/RTE/Device/SSE-310-MPS3_FVP/startup_SSE310MPS3.c.base@1.1.0 @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" +#include "system_SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __NO_RETURN __WEAK handler_name(void); \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(COMBINED_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(DMA_Channel_0_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_1_Handler) +#else +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_0_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(NPU0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Combined_Handler) +#ifdef CORSTONE310_FVP +DEFAULT_IRQ_HANDLER(ARM_VSI0_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI1_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI2_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI3_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI4_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI5_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI6_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI7_Handler) +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + COMBINED_PPU_Handler, /* 14: Combined PPU Handler */ + 0, /* 15: Reserved */ + NPU0_Handler, /* 16: NPU0 Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + 0, /* 26: Reserved */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + 0, /* 56: Reserved */ +#ifdef CORSTONE310_FVP + DMA_Channel_0_Handler, /* 57: DMA (DMA350) Channel 0 Handler */ + DMA_Channel_1_Handler, /* 58: DMA (DMA350) Channel 1 Handler */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#else + DMA_Ch_0_Error_Handler, /* 57: DMA Ch0 Error Handler */ + DMA_Ch_0_Terminal_Count_Handler, /* 58: DMA Ch0 Terminal Count Handler */ + DMA_Ch_0_Combined_Handler, /* 59: DMA Ch0 Combined Handler */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Combined_Handler, /* 127: UART 5 combined Interrupt */ +#ifdef CORSTONE310_FVP + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ + 0, /* 131: Reserved */ + 0, /* 132: Reserved */ + 0, /* 133: Reserved */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + ARM_VSI0_Handler, /* 224: VSI 0 Handler */ + ARM_VSI1_Handler, /* 225: VSI 1 Handler */ + ARM_VSI2_Handler, /* 226: VSI 2 Handler */ + ARM_VSI3_Handler, /* 227: VSI 3 Handler */ + ARM_VSI4_Handler, /* 228: VSI 4 Handler */ + ARM_VSI5_Handler, /* 229: VSI 5 Handler */ + ARM_VSI6_Handler, /* 230: VSI 6 Handler */ + ARM_VSI7_Handler, /* 231: VSI 7 Handler */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c b/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c new file mode 100644 index 0000000..d19e9e2 --- /dev/null +++ b/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (25000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + + /* Set CPDLPSTATE.RLPSTATE to 0 + Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. + Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + + /* Enable Branch Prediction */ + SCB->CCR |= SCB_CCR_BP_Msk; + + __DSB(); + __ISB(); + + /* Disable cache, because of BL2->Secure change. + If cache is enabled, then code decompression can fail or cause uncertain + behaviour after switching to main. + If cache needed to be Enabled before decompression, make sure to Clean + and Invalidate it at the begining of main(..)! + + If so, use: + SCB_InvalidateICache(); // I cache cannot be cleaned + SCB_CleanInvalidateDCache(); + */ + SCB_DisableICache(); + SCB_DisableDCache(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 b/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 new file mode 100644 index 0000000..d19e9e2 --- /dev/null +++ b/RTE/Device/SSE-310-MPS3_FVP/system_SSE310MPS3.c.base@1.1.0 @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE310MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (25000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + + /* Set CPDLPSTATE.RLPSTATE to 0 + Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. + Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + + /* Enable Branch Prediction */ + SCB->CCR |= SCB_CCR_BP_Msk; + + __DSB(); + __ISB(); + + /* Disable cache, because of BL2->Secure change. + If cache is enabled, then code decompression can fail or cause uncertain + behaviour after switching to main. + If cache needed to be Enabled before decompression, make sure to Clean + and Invalidate it at the begining of main(..)! + + If so, use: + SCB_InvalidateICache(); // I cache cannot be cleaned + SCB_CleanInvalidateDCache(); + */ + SCB_DisableICache(); + SCB_DisableDCache(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src b/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src new file mode 100644 index 0000000..7820e1f --- /dev/null +++ b/RTE/Device/SSE-315-FVP/ac6_linker_script.sct.src @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE 8 +#else +#define __STACKSEAL_SIZE 0 +#endif + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +LR_ROM0 __ROM0_BASE __ROM0_SIZE { + + ER_ROM0 __ROM0_BASE __ROM0_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + *(+RO +XO) + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) { + *(Veneer$$CMSE) + } +#endif + + RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { + *.o(.bss.noinit) + *.o(.bss.noinit.*) + } + + RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if __STACKSEAL_SIZE > 0 + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif + +#if __RAM1_SIZE > 0 + RW_RAM1 __RAM1_BASE __RAM1_SIZE { + .ANY (+RW +ZI) + } +#endif + +#if __RAM2_SIZE > 0 + RW_RAM2 __RAM2_BASE __RAM2_SIZE { + .ANY (+RW +ZI) + } +#endif + +#if __RAM3_SIZE > 0 + RW_RAM3 __RAM3_BASE __RAM3_SIZE { + .ANY (+RW +ZI) + } +#endif +} + +#if __ROM1_SIZE > 0 +LR_ROM1 __ROM1_BASE __ROM1_SIZE { + ER_ROM1 +0 __ROM1_SIZE { + .ANY (+RO +XO) + } +} +#endif + +#if __ROM2_SIZE > 0 +LR_ROM2 __ROM2_BASE __ROM2_SIZE { + ER_ROM2 +0 __ROM2_SIZE { + .ANY (+RO +XO) + } +} +#endif + +#if __ROM3_SIZE > 0 +LR_ROM3 __ROM3_BASE __ROM3_SIZE { + ER_ROM3 +0 __ROM3_SIZE { + .ANY (+RO +XO) + } +} +#endif diff --git a/RTE/Device/SSE-315-FVP/device_cfg.h b/RTE/Device/SSE-315-FVP/device_cfg.h new file mode 100644 index 0000000..008ff9a --- /dev/null +++ b/RTE/Device/SSE-315-FVP/device_cfg.h @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2020-2024 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +#include "RTE_Components.h" + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#ifdef RTE_MPS3_IO +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S +#endif + +/* I2C_SBCon */ +#ifdef RTE_I2C0 +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S +#endif +#ifdef RTE_I2C1 +#define I2C1_SBCON_S +#define I2C1_SBCON_DEV I2C1_SBCON_DEV_S +#endif +#ifdef RTE_I2C2 +#define I2C2_SBCON_S +#define I2C2_SBCON_DEV I2C2_SBCON_DEV_S +#endif + +/* I2S */ +#ifdef RTE_I2S +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S +#endif + +/* ARM UART Controller CMSDK */ +#ifdef RTE_USART0 +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#endif +#ifdef RTE_USART1 +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S +#endif +#ifdef RTE_USART2 +#define UART2_CMSDK_S +#define UART2_CMSDK_DEV UART2_CMSDK_DEV_S +#endif +#ifdef RTE_USART3 +#define UART3_CMSDK_S +#define UART3_CMSDK_DEV UART3_CMSDK_DEV_S +#endif +#ifdef RTE_USART4 +#define UART4_CMSDK_S +#define UART4_CMSDK_DEV UART4_CMSDK_DEV_S +#endif +#ifdef RTE_USART5 +#define UART5_CMSDK_S +#define UART5_CMSDK_DEV UART5_CMSDK_DEV_S +#endif + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#ifdef RTE_ISRAM0_MPC +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_ISRAM1_MPC +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_SRAM_MPC +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S +#endif + +#ifdef RTE_QSPI_MPC +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S +#endif + +/** System Counter Armv8-M */ +#ifdef RTE_SYSCOUNTER +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u +#endif + +/* System timer */ +#ifdef RTE_TIMEOUT +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#endif + +/* CMSDK GPIO driver structures */ +#ifdef RTE_GPIO +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S +#endif + +/* System Watchdogs */ +#ifdef RTE_WATCHDOG +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S +#endif + +/* ARM MPC SIE 315 driver structures */ +#ifdef RTE_VM0_MPC +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#endif +#ifdef RTE_VM1_MPC +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#endif +#ifdef RTE_SSRAM2_MPC +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#endif +#ifdef RTE_SSRAM3_MPC +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S +#endif + +/* ARM PPC driver structures */ +#ifdef RTE_MAIN0_PPC_CORSTONE315 +#define PPC_CORSTONE315_MAIN0_S +#define PPC_CORSTONE315_MAIN0_DEV PPC_CORSTONE315_MAIN0_DEV_S +#endif +#ifdef RTE_MAIN_EXP0_PPC_CORSTONE315 +#define PPC_CORSTONE315_MAIN_EXP0_S +#define PPC_CORSTONE315_MAIN_EXP0_DEV PPC_CORSTONE315_MAIN_EXP0_DEV_S +#endif +#ifdef RTE_MAIN_EXP1_PPC_CORSTONE315 +#define PPC_CORSTONE315_MAIN_EXP1_S +#define PPC_CORSTONE315_MAIN_EXP1_DEV PPC_CORSTONE315_MAIN_EXP1_DEV_S +#endif +#ifdef RTE_MAIN_EXP2_PPC_CORSTONE315 +#define PPC_CORSTONE315_MAIN_EXP2_S +#define PPC_CORSTONE315_MAIN_EXP2_DEV PPC_CORSTONE315_MAIN_EXP2_DEV_S +#endif +#ifdef RTE_MAIN_EXP3_PPC_CORSTONE315 +#define PPC_CORSTONE315_MAIN_EXP3_S +#define PPC_CORSTONE315_MAIN_EXP3_DEV PPC_CORSTONE315_MAIN_EXP3_DEV_S +#endif +#ifdef RTE_PERIPH0_PPC_CORSTONE315 +#define PPC_CORSTONE315_PERIPH0_S +#define PPC_CORSTONE315_PERIPH0_DEV PPC_CORSTONE315_PERIPH0_DEV_S +#endif +#ifdef RTE_PERIPH1_PPC_CORSTONE315 +#define PPC_CORSTONE315_PERIPH1_S +#define PPC_CORSTONE315_PERIPH1_DEV PPC_CORSTONE315_PERIPH1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP0_PPC_CORSTONE315 +#define PPC_CORSTONE315_PERIPH_EXP0_S +#define PPC_CORSTONE315_PERIPH_EXP0_DEV PPC_CORSTONE315_PERIPH_EXP0_DEV_S +#endif +#ifdef RTE_PERIPH_EXP1_PPC_CORSTONE315 +#define PPC_CORSTONE315_PERIPH_EXP1_S +#define PPC_CORSTONE315_PERIPH_EXP1_DEV PPC_CORSTONE315_PERIPH_EXP1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP2_PPC_CORSTONE315 +#define PPC_CORSTONE315_PERIPH_EXP2_S +#define PPC_CORSTONE315_PERIPH_EXP2_DEV PPC_CORSTONE315_PERIPH_EXP2_DEV_S +#endif +#ifdef RTE_PERIPH_EXP3_PPC_CORSTONE315 +#define PPC_CORSTONE315_PERIPH_EXP3_S +#define PPC_CORSTONE315_PERIPH_EXP3_DEV PPC_CORSTONE315_PERIPH_EXP3_DEV_S +#endif + +/* DMA350 */ +#ifdef RTE_DMA350 +#define DMA350_DMA0_S +#define DMA350_DMA0_DEV DMA350_DMA0_DEV_S + +#define DMA350_CH0_S +#define DMA350_DMA0_CH0_S +#define DMA350_CH1_S +#define DMA350_DMA0_CH1_S +#endif + +/* Key Management Unit */ +#ifdef RTE_KMU +#define KMU_S +#define KMU_DEV KMU_DEV_S +#endif + +/* Lifecycle Manager */ +#ifdef RTE_LCM +#define LCM_S +#define LCM_DEV LCM_DEV_S +#endif + +/* Security Alarm Manager */ +#ifdef RTE_SAM +#define SAM_S +#define SAM_DEV SAM_DEV_S +#endif + +/* HDLCD Video */ +#ifdef RTE_HDLCD +#define HDLCD_NS +#define HDLCD_DEV HDLCD_DEV_NS +#endif + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#ifdef RTE_SPI0 +#define SPI0_PL022_S +#define SPI0_PL022_DEV SPI0_PL022_DEV_S +#endif +#ifdef RTE_SPI1 +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S +#endif +#ifdef RTE_SPI2 +#define SPI2_PL022_S +#define SPI2_PL022_DEV SPI2_PL022_DEV_S +#endif + +#endif /* __DEVICE_CFG_H__ */ diff --git a/RTE/Device/SSE-315-FVP/device_cfg.h.base@1.1.0 b/RTE/Device/SSE-315-FVP/device_cfg.h.base@1.1.0 new file mode 100644 index 0000000..008ff9a --- /dev/null +++ b/RTE/Device/SSE-315-FVP/device_cfg.h.base@1.1.0 @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2020-2024 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +#include "RTE_Components.h" + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#ifdef RTE_MPS3_IO +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S +#endif + +/* I2C_SBCon */ +#ifdef RTE_I2C0 +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S +#endif +#ifdef RTE_I2C1 +#define I2C1_SBCON_S +#define I2C1_SBCON_DEV I2C1_SBCON_DEV_S +#endif +#ifdef RTE_I2C2 +#define I2C2_SBCON_S +#define I2C2_SBCON_DEV I2C2_SBCON_DEV_S +#endif + +/* I2S */ +#ifdef RTE_I2S +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S +#endif + +/* ARM UART Controller CMSDK */ +#ifdef RTE_USART0 +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#endif +#ifdef RTE_USART1 +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S +#endif +#ifdef RTE_USART2 +#define UART2_CMSDK_S +#define UART2_CMSDK_DEV UART2_CMSDK_DEV_S +#endif +#ifdef RTE_USART3 +#define UART3_CMSDK_S +#define UART3_CMSDK_DEV UART3_CMSDK_DEV_S +#endif +#ifdef RTE_USART4 +#define UART4_CMSDK_S +#define UART4_CMSDK_DEV UART4_CMSDK_DEV_S +#endif +#ifdef RTE_USART5 +#define UART5_CMSDK_S +#define UART5_CMSDK_DEV UART5_CMSDK_DEV_S +#endif + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#ifdef RTE_ISRAM0_MPC +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_ISRAM1_MPC +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_SRAM_MPC +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S +#endif + +#ifdef RTE_QSPI_MPC +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S +#endif + +/** System Counter Armv8-M */ +#ifdef RTE_SYSCOUNTER +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u +#endif + +/* System timer */ +#ifdef RTE_TIMEOUT +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#endif + +/* CMSDK GPIO driver structures */ +#ifdef RTE_GPIO +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S +#endif + +/* System Watchdogs */ +#ifdef RTE_WATCHDOG +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S +#endif + +/* ARM MPC SIE 315 driver structures */ +#ifdef RTE_VM0_MPC +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#endif +#ifdef RTE_VM1_MPC +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#endif +#ifdef RTE_SSRAM2_MPC +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#endif +#ifdef RTE_SSRAM3_MPC +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S +#endif + +/* ARM PPC driver structures */ +#ifdef RTE_MAIN0_PPC_CORSTONE315 +#define PPC_CORSTONE315_MAIN0_S +#define PPC_CORSTONE315_MAIN0_DEV PPC_CORSTONE315_MAIN0_DEV_S +#endif +#ifdef RTE_MAIN_EXP0_PPC_CORSTONE315 +#define PPC_CORSTONE315_MAIN_EXP0_S +#define PPC_CORSTONE315_MAIN_EXP0_DEV PPC_CORSTONE315_MAIN_EXP0_DEV_S +#endif +#ifdef RTE_MAIN_EXP1_PPC_CORSTONE315 +#define PPC_CORSTONE315_MAIN_EXP1_S +#define PPC_CORSTONE315_MAIN_EXP1_DEV PPC_CORSTONE315_MAIN_EXP1_DEV_S +#endif +#ifdef RTE_MAIN_EXP2_PPC_CORSTONE315 +#define PPC_CORSTONE315_MAIN_EXP2_S +#define PPC_CORSTONE315_MAIN_EXP2_DEV PPC_CORSTONE315_MAIN_EXP2_DEV_S +#endif +#ifdef RTE_MAIN_EXP3_PPC_CORSTONE315 +#define PPC_CORSTONE315_MAIN_EXP3_S +#define PPC_CORSTONE315_MAIN_EXP3_DEV PPC_CORSTONE315_MAIN_EXP3_DEV_S +#endif +#ifdef RTE_PERIPH0_PPC_CORSTONE315 +#define PPC_CORSTONE315_PERIPH0_S +#define PPC_CORSTONE315_PERIPH0_DEV PPC_CORSTONE315_PERIPH0_DEV_S +#endif +#ifdef RTE_PERIPH1_PPC_CORSTONE315 +#define PPC_CORSTONE315_PERIPH1_S +#define PPC_CORSTONE315_PERIPH1_DEV PPC_CORSTONE315_PERIPH1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP0_PPC_CORSTONE315 +#define PPC_CORSTONE315_PERIPH_EXP0_S +#define PPC_CORSTONE315_PERIPH_EXP0_DEV PPC_CORSTONE315_PERIPH_EXP0_DEV_S +#endif +#ifdef RTE_PERIPH_EXP1_PPC_CORSTONE315 +#define PPC_CORSTONE315_PERIPH_EXP1_S +#define PPC_CORSTONE315_PERIPH_EXP1_DEV PPC_CORSTONE315_PERIPH_EXP1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP2_PPC_CORSTONE315 +#define PPC_CORSTONE315_PERIPH_EXP2_S +#define PPC_CORSTONE315_PERIPH_EXP2_DEV PPC_CORSTONE315_PERIPH_EXP2_DEV_S +#endif +#ifdef RTE_PERIPH_EXP3_PPC_CORSTONE315 +#define PPC_CORSTONE315_PERIPH_EXP3_S +#define PPC_CORSTONE315_PERIPH_EXP3_DEV PPC_CORSTONE315_PERIPH_EXP3_DEV_S +#endif + +/* DMA350 */ +#ifdef RTE_DMA350 +#define DMA350_DMA0_S +#define DMA350_DMA0_DEV DMA350_DMA0_DEV_S + +#define DMA350_CH0_S +#define DMA350_DMA0_CH0_S +#define DMA350_CH1_S +#define DMA350_DMA0_CH1_S +#endif + +/* Key Management Unit */ +#ifdef RTE_KMU +#define KMU_S +#define KMU_DEV KMU_DEV_S +#endif + +/* Lifecycle Manager */ +#ifdef RTE_LCM +#define LCM_S +#define LCM_DEV LCM_DEV_S +#endif + +/* Security Alarm Manager */ +#ifdef RTE_SAM +#define SAM_S +#define SAM_DEV SAM_DEV_S +#endif + +/* HDLCD Video */ +#ifdef RTE_HDLCD +#define HDLCD_NS +#define HDLCD_DEV HDLCD_DEV_NS +#endif + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#ifdef RTE_SPI0 +#define SPI0_PL022_S +#define SPI0_PL022_DEV SPI0_PL022_DEV_S +#endif +#ifdef RTE_SPI1 +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S +#endif +#ifdef RTE_SPI2 +#define SPI2_PL022_S +#define SPI2_PL022_DEV SPI2_PL022_DEV_S +#endif + +#endif /* __DEVICE_CFG_H__ */ diff --git a/RTE/Device/SSE-315-FVP/regions_SSE-315-FVP.h b/RTE/Device/SSE-315-FVP/regions_SSE-315-FVP.h new file mode 100644 index 0000000..55cf3f2 --- /dev/null +++ b/RTE/Device/SSE-315-FVP/regions_SSE-315-FVP.h @@ -0,0 +1,366 @@ +#ifndef REGIONS_SSE_315_FVP_H +#define REGIONS_SSE_315_FVP_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Device pack: ARM::SSE_315_BSP@1.0.0 +// Device pack used to generate this file + +// ROM Configuration +// ======================= +// IROM1=<__ROM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x11000000 +#define __ROM0_BASE 0x11000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __ROM0_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __ROM0_DEFAULT 1 +// Startup +// Selects region to be used for startup code. +#define __ROM0_STARTUP 1 +// + +// + +// RAM Configuration +// ======================= +// IRAM1=<__RAM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x31000000 +#define __RAM0_BASE 0x31000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM0_SIZE 0x00020000 +// Default region +// Enables memory region globally for the application. +#define __RAM0_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM0_NOINIT 0 +// + +// ITCM_NS=<__RAM1> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00000000 +#define __RAM1_BASE 0x00000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00008000 +#define __RAM1_SIZE 0x00008000 +// Default region +// Enables memory region globally for the application. +#define __RAM1_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM1_NOINIT 0 +// + +// SRAM_NS=<__RAM2> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x01000000 +#define __RAM2_BASE 0x01000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __RAM2_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM2_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM2_NOINIT 0 +// + +// DTCM0_NS=<__RAM3> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20000000 +#define __RAM3_BASE 0x20000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00002000 +#define __RAM3_SIZE 0x00002000 +// Default region +// Enables memory region globally for the application. +#define __RAM3_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM3_NOINIT 0 +// + +// DTCM1_NS=<__RAM4> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20002000 +#define __RAM4_BASE 0x20002000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00002000 +#define __RAM4_SIZE 0x00002000 +// Default region +// Enables memory region globally for the application. +#define __RAM4_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM4_NOINIT 0 +// + +// DTCM2_NS=<__RAM5> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20004000 +#define __RAM5_BASE 0x20004000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00002000 +#define __RAM5_SIZE 0x00002000 +// Default region +// Enables memory region globally for the application. +#define __RAM5_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM5_NOINIT 0 +// + +// DTCM3_NS=<__RAM6> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20006000 +#define __RAM6_BASE 0x20006000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00002000 +#define __RAM6_SIZE 0x00002000 +// Default region +// Enables memory region globally for the application. +#define __RAM6_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM6_NOINIT 0 +// + +// ISRAM0_NS=<__RAM7> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x21000000 +#define __RAM7_BASE 0x21000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __RAM7_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM7_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM7_NOINIT 0 +// + +// ISRAM1_NS=<__RAM8> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x21200000 +#define __RAM8_BASE 0x21200000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __RAM8_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM8_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM8_NOINIT 0 +// + +// QSPI_SRAM_NS=<__RAM9> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x28000000 +#define __RAM9_BASE 0x28000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00800000 +#define __RAM9_SIZE 0x00800000 +// Default region +// Enables memory region globally for the application. +#define __RAM9_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM9_NOINIT 0 +// + +// ITCM_S=<__RAM10> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x10000000 +#define __RAM10_BASE 0x10000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00008000 +#define __RAM10_SIZE 0x00008000 +// Default region +// Enables memory region globally for the application. +#define __RAM10_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM10_NOINIT 0 +// + +// SRAM_S=<__RAM11> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x11000000 +#define __RAM11_BASE 0x11000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __RAM11_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM11_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM11_NOINIT 0 +// + +// DTCM0_S=<__RAM12> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x30000000 +#define __RAM12_BASE 0x30000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00002000 +#define __RAM12_SIZE 0x00002000 +// Default region +// Enables memory region globally for the application. +#define __RAM12_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM12_NOINIT 0 +// + +// DTCM1_S=<__RAM13> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x30002000 +#define __RAM13_BASE 0x30002000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00002000 +#define __RAM13_SIZE 0x00002000 +// Default region +// Enables memory region globally for the application. +#define __RAM13_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM13_NOINIT 0 +// + +// DTCM2_S=<__RAM14> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x30004000 +#define __RAM14_BASE 0x30004000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00002000 +#define __RAM14_SIZE 0x00002000 +// Default region +// Enables memory region globally for the application. +#define __RAM14_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM14_NOINIT 0 +// + +// DTCM3_S=<__RAM15> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x30006000 +#define __RAM15_BASE 0x30006000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00002000 +#define __RAM15_SIZE 0x00002000 +// Default region +// Enables memory region globally for the application. +#define __RAM15_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM15_NOINIT 0 +// + +// ISRAM0_S=<__RAM16> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x31000000 +#define __RAM16_BASE 0x31000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __RAM16_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM16_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM16_NOINIT 0 +// + +// ISRAM1_S=<__RAM17> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x31200000 +#define __RAM17_BASE 0x31200000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __RAM17_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM17_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM17_NOINIT 0 +// + +// QSPI_SRAM_S=<__RAM18> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x38000000 +#define __RAM18_BASE 0x38000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00800000 +#define __RAM18_SIZE 0x00800000 +// Default region +// Enables memory region globally for the application. +#define __RAM18_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM18_NOINIT 0 +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 +// + + +#endif /* REGIONS_SSE_315_FVP_H */ diff --git a/RTE/Device/SSE-315-FVP/startup_SSE315.c b/RTE/Device/SSE-315-FVP/startup_SSE315.c new file mode 100644 index 0000000..335f91f --- /dev/null +++ b/RTE/Device/SSE-315-FVP/startup_SSE315.c @@ -0,0 +1,410 @@ +/* + * Copyright (c) 2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE315.h" +#include "system_SSE315.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __NO_RETURN __WEAK handler_name(void); \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(COMBINED_PPU_Handler) +DEFAULT_IRQ_HANDLER(SDC_Handler) +DEFAULT_IRQ_HANDLER(KMU_Handler) +DEFAULT_IRQ_HANDLER(DMA_SEC_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_NONSEC_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_SECURITY_VIOLATION_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) +DEFAULT_IRQ_HANDLER(SAM_Critical_Severity_Fault_Handler) +DEFAULT_IRQ_HANDLER(SAM_Severity_Fault_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_0_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_1_Handler) +DEFAULT_IRQ_HANDLER(NPU0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(RTC_Handler) +DEFAULT_IRQ_HANDLER(ISP_C55_Handler) +DEFAULT_IRQ_HANDLER(HDLCD_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI0_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI1_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI2_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI3_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI4_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI5_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI6_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI7_Handler) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + COMBINED_PPU_Handler, /* 14: Combined PPU Handler */ + SDC_Handler, /* 15: Secure Debug Channel Handler */ + NPU0_Handler, /* 16: NPU0 Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + KMU_Handler, /* 20: KMU Handler */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + DMA_SEC_Combined_Handler, /* 24: DMA Secure Combined Handler */ + DMA_NONSEC_Combined_Handler, /* 25: DMA Non-Secure Combined Handler */ + DMA_SECURITY_VIOLATION_Handler, /* 26: DMA Security Violation Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + SAM_Critical_Severity_Fault_Handler, /* 30: SAM Critical Severity Fault Handler */ + SAM_Severity_Fault_Handler, /* 31: SAM Severity Fault Handler */ + + /* External interrupts */ + 0, /* 32: Reserved */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + 0, /* 51: Reserved */ + 0, /* 52: Reserved */ + 0, /* 53: Reserved */ + 0, /* 54: Reserved */ + 0, /* 55: Reserved */ + 0, /* 56: Reserved */ + DMA_Channel_0_Handler, /* 57: DMA (DMA350) Channel 0 Handler */ + DMA_Channel_1_Handler, /* 58: DMA (DMA350) Channel 1 Handler */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + 0, /* 73: Reserved */ + 0, /* 74: Reserved */ + 0, /* 75: Reserved */ + 0, /* 76: Reserved */ + 0, /* 77: Reserved */ + 0, /* 78: Reserved */ + 0, /* 79: Reserved */ + 0, /* 80: Reserved */ + 0, /* 81: Reserved */ + 0, /* 82: Reserved */ + 0, /* 83: Reserved */ + 0, /* 84: Reserved */ + 0, /* 85: Reserved */ + 0, /* 86: Reserved */ + 0, /* 87: Reserved */ + 0, /* 88: Reserved */ + 0, /* 89: Reserved */ + 0, /* 90: Reserved */ + 0, /* 91: Reserved */ + 0, /* 92: Reserved */ + 0, /* 93: Reserved */ + 0, /* 94: Reserved */ + 0, /* 95: Reserved */ + 0, /* 96: Reserved */ + 0, /* 97: Reserved */ + 0, /* 98: Reserved */ + 0, /* 99: Reserved */ + 0, /* 100: Reserved */ + 0, /* 101: Reserved */ + 0, /* 102: Reserved */ + 0, /* 103: Reserved */ + 0, /* 104: Reserved */ + 0, /* 105: Reserved */ + 0, /* 106: Reserved */ + 0, /* 107: Reserved */ + 0, /* 108: Reserved */ + 0, /* 109: Reserved */ + 0, /* 110: Reserved */ + 0, /* 111: Reserved */ + 0, /* 112: Reserved */ + 0, /* 113: Reserved */ + 0, /* 114: Reserved */ + 0, /* 115: Reserved */ + 0, /* 116: Reserved */ + 0, /* 117: Reserved */ + 0, /* 118: Reserved */ + 0, /* 119: Reserved */ + 0, /* 120: Reserved */ + 0, /* 121: Reserved */ + 0, /* 122: Reserved */ + 0, /* 123: Reserved */ + 0, /* 124: Reserved */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + 0, /* 127: Reserved */ + RTC_Handler, /* 128: UART 5 combined Interrupt */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ + 0, /* 131: Reserved */ + ISP_C55_Handler, /* 132: ISP C55 Handler */ + HDLCD_Handler, /* 133: HDLCD Handler */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + ARM_VSI0_Handler, /* 224: VSI 0 Handler */ + ARM_VSI1_Handler, /* 225: VSI 1 Handler */ + ARM_VSI2_Handler, /* 226: VSI 2 Handler */ + ARM_VSI3_Handler, /* 227: VSI 3 Handler */ + ARM_VSI4_Handler, /* 228: VSI 4 Handler */ + ARM_VSI5_Handler, /* 229: VSI 5 Handler */ + ARM_VSI6_Handler, /* 230: VSI 6 Handler */ + ARM_VSI7_Handler, /* 231: VSI 7 Handler */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/RTE/Device/SSE-315-FVP/startup_SSE315.c.base@1.1.0 b/RTE/Device/SSE-315-FVP/startup_SSE315.c.base@1.1.0 new file mode 100644 index 0000000..335f91f --- /dev/null +++ b/RTE/Device/SSE-315-FVP/startup_SSE315.c.base@1.1.0 @@ -0,0 +1,410 @@ +/* + * Copyright (c) 2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE315.h" +#include "system_SSE315.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __NO_RETURN __WEAK handler_name(void); \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(COMBINED_PPU_Handler) +DEFAULT_IRQ_HANDLER(SDC_Handler) +DEFAULT_IRQ_HANDLER(KMU_Handler) +DEFAULT_IRQ_HANDLER(DMA_SEC_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_NONSEC_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_SECURITY_VIOLATION_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) +DEFAULT_IRQ_HANDLER(SAM_Critical_Severity_Fault_Handler) +DEFAULT_IRQ_HANDLER(SAM_Severity_Fault_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_0_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_1_Handler) +DEFAULT_IRQ_HANDLER(NPU0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(RTC_Handler) +DEFAULT_IRQ_HANDLER(ISP_C55_Handler) +DEFAULT_IRQ_HANDLER(HDLCD_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI0_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI1_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI2_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI3_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI4_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI5_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI6_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI7_Handler) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + COMBINED_PPU_Handler, /* 14: Combined PPU Handler */ + SDC_Handler, /* 15: Secure Debug Channel Handler */ + NPU0_Handler, /* 16: NPU0 Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + KMU_Handler, /* 20: KMU Handler */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + DMA_SEC_Combined_Handler, /* 24: DMA Secure Combined Handler */ + DMA_NONSEC_Combined_Handler, /* 25: DMA Non-Secure Combined Handler */ + DMA_SECURITY_VIOLATION_Handler, /* 26: DMA Security Violation Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + SAM_Critical_Severity_Fault_Handler, /* 30: SAM Critical Severity Fault Handler */ + SAM_Severity_Fault_Handler, /* 31: SAM Severity Fault Handler */ + + /* External interrupts */ + 0, /* 32: Reserved */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + 0, /* 51: Reserved */ + 0, /* 52: Reserved */ + 0, /* 53: Reserved */ + 0, /* 54: Reserved */ + 0, /* 55: Reserved */ + 0, /* 56: Reserved */ + DMA_Channel_0_Handler, /* 57: DMA (DMA350) Channel 0 Handler */ + DMA_Channel_1_Handler, /* 58: DMA (DMA350) Channel 1 Handler */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + 0, /* 73: Reserved */ + 0, /* 74: Reserved */ + 0, /* 75: Reserved */ + 0, /* 76: Reserved */ + 0, /* 77: Reserved */ + 0, /* 78: Reserved */ + 0, /* 79: Reserved */ + 0, /* 80: Reserved */ + 0, /* 81: Reserved */ + 0, /* 82: Reserved */ + 0, /* 83: Reserved */ + 0, /* 84: Reserved */ + 0, /* 85: Reserved */ + 0, /* 86: Reserved */ + 0, /* 87: Reserved */ + 0, /* 88: Reserved */ + 0, /* 89: Reserved */ + 0, /* 90: Reserved */ + 0, /* 91: Reserved */ + 0, /* 92: Reserved */ + 0, /* 93: Reserved */ + 0, /* 94: Reserved */ + 0, /* 95: Reserved */ + 0, /* 96: Reserved */ + 0, /* 97: Reserved */ + 0, /* 98: Reserved */ + 0, /* 99: Reserved */ + 0, /* 100: Reserved */ + 0, /* 101: Reserved */ + 0, /* 102: Reserved */ + 0, /* 103: Reserved */ + 0, /* 104: Reserved */ + 0, /* 105: Reserved */ + 0, /* 106: Reserved */ + 0, /* 107: Reserved */ + 0, /* 108: Reserved */ + 0, /* 109: Reserved */ + 0, /* 110: Reserved */ + 0, /* 111: Reserved */ + 0, /* 112: Reserved */ + 0, /* 113: Reserved */ + 0, /* 114: Reserved */ + 0, /* 115: Reserved */ + 0, /* 116: Reserved */ + 0, /* 117: Reserved */ + 0, /* 118: Reserved */ + 0, /* 119: Reserved */ + 0, /* 120: Reserved */ + 0, /* 121: Reserved */ + 0, /* 122: Reserved */ + 0, /* 123: Reserved */ + 0, /* 124: Reserved */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + 0, /* 127: Reserved */ + RTC_Handler, /* 128: UART 5 combined Interrupt */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ + 0, /* 131: Reserved */ + ISP_C55_Handler, /* 132: ISP C55 Handler */ + HDLCD_Handler, /* 133: HDLCD Handler */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + ARM_VSI0_Handler, /* 224: VSI 0 Handler */ + ARM_VSI1_Handler, /* 225: VSI 1 Handler */ + ARM_VSI2_Handler, /* 226: VSI 2 Handler */ + ARM_VSI3_Handler, /* 227: VSI 3 Handler */ + ARM_VSI4_Handler, /* 228: VSI 4 Handler */ + ARM_VSI5_Handler, /* 229: VSI 5 Handler */ + ARM_VSI6_Handler, /* 230: VSI 6 Handler */ + ARM_VSI7_Handler, /* 231: VSI 7 Handler */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/RTE/Device/SSE-315-FVP/system_SSE315.c b/RTE/Device/SSE-315-FVP/system_SSE315.c new file mode 100644 index 0000000..81d74c3 --- /dev/null +++ b/RTE/Device/SSE-315-FVP/system_SSE315.c @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE315.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (25000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + + /* Set CPDLPSTATE.RLPSTATE to 0 + Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. + Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + + /* Enable Branch Prediction */ + SCB->CCR |= SCB_CCR_BP_Msk; + + __DSB(); + __ISB(); + + /* Disable cache, because of BL2->Secure change. + If cache is enabled, then code decompression can fail or cause uncertain + behaviour after switching to main. + If cache needed to be Enabled before decompression, make sure to Clean + and Invalidate it at the begining of main(..)! + + If so, use: + SCB_InvalidateICache(); // I cache cannot be cleaned + SCB_CleanInvalidateDCache(); + */ + SCB_DisableICache(); + SCB_DisableDCache(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/RTE/Device/SSE-315-FVP/system_SSE315.c.base@1.1.0 b/RTE/Device/SSE-315-FVP/system_SSE315.c.base@1.1.0 new file mode 100644 index 0000000..81d74c3 --- /dev/null +++ b/RTE/Device/SSE-315-FVP/system_SSE315.c.base@1.1.0 @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE315.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (25000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + + /* Set CPDLPSTATE.RLPSTATE to 0 + Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. + Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + + /* Enable Branch Prediction */ + SCB->CCR |= SCB_CCR_BP_Msk; + + __DSB(); + __ISB(); + + /* Disable cache, because of BL2->Secure change. + If cache is enabled, then code decompression can fail or cause uncertain + behaviour after switching to main. + If cache needed to be Enabled before decompression, make sure to Clean + and Invalidate it at the begining of main(..)! + + If so, use: + SCB_InvalidateICache(); // I cache cannot be cleaned + SCB_CleanInvalidateDCache(); + */ + SCB_DisableICache(); + SCB_DisableDCache(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/RTE/_Debug_CM0/RTE_Components.h b/RTE/_Debug_CM0/RTE_Components.h new file mode 100644 index 0000000..a3394a1 --- /dev/null +++ b/RTE/_Debug_CM0/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Debug+CM0' + * Target: 'Debug+CM0' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "CMSDK_CM0.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.3 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Debug_CM0plus/RTE_Components.h b/RTE/_Debug_CM0plus/RTE_Components.h new file mode 100644 index 0000000..1ed9b7c --- /dev/null +++ b/RTE/_Debug_CM0plus/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Debug+CM0plus' + * Target: 'Debug+CM0plus' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "CMSDK_CM0plus.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.3 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Debug_CM23/RTE_Components.h b/RTE/_Debug_CM23/RTE_Components.h new file mode 100644 index 0000000..692b585 --- /dev/null +++ b/RTE/_Debug_CM23/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Debug+CM23' + * Target: 'Debug+CM23' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "IOTKit_CM23.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.0 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Debug_CM3/RTE_Components.h b/RTE/_Debug_CM3/RTE_Components.h new file mode 100644 index 0000000..51483af --- /dev/null +++ b/RTE/_Debug_CM3/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Debug+CM3' + * Target: 'Debug+CM3' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "CMSDK_CM3.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.3 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Debug_CM33/RTE_Components.h b/RTE/_Debug_CM33/RTE_Components.h new file mode 100644 index 0000000..e17c129 --- /dev/null +++ b/RTE/_Debug_CM33/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Debug+CM33' + * Target: 'Debug+CM33' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "IOTKit_CM33.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.0 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Debug_CM33_FP/RTE_Components.h b/RTE/_Debug_CM33_FP/RTE_Components.h new file mode 100644 index 0000000..44b8307 --- /dev/null +++ b/RTE/_Debug_CM33_FP/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Debug+CM33_FP' + * Target: 'Debug+CM33_FP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "IOTKit_CM33_FP.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.0 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Debug_CM4/RTE_Components.h b/RTE/_Debug_CM4/RTE_Components.h new file mode 100644 index 0000000..24a397c --- /dev/null +++ b/RTE/_Debug_CM4/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Debug+CM4' + * Target: 'Debug+CM4' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "CMSDK_CM4.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.3 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Debug_CM4_FP/RTE_Components.h b/RTE/_Debug_CM4_FP/RTE_Components.h new file mode 100644 index 0000000..da0e24a --- /dev/null +++ b/RTE/_Debug_CM4_FP/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Debug+CM4_FP' + * Target: 'Debug+CM4_FP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "CMSDK_CM4_FP.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.3 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Debug_CM7/RTE_Components.h b/RTE/_Debug_CM7/RTE_Components.h new file mode 100644 index 0000000..46b2f8a --- /dev/null +++ b/RTE/_Debug_CM7/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Debug+CM7' + * Target: 'Debug+CM7' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "CMSDK_CM7.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.3 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Debug_CM7_DP/RTE_Components.h b/RTE/_Debug_CM7_DP/RTE_Components.h new file mode 100644 index 0000000..cafa588 --- /dev/null +++ b/RTE/_Debug_CM7_DP/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Debug+CM7_DP' + * Target: 'Debug+CM7_DP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "CMSDK_CM7_DP.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.3 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Debug_CM7_SP/RTE_Components.h b/RTE/_Debug_CM7_SP/RTE_Components.h new file mode 100644 index 0000000..a271029 --- /dev/null +++ b/RTE/_Debug_CM7_SP/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Debug+CM7_SP' + * Target: 'Debug+CM7_SP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "CMSDK_CM7_SP.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.3 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Debug_CS300/RTE_Components.h b/RTE/_Debug_CS300/RTE_Components.h new file mode 100644 index 0000000..01503e3 --- /dev/null +++ b/RTE/_Debug_CS300/RTE_Components.h @@ -0,0 +1,42 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Debug+CS300' + * Target: 'Debug+CS300' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE300MPS3.h" + +/* ARM::CMSIS Driver:USART@1.0.0 */ +#define RTE_USART0 1 + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* ARM::Device:Native Driver:IO@1.1.0 */ +#define RTE_MPS3_IO 1 +/* ARM::Device:Native Driver:SysCounter@1.1.0 */ +#define RTE_SYSCOUNTER 1 +/* ARM::Device:Native Driver:Timeout@1.0.0 */ +#define RTE_TIMEOUT 1 + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Debug_CS310/RTE_Components.h b/RTE/_Debug_CS310/RTE_Components.h new file mode 100644 index 0000000..56d5429 --- /dev/null +++ b/RTE/_Debug_CS310/RTE_Components.h @@ -0,0 +1,42 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Debug+CS310' + * Target: 'Debug+CS310' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE310MPS3.h" + +/* ARM::CMSIS Driver:USART@1.1.0 */ +#define RTE_USART0 1 + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* ARM::Device:Native Driver:IO@1.0.1 */ +#define RTE_MPS3_IO 1 +/* ARM::Device:Native Driver:SysCounter@1.0.1 */ +#define RTE_SYSCOUNTER 1 +/* ARM::Device:Native Driver:Timeout@1.0.1 */ +#define RTE_TIMEOUT 1 + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Debug_CS315/RTE_Components.h b/RTE/_Debug_CS315/RTE_Components.h new file mode 100644 index 0000000..4909a79 --- /dev/null +++ b/RTE/_Debug_CS315/RTE_Components.h @@ -0,0 +1,42 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Debug+CS315' + * Target: 'Debug+CS315' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE315.h" + +/* ARM::CMSIS Driver:USART@1.1.0 */ +#define RTE_USART0 1 + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* ARM::Device:Native Driver:IO@1.0.1 */ +#define RTE_MPS3_IO 1 +/* ARM::Device:Native Driver:SysCounter@1.0.1 */ +#define RTE_SYSCOUNTER 1 +/* ARM::Device:Native Driver:Timeout@1.0.1 */ +#define RTE_TIMEOUT 1 + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Release_CM0/RTE_Components.h b/RTE/_Release_CM0/RTE_Components.h new file mode 100644 index 0000000..7d75075 --- /dev/null +++ b/RTE/_Release_CM0/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Release+CM0' + * Target: 'Release+CM0' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "CMSDK_CM0.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.3 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Release_CM0plus/RTE_Components.h b/RTE/_Release_CM0plus/RTE_Components.h new file mode 100644 index 0000000..3fe3dfe --- /dev/null +++ b/RTE/_Release_CM0plus/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Release+CM0plus' + * Target: 'Release+CM0plus' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "CMSDK_CM0plus.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.3 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Release_CM23/RTE_Components.h b/RTE/_Release_CM23/RTE_Components.h new file mode 100644 index 0000000..0363f75 --- /dev/null +++ b/RTE/_Release_CM23/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Release+CM23' + * Target: 'Release+CM23' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "IOTKit_CM23.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.0 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Release_CM3/RTE_Components.h b/RTE/_Release_CM3/RTE_Components.h new file mode 100644 index 0000000..29a9b3e --- /dev/null +++ b/RTE/_Release_CM3/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Release+CM3' + * Target: 'Release+CM3' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "CMSDK_CM3.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.3 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Release_CM33/RTE_Components.h b/RTE/_Release_CM33/RTE_Components.h new file mode 100644 index 0000000..f164800 --- /dev/null +++ b/RTE/_Release_CM33/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Release+CM33' + * Target: 'Release+CM33' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "IOTKit_CM33.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.0 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Release_CM33_FP/RTE_Components.h b/RTE/_Release_CM33_FP/RTE_Components.h new file mode 100644 index 0000000..68b09b7 --- /dev/null +++ b/RTE/_Release_CM33_FP/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Release+CM33_FP' + * Target: 'Release+CM33_FP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "IOTKit_CM33_FP.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.0 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Release_CM4/RTE_Components.h b/RTE/_Release_CM4/RTE_Components.h new file mode 100644 index 0000000..6e2fca3 --- /dev/null +++ b/RTE/_Release_CM4/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Release+CM4' + * Target: 'Release+CM4' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "CMSDK_CM4.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.3 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Release_CM4_FP/RTE_Components.h b/RTE/_Release_CM4_FP/RTE_Components.h new file mode 100644 index 0000000..de9a25e --- /dev/null +++ b/RTE/_Release_CM4_FP/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Release+CM4_FP' + * Target: 'Release+CM4_FP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "CMSDK_CM4_FP.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.3 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Release_CM7/RTE_Components.h b/RTE/_Release_CM7/RTE_Components.h new file mode 100644 index 0000000..1b162ee --- /dev/null +++ b/RTE/_Release_CM7/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Release+CM7' + * Target: 'Release+CM7' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "CMSDK_CM7.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.3 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Release_CM7_DP/RTE_Components.h b/RTE/_Release_CM7_DP/RTE_Components.h new file mode 100644 index 0000000..f5eaee1 --- /dev/null +++ b/RTE/_Release_CM7_DP/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Release+CM7_DP' + * Target: 'Release+CM7_DP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "CMSDK_CM7_DP.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.3 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Release_CM7_SP/RTE_Components.h b/RTE/_Release_CM7_SP/RTE_Components.h new file mode 100644 index 0000000..a341000 --- /dev/null +++ b/RTE/_Release_CM7_SP/RTE_Components.h @@ -0,0 +1,35 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Release+CM7_SP' + * Target: 'Release+CM7_SP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "CMSDK_CM7_SP.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil::CMSIS Driver:USART@1.0.3 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Release_CS300/RTE_Components.h b/RTE/_Release_CS300/RTE_Components.h new file mode 100644 index 0000000..d5cf7b7 --- /dev/null +++ b/RTE/_Release_CS300/RTE_Components.h @@ -0,0 +1,42 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Release+CS300' + * Target: 'Release+CS300' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE300MPS3.h" + +/* ARM::CMSIS Driver:USART@1.0.0 */ +#define RTE_USART0 1 + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* ARM::Device:Native Driver:IO@1.1.0 */ +#define RTE_MPS3_IO 1 +/* ARM::Device:Native Driver:SysCounter@1.1.0 */ +#define RTE_SYSCOUNTER 1 +/* ARM::Device:Native Driver:Timeout@1.0.0 */ +#define RTE_TIMEOUT 1 + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Release_CS310/RTE_Components.h b/RTE/_Release_CS310/RTE_Components.h new file mode 100644 index 0000000..7d7234f --- /dev/null +++ b/RTE/_Release_CS310/RTE_Components.h @@ -0,0 +1,42 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Release+CS310' + * Target: 'Release+CS310' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE310MPS3.h" + +/* ARM::CMSIS Driver:USART@1.1.0 */ +#define RTE_USART0 1 + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* ARM::Device:Native Driver:IO@1.0.1 */ +#define RTE_MPS3_IO 1 +/* ARM::Device:Native Driver:SysCounter@1.0.1 */ +#define RTE_SYSCOUNTER 1 +/* ARM::Device:Native Driver:Timeout@1.0.1 */ +#define RTE_TIMEOUT 1 + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Release_CS315/RTE_Components.h b/RTE/_Release_CS315/RTE_Components.h new file mode 100644 index 0000000..00fd60a --- /dev/null +++ b/RTE/_Release_CS315/RTE_Components.h @@ -0,0 +1,42 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.5.0 + * + * Project: 'Hello.Release+CS315' + * Target: 'Release+CS315' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE315.h" + +/* ARM::CMSIS Driver:USART@1.1.0 */ +#define RTE_USART0 1 + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ + #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ + #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ + #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* ARM::Device:Native Driver:IO@1.0.1 */ +#define RTE_MPS3_IO 1 +/* ARM::Device:Native Driver:SysCounter@1.0.1 */ +#define RTE_SYSCOUNTER 1 +/* ARM::Device:Native Driver:Timeout@1.0.1 */ +#define RTE_TIMEOUT 1 + + +#endif /* RTE_COMPONENTS_H */ From cd014dc0a48f77aead6007579880581d8485db63 Mon Sep 17 00:00:00 2001 From: "evangelos.ganotopoulos@arm.com" Date: Mon, 2 Sep 2024 11:58:52 +0200 Subject: [PATCH 2/4] Remove --update-rte to ensure support reproducible builds. Added GCC linker files located in RTE/Device directory. --- RTE/Device/IOTKit_CM23_VHT/gcc_arm.ld | 297 +++++++++++++++++ .../IOTKit_CM23_VHT/gcc_arm.ld.base@1.2.0 | 297 +++++++++++++++++ RTE/Device/IOTKit_CM33_FP_VHT/gcc_arm.ld | 297 +++++++++++++++++ .../IOTKit_CM33_FP_VHT/gcc_arm.ld.base@1.2.0 | 297 +++++++++++++++++ RTE/Device/IOTKit_CM33_VHT/gcc_arm.ld | 297 +++++++++++++++++ .../IOTKit_CM33_VHT/gcc_arm.ld.base@1.2.0 | 297 +++++++++++++++++ .../SSE-300-MPS3/gcc_linker_script.ld.src | 308 ++++++++++++++++++ .../SSE-310-MPS3_FVP/gcc_linker_script.ld.src | 308 ++++++++++++++++++ .../SSE-315-FVP/gcc_linker_script.ld.src | 308 ++++++++++++++++++ 9 files changed, 2706 insertions(+) create mode 100644 RTE/Device/IOTKit_CM23_VHT/gcc_arm.ld create mode 100644 RTE/Device/IOTKit_CM23_VHT/gcc_arm.ld.base@1.2.0 create mode 100644 RTE/Device/IOTKit_CM33_FP_VHT/gcc_arm.ld create mode 100644 RTE/Device/IOTKit_CM33_FP_VHT/gcc_arm.ld.base@1.2.0 create mode 100644 RTE/Device/IOTKit_CM33_VHT/gcc_arm.ld create mode 100644 RTE/Device/IOTKit_CM33_VHT/gcc_arm.ld.base@1.2.0 create mode 100644 RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src create mode 100644 RTE/Device/SSE-310-MPS3_FVP/gcc_linker_script.ld.src create mode 100644 RTE/Device/SSE-315-FVP/gcc_linker_script.ld.src diff --git a/RTE/Device/IOTKit_CM23_VHT/gcc_arm.ld b/RTE/Device/IOTKit_CM23_VHT/gcc_arm.ld new file mode 100644 index 0000000..74d717d --- /dev/null +++ b/RTE/Device/IOTKit_CM23_VHT/gcc_arm.ld @@ -0,0 +1,297 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x10000000; +__ROM_SIZE = 0x00200000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x38000000; +__RAM_SIZE = 0x00200000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +/* ARMv8-M stack sealing: + to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 + */ +__STACKSEAL_SIZE = 0; + + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __StackSeal (only if ARMv8-M stack sealing is used) + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* ARMv8-M stack sealing: + to use ARMv8-M stack sealing uncomment '.stackseal' section + */ +/* + .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : + { + . = ALIGN(8); + __StackSeal = .; + . = . + 8; + . = ALIGN(8); + } > RAM +*/ + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/IOTKit_CM23_VHT/gcc_arm.ld.base@1.2.0 b/RTE/Device/IOTKit_CM23_VHT/gcc_arm.ld.base@1.2.0 new file mode 100644 index 0000000..74d717d --- /dev/null +++ b/RTE/Device/IOTKit_CM23_VHT/gcc_arm.ld.base@1.2.0 @@ -0,0 +1,297 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x10000000; +__ROM_SIZE = 0x00200000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x38000000; +__RAM_SIZE = 0x00200000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +/* ARMv8-M stack sealing: + to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 + */ +__STACKSEAL_SIZE = 0; + + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __StackSeal (only if ARMv8-M stack sealing is used) + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* ARMv8-M stack sealing: + to use ARMv8-M stack sealing uncomment '.stackseal' section + */ +/* + .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : + { + . = ALIGN(8); + __StackSeal = .; + . = . + 8; + . = ALIGN(8); + } > RAM +*/ + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/IOTKit_CM33_FP_VHT/gcc_arm.ld b/RTE/Device/IOTKit_CM33_FP_VHT/gcc_arm.ld new file mode 100644 index 0000000..74d717d --- /dev/null +++ b/RTE/Device/IOTKit_CM33_FP_VHT/gcc_arm.ld @@ -0,0 +1,297 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x10000000; +__ROM_SIZE = 0x00200000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x38000000; +__RAM_SIZE = 0x00200000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +/* ARMv8-M stack sealing: + to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 + */ +__STACKSEAL_SIZE = 0; + + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __StackSeal (only if ARMv8-M stack sealing is used) + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* ARMv8-M stack sealing: + to use ARMv8-M stack sealing uncomment '.stackseal' section + */ +/* + .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : + { + . = ALIGN(8); + __StackSeal = .; + . = . + 8; + . = ALIGN(8); + } > RAM +*/ + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/IOTKit_CM33_FP_VHT/gcc_arm.ld.base@1.2.0 b/RTE/Device/IOTKit_CM33_FP_VHT/gcc_arm.ld.base@1.2.0 new file mode 100644 index 0000000..74d717d --- /dev/null +++ b/RTE/Device/IOTKit_CM33_FP_VHT/gcc_arm.ld.base@1.2.0 @@ -0,0 +1,297 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x10000000; +__ROM_SIZE = 0x00200000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x38000000; +__RAM_SIZE = 0x00200000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +/* ARMv8-M stack sealing: + to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 + */ +__STACKSEAL_SIZE = 0; + + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __StackSeal (only if ARMv8-M stack sealing is used) + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* ARMv8-M stack sealing: + to use ARMv8-M stack sealing uncomment '.stackseal' section + */ +/* + .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : + { + . = ALIGN(8); + __StackSeal = .; + . = . + 8; + . = ALIGN(8); + } > RAM +*/ + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/IOTKit_CM33_VHT/gcc_arm.ld b/RTE/Device/IOTKit_CM33_VHT/gcc_arm.ld new file mode 100644 index 0000000..74d717d --- /dev/null +++ b/RTE/Device/IOTKit_CM33_VHT/gcc_arm.ld @@ -0,0 +1,297 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x10000000; +__ROM_SIZE = 0x00200000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x38000000; +__RAM_SIZE = 0x00200000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +/* ARMv8-M stack sealing: + to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 + */ +__STACKSEAL_SIZE = 0; + + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __StackSeal (only if ARMv8-M stack sealing is used) + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* ARMv8-M stack sealing: + to use ARMv8-M stack sealing uncomment '.stackseal' section + */ +/* + .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : + { + . = ALIGN(8); + __StackSeal = .; + . = . + 8; + . = ALIGN(8); + } > RAM +*/ + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/IOTKit_CM33_VHT/gcc_arm.ld.base@1.2.0 b/RTE/Device/IOTKit_CM33_VHT/gcc_arm.ld.base@1.2.0 new file mode 100644 index 0000000..74d717d --- /dev/null +++ b/RTE/Device/IOTKit_CM33_VHT/gcc_arm.ld.base@1.2.0 @@ -0,0 +1,297 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x10000000; +__ROM_SIZE = 0x00200000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x38000000; +__RAM_SIZE = 0x00200000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +/* ARMv8-M stack sealing: + to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 + */ +__STACKSEAL_SIZE = 0; + + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __StackSeal (only if ARMv8-M stack sealing is used) + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* ARMv8-M stack sealing: + to use ARMv8-M stack sealing uncomment '.stackseal' section + */ +/* + .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : + { + . = ALIGN(8); + __StackSeal = .; + . = . + 8; + . = ALIGN(8); + } > RAM +*/ + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src b/RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src new file mode 100644 index 0000000..7cd986d --- /dev/null +++ b/RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + +/* ---------------------------------------------------------------------------- + Memory definition + *----------------------------------------------------------------------------*/ +MEMORY +{ + ROM0 (rx) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE +#if __ROM1_SIZE > 0 + ROM1 (rx) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE +#endif +#if __ROM2_SIZE > 0 + ROM2 (rx) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE +#endif +#if __ROM3_SIZE > 0 + ROM3 (rx) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE +#endif + + RAM0 (rwx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +#if __RAM1_SIZE > 0 + RAM1 (rwx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE +#endif +#if __RAM2_SIZE > 0 + RAM2 (rwx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE +#endif +#if __RAM3_SIZE > 0 + RAM3 (rwx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE +#endif +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext (deprecated) + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __noinit_start + * __noinit_end + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > ROM0 + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .gnu.sgstubs : + { + . = ALIGN(32); + } > ROM0 +#endif + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > ROM0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ROM0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (LOADADDR(.data)) + LONG (ADDR(.data)) + LONG (SIZEOF(.data) / 4) + + /* Add each additional data section here */ +/* + LONG (LOADADDR(.data2)) + LONG (ADDR(.data2)) + LONG (SIZEOF(.data2) / 4) +*/ + __copy_table_end__ = .; + } > ROM0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + +/* .bss initialization to zero is already done during C Run-Time Startup. + LONG (ADDR(.bss)) + LONG (SIZEOF(.bss) / 4) +*/ + + /* Add each additional bss section here */ +/* + LONG (ADDR(.bss2)) + LONG (SIZEOF(.bss2) / 4) +*/ + __zero_table_end__ = .; + } > ROM0 + + /* + * This __etext variable is kept for backward compatibility with older, + * ASM based startup files. + */ + PROVIDE(__etext = LOADADDR(.data)); + + .data : ALIGN(4) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM0 AT > ROM0 + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to assure proper + * initialization during startup. + */ +/* + .data2 : ALIGN(4) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM1 AT > ROM0 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM0 AT > RAM0 + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to assure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM1 AT > RAM1 +*/ + + /* This section contains data that is not initialized during load, + or during the application's initialization sequence. */ + .noinit (NOLOAD) : + { + . = ALIGN(4); + __noinit_start = .; + *(.noinit) + *(.noinit.*) + . = ALIGN(4); + __noinit_end = .; + } > RAM0 + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM0 + + .stack (ORIGIN(RAM0) + LENGTH(RAM0) - __STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM0 + PROVIDE(__stack = __StackTop); + +#if __STACKSEAL_SIZE > 0 + .stackseal (ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE) (NOLOAD) : + { + . = ALIGN(8); + __StackSeal = .; + . = . + 8; + . = ALIGN(8); + } > RAM0 +#endif + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/SSE-310-MPS3_FVP/gcc_linker_script.ld.src b/RTE/Device/SSE-310-MPS3_FVP/gcc_linker_script.ld.src new file mode 100644 index 0000000..7cd986d --- /dev/null +++ b/RTE/Device/SSE-310-MPS3_FVP/gcc_linker_script.ld.src @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + +/* ---------------------------------------------------------------------------- + Memory definition + *----------------------------------------------------------------------------*/ +MEMORY +{ + ROM0 (rx) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE +#if __ROM1_SIZE > 0 + ROM1 (rx) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE +#endif +#if __ROM2_SIZE > 0 + ROM2 (rx) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE +#endif +#if __ROM3_SIZE > 0 + ROM3 (rx) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE +#endif + + RAM0 (rwx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +#if __RAM1_SIZE > 0 + RAM1 (rwx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE +#endif +#if __RAM2_SIZE > 0 + RAM2 (rwx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE +#endif +#if __RAM3_SIZE > 0 + RAM3 (rwx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE +#endif +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext (deprecated) + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __noinit_start + * __noinit_end + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > ROM0 + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .gnu.sgstubs : + { + . = ALIGN(32); + } > ROM0 +#endif + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > ROM0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ROM0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (LOADADDR(.data)) + LONG (ADDR(.data)) + LONG (SIZEOF(.data) / 4) + + /* Add each additional data section here */ +/* + LONG (LOADADDR(.data2)) + LONG (ADDR(.data2)) + LONG (SIZEOF(.data2) / 4) +*/ + __copy_table_end__ = .; + } > ROM0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + +/* .bss initialization to zero is already done during C Run-Time Startup. + LONG (ADDR(.bss)) + LONG (SIZEOF(.bss) / 4) +*/ + + /* Add each additional bss section here */ +/* + LONG (ADDR(.bss2)) + LONG (SIZEOF(.bss2) / 4) +*/ + __zero_table_end__ = .; + } > ROM0 + + /* + * This __etext variable is kept for backward compatibility with older, + * ASM based startup files. + */ + PROVIDE(__etext = LOADADDR(.data)); + + .data : ALIGN(4) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM0 AT > ROM0 + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to assure proper + * initialization during startup. + */ +/* + .data2 : ALIGN(4) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM1 AT > ROM0 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM0 AT > RAM0 + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to assure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM1 AT > RAM1 +*/ + + /* This section contains data that is not initialized during load, + or during the application's initialization sequence. */ + .noinit (NOLOAD) : + { + . = ALIGN(4); + __noinit_start = .; + *(.noinit) + *(.noinit.*) + . = ALIGN(4); + __noinit_end = .; + } > RAM0 + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM0 + + .stack (ORIGIN(RAM0) + LENGTH(RAM0) - __STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM0 + PROVIDE(__stack = __StackTop); + +#if __STACKSEAL_SIZE > 0 + .stackseal (ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE) (NOLOAD) : + { + . = ALIGN(8); + __StackSeal = .; + . = . + 8; + . = ALIGN(8); + } > RAM0 +#endif + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/SSE-315-FVP/gcc_linker_script.ld.src b/RTE/Device/SSE-315-FVP/gcc_linker_script.ld.src new file mode 100644 index 0000000..7cd986d --- /dev/null +++ b/RTE/Device/SSE-315-FVP/gcc_linker_script.ld.src @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + +/* ---------------------------------------------------------------------------- + Memory definition + *----------------------------------------------------------------------------*/ +MEMORY +{ + ROM0 (rx) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE +#if __ROM1_SIZE > 0 + ROM1 (rx) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE +#endif +#if __ROM2_SIZE > 0 + ROM2 (rx) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE +#endif +#if __ROM3_SIZE > 0 + ROM3 (rx) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE +#endif + + RAM0 (rwx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +#if __RAM1_SIZE > 0 + RAM1 (rwx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE +#endif +#if __RAM2_SIZE > 0 + RAM2 (rwx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE +#endif +#if __RAM3_SIZE > 0 + RAM3 (rwx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE +#endif +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext (deprecated) + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __noinit_start + * __noinit_end + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > ROM0 + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .gnu.sgstubs : + { + . = ALIGN(32); + } > ROM0 +#endif + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > ROM0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ROM0 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (LOADADDR(.data)) + LONG (ADDR(.data)) + LONG (SIZEOF(.data) / 4) + + /* Add each additional data section here */ +/* + LONG (LOADADDR(.data2)) + LONG (ADDR(.data2)) + LONG (SIZEOF(.data2) / 4) +*/ + __copy_table_end__ = .; + } > ROM0 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + +/* .bss initialization to zero is already done during C Run-Time Startup. + LONG (ADDR(.bss)) + LONG (SIZEOF(.bss) / 4) +*/ + + /* Add each additional bss section here */ +/* + LONG (ADDR(.bss2)) + LONG (SIZEOF(.bss2) / 4) +*/ + __zero_table_end__ = .; + } > ROM0 + + /* + * This __etext variable is kept for backward compatibility with older, + * ASM based startup files. + */ + PROVIDE(__etext = LOADADDR(.data)); + + .data : ALIGN(4) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM0 AT > ROM0 + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to assure proper + * initialization during startup. + */ +/* + .data2 : ALIGN(4) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM1 AT > ROM0 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM0 AT > RAM0 + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to assure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM1 AT > RAM1 +*/ + + /* This section contains data that is not initialized during load, + or during the application's initialization sequence. */ + .noinit (NOLOAD) : + { + . = ALIGN(4); + __noinit_start = .; + *(.noinit) + *(.noinit.*) + . = ALIGN(4); + __noinit_end = .; + } > RAM0 + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM0 + + .stack (ORIGIN(RAM0) + LENGTH(RAM0) - __STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM0 + PROVIDE(__stack = __StackTop); + +#if __STACKSEAL_SIZE > 0 + .stackseal (ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE) (NOLOAD) : + { + . = ALIGN(8); + __StackSeal = .; + . = . + 8; + . = ALIGN(8); + } > RAM0 +#endif + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} From fb50942a1f09b0cc8a9f8f4be4a5bf39a4e7a67b Mon Sep 17 00:00:00 2001 From: "evangelos.ganotopoulos@arm.com" Date: Mon, 2 Sep 2024 12:18:45 +0200 Subject: [PATCH 3/4] Remove --update-rte to ensure support reproducible builds. Added GCC linker files located in RTE/Device directory. --- RTE/Device/CMSDK_CM7_DP_VHT/gcc_arm.ld | 277 ++++++++++++++++++ .../CMSDK_CM7_DP_VHT/gcc_arm.ld.base@1.1.0 | 277 ++++++++++++++++++ RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld | 277 ++++++++++++++++++ .../CMSDK_CM7_SP_VHT/gcc_arm.ld.base@1.1.0 | 277 ++++++++++++++++++ 4 files changed, 1108 insertions(+) create mode 100644 RTE/Device/CMSDK_CM7_DP_VHT/gcc_arm.ld create mode 100644 RTE/Device/CMSDK_CM7_DP_VHT/gcc_arm.ld.base@1.1.0 create mode 100644 RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld create mode 100644 RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld.base@1.1.0 diff --git a/RTE/Device/CMSDK_CM7_DP_VHT/gcc_arm.ld b/RTE/Device/CMSDK_CM7_DP_VHT/gcc_arm.ld new file mode 100644 index 0000000..aa2735f --- /dev/null +++ b/RTE/Device/CMSDK_CM7_DP_VHT/gcc_arm.ld @@ -0,0 +1,277 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/CMSDK_CM7_DP_VHT/gcc_arm.ld.base@1.1.0 b/RTE/Device/CMSDK_CM7_DP_VHT/gcc_arm.ld.base@1.1.0 new file mode 100644 index 0000000..aa2735f --- /dev/null +++ b/RTE/Device/CMSDK_CM7_DP_VHT/gcc_arm.ld.base@1.1.0 @@ -0,0 +1,277 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld b/RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld new file mode 100644 index 0000000..aa2735f --- /dev/null +++ b/RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld @@ -0,0 +1,277 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld.base@1.1.0 b/RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld.base@1.1.0 new file mode 100644 index 0000000..aa2735f --- /dev/null +++ b/RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld.base@1.1.0 @@ -0,0 +1,277 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + ******************************************************************************/ + +/* +; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* +; -------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ‘--section-start’ or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} From d35bd6b96cdd1c279d956d196add6c8731f426bb Mon Sep 17 00:00:00 2001 From: "evangelos.ganotopoulos@arm.com" Date: Mon, 2 Sep 2024 12:51:52 +0200 Subject: [PATCH 4/4] Updated commandline description to generate the application on a local computer. --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 53320ba..81aaadc 100644 --- a/README.md +++ b/README.md @@ -41,7 +41,7 @@ The workflow allows to build and test the application on different host systems, To generate the application for a specific target-type, build-type, and compiler execute the following command line: ```txt -> cbuild Hello.csolution.yml --update-rte --packs --context Hello.Debug+CS300 --toolchain AC6 --rebuild +> cbuild Hello.csolution.yml --packs --context Hello.Debug+CS300 --toolchain AC6 --rebuild ``` Parameters\Flags | Description