diff --git a/src/integration/rtl/caliptra_reg.h b/src/integration/rtl/caliptra_reg.h index b9e942264..a5117e8c8 100644 --- a/src/integration/rtl/caliptra_reg.h +++ b/src/integration/rtl/caliptra_reg.h @@ -5552,6 +5552,8 @@ #define SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_MASK (0x4) #define SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_LOW (3) #define SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_MASK (0x8) +#define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_LOW (4) +#define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (0x10) #define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN (0x300300e4) #define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN (0xe4) #define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0) diff --git a/src/integration/rtl/caliptra_reg_defines.svh b/src/integration/rtl/caliptra_reg_defines.svh index fa35a7f13..ca517ddab 100644 --- a/src/integration/rtl/caliptra_reg_defines.svh +++ b/src/integration/rtl/caliptra_reg_defines.svh @@ -5552,6 +5552,8 @@ `define SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_MASK (32'h4) `define SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_LOW (3) `define SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_MASK (32'h8) +`define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_LOW (4) +`define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (32'h10) `define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN (32'h300300e4) `define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN (32'he4) `define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0) diff --git a/src/soc_ifc/rtl/caliptra_top_reg.h b/src/soc_ifc/rtl/caliptra_top_reg.h index 553225858..89a1738ba 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg.h +++ b/src/soc_ifc/rtl/caliptra_top_reg.h @@ -308,6 +308,8 @@ #define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_I3C_EN_MASK (0x4) #define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_UART_EN_LOW (3) #define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_UART_EN_MASK (0x8) +#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_LOW (4) +#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (0x10) #define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN (0x300300e4) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN (0xe4) #define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0) @@ -542,4 +544,4 @@ #define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK (0xffff) -#endif +#endif \ No newline at end of file diff --git a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh index 9677a065e..8d537dd1a 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh +++ b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh @@ -308,6 +308,8 @@ `define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_I3C_EN_MASK (32'h4) `define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_UART_EN_LOW (3) `define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_UART_EN_MASK (32'h8) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_LOW (4) +`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (32'h10) `define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN (32'h300300e4) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN (32'he4) `define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0) @@ -542,4 +544,4 @@ `define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK (32'hffff) -`endif +`endif \ No newline at end of file diff --git a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl index e4a50e083..ff8579fc3 100644 --- a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl +++ b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl @@ -326,6 +326,7 @@ reg { field {sw=r; hw=w;} QSPI_en; field {sw=r; hw=w;} I3C_en; field {sw=r; hw=w;} UART_en; + field {sw=r; hw=w;} LMS_acc_en; } CPTRA_HW_CONFIG; //Timer1 diff --git a/src/soc_ifc/rtl/soc_ifc_reg.sv b/src/soc_ifc/rtl/soc_ifc_reg.sv index c5e84234e..ed07103ad 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg.sv @@ -5493,7 +5493,8 @@ module soc_ifc_reg ( assign readback_array[56][1:1] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.QSPI_en.next : '0; assign readback_array[56][2:2] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.I3C_en.next : '0; assign readback_array[56][3:3] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.UART_en.next : '0; - assign readback_array[56][31:4] = '0; + assign readback_array[56][4:4] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.LMS_acc_en.next : '0; + assign readback_array[56][31:5] = '0; assign readback_array[57][0:0] = (decoded_reg_strb.CPTRA_WDT_TIMER1_EN && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value : '0; assign readback_array[57][31:1] = '0; assign readback_array[58][0:0] = (decoded_reg_strb.CPTRA_WDT_TIMER1_CTRL && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value : '0; diff --git a/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh b/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh index 0b835415e..6fc4600d8 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh +++ b/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh @@ -633,13 +633,15 @@ input bit [1-1:0] iTRNG_en, input bit [1-1:0] QSPI_en, input bit [1-1:0] I3C_en, - input bit [1-1:0] UART_en + input bit [1-1:0] UART_en, + input bit [1-1:0] LMS_acc_en ); option.per_instance = 1; iTRNG_en_cp : coverpoint iTRNG_en; QSPI_en_cp : coverpoint QSPI_en; I3C_en_cp : coverpoint I3C_en; UART_en_cp : coverpoint UART_en; + LMS_acc_en_cp : coverpoint LMS_acc_en; endgroup diff --git a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv index 960293743..2f989c71d 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv @@ -185,11 +185,16 @@ package soc_ifc_reg_pkg; logic next; } soc_ifc_reg__CPTRA_HW_CONFIG__UART_en__in_t; + typedef struct packed{ + logic next; + } soc_ifc_reg__CPTRA_HW_CONFIG__LMS_acc_en__in_t; + typedef struct packed{ soc_ifc_reg__CPTRA_HW_CONFIG__iTRNG_en__in_t iTRNG_en; soc_ifc_reg__CPTRA_HW_CONFIG__QSPI_en__in_t QSPI_en; soc_ifc_reg__CPTRA_HW_CONFIG__I3C_en__in_t I3C_en; soc_ifc_reg__CPTRA_HW_CONFIG__UART_en__in_t UART_en; + soc_ifc_reg__CPTRA_HW_CONFIG__LMS_acc_en__in_t LMS_acc_en; } soc_ifc_reg__CPTRA_HW_CONFIG__in_t; typedef struct packed{ diff --git a/src/soc_ifc/rtl/soc_ifc_reg_sample.svh b/src/soc_ifc/rtl/soc_ifc_reg_sample.svh index e677131de..7dd9fc4b9 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_sample.svh +++ b/src/soc_ifc/rtl/soc_ifc_reg_sample.svh @@ -735,9 +735,10 @@ foreach(QSPI_en_bit_cg[bt]) this.QSPI_en_bit_cg[bt].sample(data[1 + bt]); foreach(I3C_en_bit_cg[bt]) this.I3C_en_bit_cg[bt].sample(data[2 + bt]); foreach(UART_en_bit_cg[bt]) this.UART_en_bit_cg[bt].sample(data[3 + bt]); + foreach(LMS_acc_en_bit_cg[bt]) this.LMS_acc_en_bit_cg[bt].sample(data[4 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[0:0]/*iTRNG_en*/ , data[1:1]/*QSPI_en*/ , data[2:2]/*I3C_en*/ , data[3:3]/*UART_en*/ ); + this.fld_cg.sample( data[0:0]/*iTRNG_en*/ , data[1:1]/*QSPI_en*/ , data[2:2]/*I3C_en*/ , data[3:3]/*UART_en*/ , data[4:4]/*LMS_acc_en*/ ); end endfunction @@ -747,9 +748,10 @@ foreach(QSPI_en_bit_cg[bt]) this.QSPI_en_bit_cg[bt].sample(QSPI_en.get_mirrored_value() >> bt); foreach(I3C_en_bit_cg[bt]) this.I3C_en_bit_cg[bt].sample(I3C_en.get_mirrored_value() >> bt); foreach(UART_en_bit_cg[bt]) this.UART_en_bit_cg[bt].sample(UART_en.get_mirrored_value() >> bt); + foreach(LMS_acc_en_bit_cg[bt]) this.LMS_acc_en_bit_cg[bt].sample(LMS_acc_en.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( iTRNG_en.get_mirrored_value() , QSPI_en.get_mirrored_value() , I3C_en.get_mirrored_value() , UART_en.get_mirrored_value() ); + this.fld_cg.sample( iTRNG_en.get_mirrored_value() , QSPI_en.get_mirrored_value() , I3C_en.get_mirrored_value() , UART_en.get_mirrored_value() , LMS_acc_en.get_mirrored_value() ); end endfunction diff --git a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv index 249f71bb5..eb8b4ddd8 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv @@ -904,11 +904,13 @@ package soc_ifc_reg_uvm; soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg QSPI_en_bit_cg[1]; soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg I3C_en_bit_cg[1]; soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg UART_en_bit_cg[1]; + soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg LMS_acc_en_bit_cg[1]; soc_ifc_reg__CPTRA_HW_CONFIG_fld_cg fld_cg; rand uvm_reg_field iTRNG_en; rand uvm_reg_field QSPI_en; rand uvm_reg_field I3C_en; rand uvm_reg_field UART_en; + rand uvm_reg_field LMS_acc_en; function new(string name = "soc_ifc_reg__CPTRA_HW_CONFIG"); super.new(name, 32, build_coverage(UVM_CVR_ALL)); @@ -928,11 +930,14 @@ package soc_ifc_reg_uvm; this.I3C_en.configure(this, 1, 2, "RO", 1, 'h0, 0, 1, 0); this.UART_en = new("UART_en"); this.UART_en.configure(this, 1, 3, "RO", 1, 'h0, 0, 1, 0); + this.LMS_acc_en = new("LMS_acc_en"); + this.LMS_acc_en.configure(this, 1, 4, "RO", 1, 'h0, 0, 1, 0); if (has_coverage(UVM_CVR_REG_BITS)) begin foreach(iTRNG_en_bit_cg[bt]) iTRNG_en_bit_cg[bt] = new(); foreach(QSPI_en_bit_cg[bt]) QSPI_en_bit_cg[bt] = new(); foreach(I3C_en_bit_cg[bt]) I3C_en_bit_cg[bt] = new(); foreach(UART_en_bit_cg[bt]) UART_en_bit_cg[bt] = new(); + foreach(LMS_acc_en_bit_cg[bt]) LMS_acc_en_bit_cg[bt] = new(); end if (has_coverage(UVM_CVR_FIELD_VALS)) fld_cg = new(); diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv index a5d862690..bc13aad07 100644 --- a/src/soc_ifc/rtl/soc_ifc_top.sv +++ b/src/soc_ifc/rtl/soc_ifc_top.sv @@ -412,6 +412,8 @@ always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.UART_en.next = 1'b1; `else always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.UART_en.next = 1'b0; `endif +// Hardcoded because all future revs will have LMS accelerator available +always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.LMS_acc_en.next = 1'b1; //SOC Stepping ID update always_comb begin