diff --git a/src/datavault/rtl/dv_reg.sv b/src/datavault/rtl/dv_reg.sv index ded8e5d15..7e92f0807 100644 --- a/src/datavault/rtl/dv_reg.sv +++ b/src/datavault/rtl/dv_reg.sv @@ -58,7 +58,9 @@ module dv_reg ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -82,35 +84,35 @@ module dv_reg ( always_comb begin for(int i0=0; i0<10; i0++) begin - decoded_reg_strb.StickyDataVaultCtrl[i0] = cpuif_req_masked & (cpuif_addr == 'h0 + i0*'h4); + decoded_reg_strb.StickyDataVaultCtrl[i0] = cpuif_req_masked & (cpuif_addr == 11'h0 + i0*11'h4); end for(int i0=0; i0<10; i0++) begin for(int i1=0; i1<12; i1++) begin - decoded_reg_strb.STICKY_DATA_VAULT_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 'h28 + i0*'h30 + i1*'h4); + decoded_reg_strb.STICKY_DATA_VAULT_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 11'h28 + i0*11'h30 + i1*11'h4); end end for(int i0=0; i0<10; i0++) begin - decoded_reg_strb.DataVaultCtrl[i0] = cpuif_req_masked & (cpuif_addr == 'h208 + i0*'h4); + decoded_reg_strb.DataVaultCtrl[i0] = cpuif_req_masked & (cpuif_addr == 11'h208 + i0*11'h4); end for(int i0=0; i0<10; i0++) begin for(int i1=0; i1<12; i1++) begin - decoded_reg_strb.DATA_VAULT_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 'h230 + i0*'h30 + i1*'h4); + decoded_reg_strb.DATA_VAULT_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 11'h230 + i0*11'h30 + i1*11'h4); end end for(int i0=0; i0<10; i0++) begin - decoded_reg_strb.LockableScratchRegCtrl[i0] = cpuif_req_masked & (cpuif_addr == 'h410 + i0*'h4); + decoded_reg_strb.LockableScratchRegCtrl[i0] = cpuif_req_masked & (cpuif_addr == 11'h410 + i0*11'h4); end for(int i0=0; i0<10; i0++) begin - decoded_reg_strb.LockableScratchReg[i0] = cpuif_req_masked & (cpuif_addr == 'h438 + i0*'h4); + decoded_reg_strb.LockableScratchReg[i0] = cpuif_req_masked & (cpuif_addr == 11'h438 + i0*11'h4); end for(int i0=0; i0<8; i0++) begin - decoded_reg_strb.NonStickyGenericScratchReg[i0] = cpuif_req_masked & (cpuif_addr == 'h460 + i0*'h4); + decoded_reg_strb.NonStickyGenericScratchReg[i0] = cpuif_req_masked & (cpuif_addr == 11'h460 + i0*11'h4); end for(int i0=0; i0<8; i0++) begin - decoded_reg_strb.StickyLockableScratchRegCtrl[i0] = cpuif_req_masked & (cpuif_addr == 'h480 + i0*'h4); + decoded_reg_strb.StickyLockableScratchRegCtrl[i0] = cpuif_req_masked & (cpuif_addr == 11'h480 + i0*11'h4); end for(int i0=0; i0<8; i0++) begin - decoded_reg_strb.StickyLockableScratchReg[i0] = cpuif_req_masked & (cpuif_addr == 'h4a0 + i0*'h4); + decoded_reg_strb.StickyLockableScratchReg[i0] = cpuif_req_masked & (cpuif_addr == 11'h4a0 + i0*11'h4); end end @@ -120,10 +122,6 @@ module dv_reg ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -237,8 +235,10 @@ module dv_reg ( for(genvar i0=0; i0<10; i0++) begin // Field: dv_reg.StickyDataVaultCtrl[].lock_entry always_comb begin - automatic logic [0:0] next_c = field_storage.StickyDataVaultCtrl[i0].lock_entry.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.StickyDataVaultCtrl[i0].lock_entry.value; + load_next_c = '0; if(decoded_reg_strb.StickyDataVaultCtrl[i0] && decoded_req_is_wr && !(hwif_in.StickyDataVaultCtrl[i0].lock_entry.swwel)) begin // SW write next_c = (field_storage.StickyDataVaultCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -248,7 +248,7 @@ module dv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.StickyDataVaultCtrl[i0].lock_entry.value <= 'h0; + field_storage.StickyDataVaultCtrl[i0].lock_entry.value <= 1'h0; end else if(field_combo.StickyDataVaultCtrl[i0].lock_entry.load_next) begin field_storage.StickyDataVaultCtrl[i0].lock_entry.value <= field_combo.StickyDataVaultCtrl[i0].lock_entry.next; end @@ -259,8 +259,10 @@ module dv_reg ( for(genvar i1=0; i1<12; i1++) begin // Field: dv_reg.STICKY_DATA_VAULT_ENTRY[][].data always_comb begin - automatic logic [31:0] next_c = field_storage.STICKY_DATA_VAULT_ENTRY[i0][i1].data.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.STICKY_DATA_VAULT_ENTRY[i0][i1].data.value; + load_next_c = '0; if(decoded_reg_strb.STICKY_DATA_VAULT_ENTRY[i0][i1] && decoded_req_is_wr && !(hwif_in.STICKY_DATA_VAULT_ENTRY[i0][i1].data.swwel)) begin // SW write next_c = (field_storage.STICKY_DATA_VAULT_ENTRY[i0][i1].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -270,7 +272,7 @@ module dv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.STICKY_DATA_VAULT_ENTRY[i0][i1].data.value <= 'h0; + field_storage.STICKY_DATA_VAULT_ENTRY[i0][i1].data.value <= 32'h0; end else if(field_combo.STICKY_DATA_VAULT_ENTRY[i0][i1].data.load_next) begin field_storage.STICKY_DATA_VAULT_ENTRY[i0][i1].data.value <= field_combo.STICKY_DATA_VAULT_ENTRY[i0][i1].data.next; end @@ -280,8 +282,10 @@ module dv_reg ( for(genvar i0=0; i0<10; i0++) begin // Field: dv_reg.DataVaultCtrl[].lock_entry always_comb begin - automatic logic [0:0] next_c = field_storage.DataVaultCtrl[i0].lock_entry.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DataVaultCtrl[i0].lock_entry.value; + load_next_c = '0; if(decoded_reg_strb.DataVaultCtrl[i0] && decoded_req_is_wr && !(hwif_in.DataVaultCtrl[i0].lock_entry.swwel)) begin // SW write next_c = (field_storage.DataVaultCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -291,7 +295,7 @@ module dv_reg ( end always_ff @(posedge clk or negedge hwif_in.core_only_rst_b) begin if(~hwif_in.core_only_rst_b) begin - field_storage.DataVaultCtrl[i0].lock_entry.value <= 'h0; + field_storage.DataVaultCtrl[i0].lock_entry.value <= 1'h0; end else if(field_combo.DataVaultCtrl[i0].lock_entry.load_next) begin field_storage.DataVaultCtrl[i0].lock_entry.value <= field_combo.DataVaultCtrl[i0].lock_entry.next; end @@ -302,8 +306,10 @@ module dv_reg ( for(genvar i1=0; i1<12; i1++) begin // Field: dv_reg.DATA_VAULT_ENTRY[][].data always_comb begin - automatic logic [31:0] next_c = field_storage.DATA_VAULT_ENTRY[i0][i1].data.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DATA_VAULT_ENTRY[i0][i1].data.value; + load_next_c = '0; if(decoded_reg_strb.DATA_VAULT_ENTRY[i0][i1] && decoded_req_is_wr && !(hwif_in.DATA_VAULT_ENTRY[i0][i1].data.swwel)) begin // SW write next_c = (field_storage.DATA_VAULT_ENTRY[i0][i1].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -313,7 +319,7 @@ module dv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.DATA_VAULT_ENTRY[i0][i1].data.value <= 'h0; + field_storage.DATA_VAULT_ENTRY[i0][i1].data.value <= 32'h0; end else if(field_combo.DATA_VAULT_ENTRY[i0][i1].data.load_next) begin field_storage.DATA_VAULT_ENTRY[i0][i1].data.value <= field_combo.DATA_VAULT_ENTRY[i0][i1].data.next; end @@ -323,8 +329,10 @@ module dv_reg ( for(genvar i0=0; i0<10; i0++) begin // Field: dv_reg.LockableScratchRegCtrl[].lock_entry always_comb begin - automatic logic [0:0] next_c = field_storage.LockableScratchRegCtrl[i0].lock_entry.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.LockableScratchRegCtrl[i0].lock_entry.value; + load_next_c = '0; if(decoded_reg_strb.LockableScratchRegCtrl[i0] && decoded_req_is_wr && !(hwif_in.LockableScratchRegCtrl[i0].lock_entry.swwel)) begin // SW write next_c = (field_storage.LockableScratchRegCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -334,7 +342,7 @@ module dv_reg ( end always_ff @(posedge clk or negedge hwif_in.core_only_rst_b) begin if(~hwif_in.core_only_rst_b) begin - field_storage.LockableScratchRegCtrl[i0].lock_entry.value <= 'h0; + field_storage.LockableScratchRegCtrl[i0].lock_entry.value <= 1'h0; end else if(field_combo.LockableScratchRegCtrl[i0].lock_entry.load_next) begin field_storage.LockableScratchRegCtrl[i0].lock_entry.value <= field_combo.LockableScratchRegCtrl[i0].lock_entry.next; end @@ -344,8 +352,10 @@ module dv_reg ( for(genvar i0=0; i0<10; i0++) begin // Field: dv_reg.LockableScratchReg[].data always_comb begin - automatic logic [31:0] next_c = field_storage.LockableScratchReg[i0].data.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.LockableScratchReg[i0].data.value; + load_next_c = '0; if(decoded_reg_strb.LockableScratchReg[i0] && decoded_req_is_wr && !(hwif_in.LockableScratchReg[i0].data.swwel)) begin // SW write next_c = (field_storage.LockableScratchReg[i0].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -355,7 +365,7 @@ module dv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.LockableScratchReg[i0].data.value <= 'h0; + field_storage.LockableScratchReg[i0].data.value <= 32'h0; end else if(field_combo.LockableScratchReg[i0].data.load_next) begin field_storage.LockableScratchReg[i0].data.value <= field_combo.LockableScratchReg[i0].data.next; end @@ -364,8 +374,10 @@ module dv_reg ( for(genvar i0=0; i0<8; i0++) begin // Field: dv_reg.NonStickyGenericScratchReg[].data always_comb begin - automatic logic [31:0] next_c = field_storage.NonStickyGenericScratchReg[i0].data.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.NonStickyGenericScratchReg[i0].data.value; + load_next_c = '0; if(decoded_reg_strb.NonStickyGenericScratchReg[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.NonStickyGenericScratchReg[i0].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -375,7 +387,7 @@ module dv_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.NonStickyGenericScratchReg[i0].data.value <= 'h0; + field_storage.NonStickyGenericScratchReg[i0].data.value <= 32'h0; end else if(field_combo.NonStickyGenericScratchReg[i0].data.load_next) begin field_storage.NonStickyGenericScratchReg[i0].data.value <= field_combo.NonStickyGenericScratchReg[i0].data.next; end @@ -384,8 +396,10 @@ module dv_reg ( for(genvar i0=0; i0<8; i0++) begin // Field: dv_reg.StickyLockableScratchRegCtrl[].lock_entry always_comb begin - automatic logic [0:0] next_c = field_storage.StickyLockableScratchRegCtrl[i0].lock_entry.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.StickyLockableScratchRegCtrl[i0].lock_entry.value; + load_next_c = '0; if(decoded_reg_strb.StickyLockableScratchRegCtrl[i0] && decoded_req_is_wr && !(hwif_in.StickyLockableScratchRegCtrl[i0].lock_entry.swwel)) begin // SW write next_c = (field_storage.StickyLockableScratchRegCtrl[i0].lock_entry.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -395,7 +409,7 @@ module dv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.StickyLockableScratchRegCtrl[i0].lock_entry.value <= 'h0; + field_storage.StickyLockableScratchRegCtrl[i0].lock_entry.value <= 1'h0; end else if(field_combo.StickyLockableScratchRegCtrl[i0].lock_entry.load_next) begin field_storage.StickyLockableScratchRegCtrl[i0].lock_entry.value <= field_combo.StickyLockableScratchRegCtrl[i0].lock_entry.next; end @@ -405,8 +419,10 @@ module dv_reg ( for(genvar i0=0; i0<8; i0++) begin // Field: dv_reg.StickyLockableScratchReg[].data always_comb begin - automatic logic [31:0] next_c = field_storage.StickyLockableScratchReg[i0].data.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.StickyLockableScratchReg[i0].data.value; + load_next_c = '0; if(decoded_reg_strb.StickyLockableScratchReg[i0] && decoded_req_is_wr && !(hwif_in.StickyLockableScratchReg[i0].data.swwel)) begin // SW write next_c = (field_storage.StickyLockableScratchReg[i0].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -416,19 +432,28 @@ module dv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.StickyLockableScratchReg[i0].data.value <= 'h0; + field_storage.StickyLockableScratchReg[i0].data.value <= 32'h0; end else if(field_combo.StickyLockableScratchReg[i0].data.load_next) begin field_storage.StickyLockableScratchReg[i0].data.value <= field_combo.StickyLockableScratchReg[i0].data.next; end end end + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [304-1:0][31:0] readback_array; for(genvar i0=0; i0<10; i0++) begin @@ -480,4 +505,4 @@ module dv_reg ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; -endmodule \ No newline at end of file +endmodule diff --git a/src/datavault/rtl/dv_reg_pkg.sv b/src/datavault/rtl/dv_reg_pkg.sv index ee3801467..10a491e9f 100644 --- a/src/datavault/rtl/dv_reg_pkg.sv +++ b/src/datavault/rtl/dv_reg_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package dv_reg_pkg; + + localparam DV_REG_DATA_WIDTH = 32; + localparam DV_REG_MIN_ADDR_WIDTH = 11; + typedef struct packed{ logic swwel; } dv_reg__StickyDataVaultCtrl__lock_entry__in_t; diff --git a/src/doe/rtl/doe_reg.sv b/src/doe/rtl/doe_reg.sv index 2f567cc7f..85db9fee7 100644 --- a/src/doe/rtl/doe_reg.sv +++ b/src/doe/rtl/doe_reg.sv @@ -58,7 +58,9 @@ module doe_reg ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -97,29 +99,29 @@ module doe_reg ( always_comb begin for(int i0=0; i0<4; i0++) begin - decoded_reg_strb.DOE_IV[i0] = cpuif_req_masked & (cpuif_addr == 'h0 + i0*'h4); - end - decoded_reg_strb.DOE_CTRL = cpuif_req_masked & (cpuif_addr == 'h10); - decoded_reg_strb.DOE_STATUS = cpuif_req_masked & (cpuif_addr == 'h14); - decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h800); - decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h804); - decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h808); - decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h80c); - decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h810); - decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h814); - decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h818); - decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h81c); - decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h820); - decoded_reg_strb.intr_block_rf.error0_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h900); - decoded_reg_strb.intr_block_rf.error1_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h904); - decoded_reg_strb.intr_block_rf.error2_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h908); - decoded_reg_strb.intr_block_rf.error3_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h90c); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h980); - decoded_reg_strb.intr_block_rf.error0_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha00); - decoded_reg_strb.intr_block_rf.error1_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha04); - decoded_reg_strb.intr_block_rf.error2_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha08); - decoded_reg_strb.intr_block_rf.error3_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha0c); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha10); + decoded_reg_strb.DOE_IV[i0] = cpuif_req_masked & (cpuif_addr == 12'h0 + i0*12'h4); + end + decoded_reg_strb.DOE_CTRL = cpuif_req_masked & (cpuif_addr == 12'h10); + decoded_reg_strb.DOE_STATUS = cpuif_req_masked & (cpuif_addr == 12'h14); + decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h800); + decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h804); + decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h808); + decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h80c); + decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h810); + decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h814); + decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h818); + decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h81c); + decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h820); + decoded_reg_strb.intr_block_rf.error0_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h900); + decoded_reg_strb.intr_block_rf.error1_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h904); + decoded_reg_strb.intr_block_rf.error2_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h908); + decoded_reg_strb.intr_block_rf.error3_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h90c); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h980); + decoded_reg_strb.intr_block_rf.error0_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha00); + decoded_reg_strb.intr_block_rf.error1_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha04); + decoded_reg_strb.intr_block_rf.error2_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha08); + decoded_reg_strb.intr_block_rf.error3_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha0c); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha10); end // Pass down signals to next stage @@ -128,10 +130,6 @@ module doe_reg ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -503,8 +501,10 @@ module doe_reg ( for(genvar i0=0; i0<4; i0++) begin // Field: doe_reg.DOE_IV[].IV always_comb begin - automatic logic [31:0] next_c = field_storage.DOE_IV[i0].IV.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DOE_IV[i0].IV.value; + load_next_c = '0; if(decoded_reg_strb.DOE_IV[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.DOE_IV[i0].IV.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -517,7 +517,7 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.DOE_IV[i0].IV.value <= 'h0; + field_storage.DOE_IV[i0].IV.value <= 32'h0; end else if(field_combo.DOE_IV[i0].IV.load_next) begin field_storage.DOE_IV[i0].IV.value <= field_combo.DOE_IV[i0].IV.next; end @@ -527,8 +527,10 @@ module doe_reg ( end // Field: doe_reg.DOE_CTRL.CMD always_comb begin - automatic logic [1:0] next_c = field_storage.DOE_CTRL.CMD.value; - automatic logic load_next_c = '0; + automatic logic [1:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DOE_CTRL.CMD.value; + load_next_c = '0; if(decoded_reg_strb.DOE_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.DOE_CTRL.CMD.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]); load_next_c = '1; @@ -541,7 +543,7 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.DOE_CTRL.CMD.value <= 'h0; + field_storage.DOE_CTRL.CMD.value <= 2'h0; end else if(field_combo.DOE_CTRL.CMD.load_next) begin field_storage.DOE_CTRL.CMD.value <= field_combo.DOE_CTRL.CMD.next; end @@ -550,8 +552,10 @@ module doe_reg ( assign hwif_out.DOE_CTRL.CMD.swmod = decoded_reg_strb.DOE_CTRL && decoded_req_is_wr; // Field: doe_reg.DOE_CTRL.DEST always_comb begin - automatic logic [4:0] next_c = field_storage.DOE_CTRL.DEST.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DOE_CTRL.DEST.value; + load_next_c = '0; if(decoded_reg_strb.DOE_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.DOE_CTRL.DEST.value & ~decoded_wr_biten[6:2]) | (decoded_wr_data[6:2] & decoded_wr_biten[6:2]); load_next_c = '1; @@ -561,7 +565,7 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.DOE_CTRL.DEST.value <= 'h0; + field_storage.DOE_CTRL.DEST.value <= 5'h0; end else if(field_combo.DOE_CTRL.DEST.load_next) begin field_storage.DOE_CTRL.DEST.value <= field_combo.DOE_CTRL.DEST.next; end @@ -569,8 +573,10 @@ module doe_reg ( assign hwif_out.DOE_CTRL.DEST.value = field_storage.DOE_CTRL.DEST.value; // Field: doe_reg.DOE_STATUS.READY always_comb begin - automatic logic [0:0] next_c = field_storage.DOE_STATUS.READY.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DOE_STATUS.READY.value; + load_next_c = '0; if(hwif_in.DOE_STATUS.READY.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -583,15 +589,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.DOE_STATUS.READY.value <= 'h0; + field_storage.DOE_STATUS.READY.value <= 1'h0; end else if(field_combo.DOE_STATUS.READY.load_next) begin field_storage.DOE_STATUS.READY.value <= field_combo.DOE_STATUS.READY.next; end end // Field: doe_reg.DOE_STATUS.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.DOE_STATUS.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DOE_STATUS.VALID.value; + load_next_c = '0; if(hwif_in.DOE_STATUS.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -604,15 +612,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.DOE_STATUS.VALID.value <= 'h0; + field_storage.DOE_STATUS.VALID.value <= 1'h0; end else if(field_combo.DOE_STATUS.VALID.load_next) begin field_storage.DOE_STATUS.VALID.value <= field_combo.DOE_STATUS.VALID.next; end end // Field: doe_reg.DOE_STATUS.DEOBF_SECRETS_CLEARED always_comb begin - automatic logic [0:0] next_c = field_storage.DOE_STATUS.DEOBF_SECRETS_CLEARED.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DOE_STATUS.DEOBF_SECRETS_CLEARED.value; + load_next_c = '0; if(hwif_in.DOE_STATUS.DEOBF_SECRETS_CLEARED.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -622,15 +632,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.DOE_STATUS.DEOBF_SECRETS_CLEARED.value <= 'h0; + field_storage.DOE_STATUS.DEOBF_SECRETS_CLEARED.value <= 1'h0; end else if(field_combo.DOE_STATUS.DEOBF_SECRETS_CLEARED.load_next) begin field_storage.DOE_STATUS.DEOBF_SECRETS_CLEARED.value <= field_combo.DOE_STATUS.DEOBF_SECRETS_CLEARED.next; end end // Field: doe_reg.intr_block_rf.global_intr_en_r.error_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.error_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -640,15 +652,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.error_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.error_en.value <= field_combo.intr_block_rf.global_intr_en_r.error_en.next; end end // Field: doe_reg.intr_block_rf.global_intr_en_r.notif_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.notif_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -658,15 +672,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.notif_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= field_combo.intr_block_rf.global_intr_en_r.notif_en.next; end end // Field: doe_reg.intr_block_rf.error_intr_en_r.error0_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error0_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -676,15 +692,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error0_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= field_combo.intr_block_rf.error_intr_en_r.error0_en.next; end end // Field: doe_reg.intr_block_rf.error_intr_en_r.error1_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error1_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -694,15 +712,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error1_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= field_combo.intr_block_rf.error_intr_en_r.error1_en.next; end end // Field: doe_reg.intr_block_rf.error_intr_en_r.error2_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error2_en.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -712,15 +732,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error2_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= field_combo.intr_block_rf.error_intr_en_r.error2_en.next; end end // Field: doe_reg.intr_block_rf.error_intr_en_r.error3_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error3_en.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -730,15 +752,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error3_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= field_combo.intr_block_rf.error_intr_en_r.error3_en.next; end end // Field: doe_reg.intr_block_rf.notif_intr_en_r.notif_cmd_done_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -748,25 +772,27 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.next; end end // Field: doe_reg.intr_block_rf.error_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.error_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.error_global_intr_r.agg_sts.next; end @@ -775,18 +801,20 @@ module doe_reg ( |(field_storage.intr_block_rf.error_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.error_en.value); // Field: doe_reg.intr_block_rf.notif_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next; end @@ -795,9 +823,11 @@ module doe_reg ( |(field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.notif_en.value); // Field: doe_reg.intr_block_rf.error_internal_intr_r.error0_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error0_sts.hwset) begin // HW Set @@ -812,16 +842,18 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error0_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error0_sts.next; end end // Field: doe_reg.intr_block_rf.error_internal_intr_r.error1_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error1_sts.hwset) begin // HW Set @@ -836,16 +868,18 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error1_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error1_sts.next; end end // Field: doe_reg.intr_block_rf.error_internal_intr_r.error2_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error2_sts.hwset) begin // HW Set @@ -860,16 +894,18 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error2_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error2_sts.next; end end // Field: doe_reg.intr_block_rf.error_internal_intr_r.error3_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error3_sts.hwset) begin // HW Set @@ -884,7 +920,7 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error3_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error3_sts.next; end @@ -896,9 +932,11 @@ module doe_reg ( || |(field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value & field_storage.intr_block_rf.error_intr_en_r.error3_en.value); // Field: doe_reg.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.hwset) begin // HW Set @@ -913,7 +951,7 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.next; end @@ -922,12 +960,14 @@ module doe_reg ( |(field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value); // Field: doe_reg.intr_block_rf.error_intr_trig_r.error0_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -936,19 +976,21 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error0_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error0_trig.next; end end // Field: doe_reg.intr_block_rf.error_intr_trig_r.error1_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -957,19 +999,21 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error1_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error1_trig.next; end end // Field: doe_reg.intr_block_rf.error_intr_trig_r.error2_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -978,19 +1022,21 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error2_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error2_trig.next; end end // Field: doe_reg.intr_block_rf.error_intr_trig_r.error3_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -999,19 +1045,21 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error3_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error3_trig.next; end end // Field: doe_reg.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1020,31 +1068,33 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.next; end end // Field: doe_reg.intr_block_rf.error0_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error0_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error0_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error0_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error0_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error0_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error0_intr_count_r.cnt.next = next_c; @@ -1052,31 +1102,33 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error0_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= field_combo.intr_block_rf.error0_intr_count_r.cnt.next; end end // Field: doe_reg.intr_block_rf.error1_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error1_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error1_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error1_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error1_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error1_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error1_intr_count_r.cnt.next = next_c; @@ -1084,31 +1136,33 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error1_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= field_combo.intr_block_rf.error1_intr_count_r.cnt.next; end end // Field: doe_reg.intr_block_rf.error2_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error2_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error2_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error2_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error2_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error2_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error2_intr_count_r.cnt.next = next_c; @@ -1116,31 +1170,33 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error2_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= field_combo.intr_block_rf.error2_intr_count_r.cnt.next; end end // Field: doe_reg.intr_block_rf.error3_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error3_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error3_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error3_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error3_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error3_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error3_intr_count_r.cnt.next = next_c; @@ -1148,31 +1204,33 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error3_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= field_combo.intr_block_rf.error3_intr_count_r.cnt.next; end end // Field: doe_reg.intr_block_rf.notif_cmd_done_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next = next_c; @@ -1180,15 +1238,17 @@ module doe_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next; end end // Field: doe_reg.intr_block_rf.error0_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; @@ -1197,27 +1257,29 @@ module doe_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.next; end end // Field: doe_reg.intr_block_rf.error1_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; @@ -1226,27 +1288,29 @@ module doe_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.next; end end // Field: doe_reg.intr_block_rf.error2_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; @@ -1255,27 +1319,29 @@ module doe_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.next; end end // Field: doe_reg.intr_block_rf.error3_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; @@ -1284,27 +1350,29 @@ module doe_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.next; end end // Field: doe_reg.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; @@ -1313,30 +1381,39 @@ module doe_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next; end end + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [25-1:0][31:0] readback_array; for(genvar i0=0; i0<4; i0++) begin @@ -1408,4 +1485,4 @@ module doe_reg ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; -endmodule \ No newline at end of file +endmodule diff --git a/src/doe/rtl/doe_reg_pkg.sv b/src/doe/rtl/doe_reg_pkg.sv index e8d318c07..12608a178 100644 --- a/src/doe/rtl/doe_reg_pkg.sv +++ b/src/doe/rtl/doe_reg_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package doe_reg_pkg; + + localparam DOE_REG_DATA_WIDTH = 32; + localparam DOE_REG_MIN_ADDR_WIDTH = 12; + typedef struct packed{ logic hwclr; } doe_reg__DOE_IV__IV__in_t; @@ -50,33 +54,33 @@ package doe_reg_pkg; typedef struct packed{ logic hwset; - } doe_reg__error_intr_t__error0_sts_enable_528ccada_next_b1018582_resetsignal_f7aac87a__in_t; + } doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error0_sts_enable_528ccada_next_b1018582_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } doe_reg__error_intr_t__error1_sts_enable_938cafef_next_f460eb81_resetsignal_f7aac87a__in_t; + } doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error1_sts_enable_938cafef_next_f460eb81_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } doe_reg__error_intr_t__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_f7aac87a__in_t; + } doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } doe_reg__error_intr_t__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_f7aac87a__in_t; + } doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_f7aac87a__in_t; typedef struct packed{ - doe_reg__error_intr_t__error0_sts_enable_528ccada_next_b1018582_resetsignal_f7aac87a__in_t error0_sts; - doe_reg__error_intr_t__error1_sts_enable_938cafef_next_f460eb81_resetsignal_f7aac87a__in_t error1_sts; - doe_reg__error_intr_t__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_f7aac87a__in_t error2_sts; - doe_reg__error_intr_t__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_f7aac87a__in_t error3_sts; + doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error0_sts_enable_528ccada_next_b1018582_resetsignal_f7aac87a__in_t error0_sts; + doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error1_sts_enable_938cafef_next_f460eb81_resetsignal_f7aac87a__in_t error1_sts; + doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_f7aac87a__in_t error2_sts; + doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_f7aac87a__in_t error3_sts; } doe_reg__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__in_t; typedef struct packed{ logic hwset; - } doe_reg__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; + } doe_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; typedef struct packed{ - doe_reg__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; + doe_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; } doe_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__in_t; typedef struct packed{ @@ -145,6 +149,13 @@ package doe_reg_pkg; doe_reg__intr_block_t__out_t intr_block_rf; } doe_reg__out_t; + typedef enum { + doe_reg__DOE_CTRL__CMD__doe_cmd_e__DOE_IDLE = 'h0, + doe_reg__DOE_CTRL__CMD__doe_cmd_e__DOE_UDS = 'h1, + doe_reg__DOE_CTRL__CMD__doe_cmd_e__DOE_FE = 'h2, + doe_reg__DOE_CTRL__CMD__doe_cmd_e__DOE_CLEAR_OBF_SECRETS = 'h3 + } doe_reg__DOE_CTRL__CMD__doe_cmd_e_e; + localparam DOE_REG_ADDR_WIDTH = 32'd12; endpackage \ No newline at end of file diff --git a/src/ecc/rtl/ecc_reg.sv b/src/ecc/rtl/ecc_reg.sv index 212ad6d15..5d7e9c5b5 100644 --- a/src/ecc/rtl/ecc_reg.sv +++ b/src/ecc/rtl/ecc_reg.sv @@ -58,7 +58,9 @@ module ecc_reg ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -109,65 +111,65 @@ module ecc_reg ( always_comb begin for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.ECC_NAME[i0] = cpuif_req_masked & (cpuif_addr == 'h0 + i0*'h4); + decoded_reg_strb.ECC_NAME[i0] = cpuif_req_masked & (cpuif_addr == 12'h0 + i0*12'h4); end for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.ECC_VERSION[i0] = cpuif_req_masked & (cpuif_addr == 'h8 + i0*'h4); + decoded_reg_strb.ECC_VERSION[i0] = cpuif_req_masked & (cpuif_addr == 12'h8 + i0*12'h4); end - decoded_reg_strb.ECC_CTRL = cpuif_req_masked & (cpuif_addr == 'h10); - decoded_reg_strb.ECC_STATUS = cpuif_req_masked & (cpuif_addr == 'h18); + decoded_reg_strb.ECC_CTRL = cpuif_req_masked & (cpuif_addr == 12'h10); + decoded_reg_strb.ECC_STATUS = cpuif_req_masked & (cpuif_addr == 12'h18); for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_SEED[i0] = cpuif_req_masked & (cpuif_addr == 'h80 + i0*'h4); + decoded_reg_strb.ECC_SEED[i0] = cpuif_req_masked & (cpuif_addr == 12'h80 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_MSG[i0] = cpuif_req_masked & (cpuif_addr == 'h100 + i0*'h4); + decoded_reg_strb.ECC_MSG[i0] = cpuif_req_masked & (cpuif_addr == 12'h100 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_PRIVKEY_OUT[i0] = cpuif_req_masked & (cpuif_addr == 'h180 + i0*'h4); + decoded_reg_strb.ECC_PRIVKEY_OUT[i0] = cpuif_req_masked & (cpuif_addr == 12'h180 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_PUBKEY_X[i0] = cpuif_req_masked & (cpuif_addr == 'h200 + i0*'h4); + decoded_reg_strb.ECC_PUBKEY_X[i0] = cpuif_req_masked & (cpuif_addr == 12'h200 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_PUBKEY_Y[i0] = cpuif_req_masked & (cpuif_addr == 'h280 + i0*'h4); + decoded_reg_strb.ECC_PUBKEY_Y[i0] = cpuif_req_masked & (cpuif_addr == 12'h280 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_SIGN_R[i0] = cpuif_req_masked & (cpuif_addr == 'h300 + i0*'h4); + decoded_reg_strb.ECC_SIGN_R[i0] = cpuif_req_masked & (cpuif_addr == 12'h300 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_SIGN_S[i0] = cpuif_req_masked & (cpuif_addr == 'h380 + i0*'h4); + decoded_reg_strb.ECC_SIGN_S[i0] = cpuif_req_masked & (cpuif_addr == 12'h380 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_VERIFY_R[i0] = cpuif_req_masked & (cpuif_addr == 'h400 + i0*'h4); + decoded_reg_strb.ECC_VERIFY_R[i0] = cpuif_req_masked & (cpuif_addr == 12'h400 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_IV[i0] = cpuif_req_masked & (cpuif_addr == 'h480 + i0*'h4); + decoded_reg_strb.ECC_IV[i0] = cpuif_req_masked & (cpuif_addr == 12'h480 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_NONCE[i0] = cpuif_req_masked & (cpuif_addr == 'h500 + i0*'h4); + decoded_reg_strb.ECC_NONCE[i0] = cpuif_req_masked & (cpuif_addr == 12'h500 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.ECC_PRIVKEY_IN[i0] = cpuif_req_masked & (cpuif_addr == 'h580 + i0*'h4); - end - decoded_reg_strb.ecc_kv_rd_pkey_ctrl = cpuif_req_masked & (cpuif_addr == 'h600); - decoded_reg_strb.ecc_kv_rd_pkey_status = cpuif_req_masked & (cpuif_addr == 'h604); - decoded_reg_strb.ecc_kv_rd_seed_ctrl = cpuif_req_masked & (cpuif_addr == 'h608); - decoded_reg_strb.ecc_kv_rd_seed_status = cpuif_req_masked & (cpuif_addr == 'h60c); - decoded_reg_strb.ecc_kv_wr_pkey_ctrl = cpuif_req_masked & (cpuif_addr == 'h610); - decoded_reg_strb.ecc_kv_wr_pkey_status = cpuif_req_masked & (cpuif_addr == 'h614); - decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h800); - decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h804); - decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h808); - decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h80c); - decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h810); - decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h814); - decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h818); - decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h81c); - decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h820); - decoded_reg_strb.intr_block_rf.error_internal_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h900); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h980); - decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha00); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha04); + decoded_reg_strb.ECC_PRIVKEY_IN[i0] = cpuif_req_masked & (cpuif_addr == 12'h580 + i0*12'h4); + end + decoded_reg_strb.ecc_kv_rd_pkey_ctrl = cpuif_req_masked & (cpuif_addr == 12'h600); + decoded_reg_strb.ecc_kv_rd_pkey_status = cpuif_req_masked & (cpuif_addr == 12'h604); + decoded_reg_strb.ecc_kv_rd_seed_ctrl = cpuif_req_masked & (cpuif_addr == 12'h608); + decoded_reg_strb.ecc_kv_rd_seed_status = cpuif_req_masked & (cpuif_addr == 12'h60c); + decoded_reg_strb.ecc_kv_wr_pkey_ctrl = cpuif_req_masked & (cpuif_addr == 12'h610); + decoded_reg_strb.ecc_kv_wr_pkey_status = cpuif_req_masked & (cpuif_addr == 12'h614); + decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h800); + decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h804); + decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h808); + decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h80c); + decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h810); + decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h814); + decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h818); + decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h81c); + decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h820); + decoded_reg_strb.intr_block_rf.error_internal_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h900); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h980); + decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha00); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha04); end // Pass down signals to next stage @@ -176,10 +178,6 @@ module ecc_reg ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -658,8 +656,10 @@ module ecc_reg ( // Field: ecc_reg.ECC_CTRL.CTRL always_comb begin - automatic logic [1:0] next_c = field_storage.ECC_CTRL.CTRL.value; - automatic logic load_next_c = '0; + automatic logic [1:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_CTRL.CTRL.value; + load_next_c = '0; if(decoded_reg_strb.ECC_CTRL && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_CTRL.CTRL.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]); load_next_c = '1; @@ -672,7 +672,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_CTRL.CTRL.value <= 'h0; + field_storage.ECC_CTRL.CTRL.value <= 2'h0; end else if(field_combo.ECC_CTRL.CTRL.load_next) begin field_storage.ECC_CTRL.CTRL.value <= field_combo.ECC_CTRL.CTRL.next; end @@ -680,12 +680,14 @@ module ecc_reg ( assign hwif_out.ECC_CTRL.CTRL.value = field_storage.ECC_CTRL.CTRL.value; // Field: ecc_reg.ECC_CTRL.ZEROIZE always_comb begin - automatic logic [0:0] next_c = field_storage.ECC_CTRL.ZEROIZE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_CTRL.ZEROIZE.value; + load_next_c = '0; if(decoded_reg_strb.ECC_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.ECC_CTRL.ZEROIZE.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -694,7 +696,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_CTRL.ZEROIZE.value <= 'h0; + field_storage.ECC_CTRL.ZEROIZE.value <= 1'h0; end else if(field_combo.ECC_CTRL.ZEROIZE.load_next) begin field_storage.ECC_CTRL.ZEROIZE.value <= field_combo.ECC_CTRL.ZEROIZE.next; end @@ -702,8 +704,10 @@ module ecc_reg ( assign hwif_out.ECC_CTRL.ZEROIZE.value = field_storage.ECC_CTRL.ZEROIZE.value; // Field: ecc_reg.ECC_CTRL.PCR_SIGN always_comb begin - automatic logic [0:0] next_c = field_storage.ECC_CTRL.PCR_SIGN.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_CTRL.PCR_SIGN.value; + load_next_c = '0; if(decoded_reg_strb.ECC_CTRL && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_CTRL.PCR_SIGN.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -716,7 +720,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_CTRL.PCR_SIGN.value <= 'h0; + field_storage.ECC_CTRL.PCR_SIGN.value <= 1'h0; end else if(field_combo.ECC_CTRL.PCR_SIGN.load_next) begin field_storage.ECC_CTRL.PCR_SIGN.value <= field_combo.ECC_CTRL.PCR_SIGN.next; end @@ -725,8 +729,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_SEED[].SEED always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_SEED[i0].SEED.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_SEED[i0].SEED.value; + load_next_c = '0; if(decoded_reg_strb.ECC_SEED[i0] && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_SEED[i0].SEED.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -742,7 +748,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_SEED[i0].SEED.value <= 'h0; + field_storage.ECC_SEED[i0].SEED.value <= 32'h0; end else if(field_combo.ECC_SEED[i0].SEED.load_next) begin field_storage.ECC_SEED[i0].SEED.value <= field_combo.ECC_SEED[i0].SEED.next; end @@ -752,8 +758,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_MSG[].MSG always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_MSG[i0].MSG.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_MSG[i0].MSG.value; + load_next_c = '0; if(decoded_reg_strb.ECC_MSG[i0] && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_MSG[i0].MSG.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -769,7 +777,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_MSG[i0].MSG.value <= 'h0; + field_storage.ECC_MSG[i0].MSG.value <= 32'h0; end else if(field_combo.ECC_MSG[i0].MSG.load_next) begin field_storage.ECC_MSG[i0].MSG.value <= field_combo.ECC_MSG[i0].MSG.next; end @@ -779,8 +787,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_PRIVKEY_OUT[].PRIVKEY_OUT always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_PRIVKEY_OUT[i0].PRIVKEY_OUT.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_PRIVKEY_OUT[i0].PRIVKEY_OUT.value; + load_next_c = '0; if(hwif_in.ECC_PRIVKEY_OUT[i0].PRIVKEY_OUT.we) begin // HW Write - we next_c = hwif_in.ECC_PRIVKEY_OUT[i0].PRIVKEY_OUT.next; load_next_c = '1; @@ -793,7 +803,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_PRIVKEY_OUT[i0].PRIVKEY_OUT.value <= 'h0; + field_storage.ECC_PRIVKEY_OUT[i0].PRIVKEY_OUT.value <= 32'h0; end else if(field_combo.ECC_PRIVKEY_OUT[i0].PRIVKEY_OUT.load_next) begin field_storage.ECC_PRIVKEY_OUT[i0].PRIVKEY_OUT.value <= field_combo.ECC_PRIVKEY_OUT[i0].PRIVKEY_OUT.next; end @@ -802,8 +812,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_PUBKEY_X[].PUBKEY_X always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_PUBKEY_X[i0].PUBKEY_X.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_PUBKEY_X[i0].PUBKEY_X.value; + load_next_c = '0; if(decoded_reg_strb.ECC_PUBKEY_X[i0] && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_PUBKEY_X[i0].PUBKEY_X.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -819,7 +831,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_PUBKEY_X[i0].PUBKEY_X.value <= 'h0; + field_storage.ECC_PUBKEY_X[i0].PUBKEY_X.value <= 32'h0; end else if(field_combo.ECC_PUBKEY_X[i0].PUBKEY_X.load_next) begin field_storage.ECC_PUBKEY_X[i0].PUBKEY_X.value <= field_combo.ECC_PUBKEY_X[i0].PUBKEY_X.next; end @@ -829,8 +841,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_PUBKEY_Y[].PUBKEY_Y always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_PUBKEY_Y[i0].PUBKEY_Y.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_PUBKEY_Y[i0].PUBKEY_Y.value; + load_next_c = '0; if(decoded_reg_strb.ECC_PUBKEY_Y[i0] && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_PUBKEY_Y[i0].PUBKEY_Y.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -846,7 +860,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_PUBKEY_Y[i0].PUBKEY_Y.value <= 'h0; + field_storage.ECC_PUBKEY_Y[i0].PUBKEY_Y.value <= 32'h0; end else if(field_combo.ECC_PUBKEY_Y[i0].PUBKEY_Y.load_next) begin field_storage.ECC_PUBKEY_Y[i0].PUBKEY_Y.value <= field_combo.ECC_PUBKEY_Y[i0].PUBKEY_Y.next; end @@ -856,8 +870,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_SIGN_R[].SIGN_R always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_SIGN_R[i0].SIGN_R.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_SIGN_R[i0].SIGN_R.value; + load_next_c = '0; if(decoded_reg_strb.ECC_SIGN_R[i0] && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_SIGN_R[i0].SIGN_R.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -873,7 +889,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_SIGN_R[i0].SIGN_R.value <= 'h0; + field_storage.ECC_SIGN_R[i0].SIGN_R.value <= 32'h0; end else if(field_combo.ECC_SIGN_R[i0].SIGN_R.load_next) begin field_storage.ECC_SIGN_R[i0].SIGN_R.value <= field_combo.ECC_SIGN_R[i0].SIGN_R.next; end @@ -883,8 +899,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_SIGN_S[].SIGN_S always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_SIGN_S[i0].SIGN_S.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_SIGN_S[i0].SIGN_S.value; + load_next_c = '0; if(decoded_reg_strb.ECC_SIGN_S[i0] && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_SIGN_S[i0].SIGN_S.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -900,7 +918,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_SIGN_S[i0].SIGN_S.value <= 'h0; + field_storage.ECC_SIGN_S[i0].SIGN_S.value <= 32'h0; end else if(field_combo.ECC_SIGN_S[i0].SIGN_S.load_next) begin field_storage.ECC_SIGN_S[i0].SIGN_S.value <= field_combo.ECC_SIGN_S[i0].SIGN_S.next; end @@ -910,8 +928,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_VERIFY_R[].VERIFY_R always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_VERIFY_R[i0].VERIFY_R.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_VERIFY_R[i0].VERIFY_R.value; + load_next_c = '0; if(hwif_in.ECC_VERIFY_R[i0].VERIFY_R.we) begin // HW Write - we next_c = hwif_in.ECC_VERIFY_R[i0].VERIFY_R.next; load_next_c = '1; @@ -924,7 +944,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_VERIFY_R[i0].VERIFY_R.value <= 'h0; + field_storage.ECC_VERIFY_R[i0].VERIFY_R.value <= 32'h0; end else if(field_combo.ECC_VERIFY_R[i0].VERIFY_R.load_next) begin field_storage.ECC_VERIFY_R[i0].VERIFY_R.value <= field_combo.ECC_VERIFY_R[i0].VERIFY_R.next; end @@ -934,8 +954,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_IV[].IV always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_IV[i0].IV.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_IV[i0].IV.value; + load_next_c = '0; if(decoded_reg_strb.ECC_IV[i0] && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_IV[i0].IV.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -948,7 +970,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_IV[i0].IV.value <= 'h0; + field_storage.ECC_IV[i0].IV.value <= 32'h0; end else if(field_combo.ECC_IV[i0].IV.load_next) begin field_storage.ECC_IV[i0].IV.value <= field_combo.ECC_IV[i0].IV.next; end @@ -958,8 +980,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_NONCE[].NONCE always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_NONCE[i0].NONCE.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_NONCE[i0].NONCE.value; + load_next_c = '0; if(decoded_reg_strb.ECC_NONCE[i0] && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_NONCE[i0].NONCE.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -972,7 +996,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_NONCE[i0].NONCE.value <= 'h0; + field_storage.ECC_NONCE[i0].NONCE.value <= 32'h0; end else if(field_combo.ECC_NONCE[i0].NONCE.load_next) begin field_storage.ECC_NONCE[i0].NONCE.value <= field_combo.ECC_NONCE[i0].NONCE.next; end @@ -982,8 +1006,10 @@ module ecc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: ecc_reg.ECC_PRIVKEY_IN[].PRIVKEY_IN always_comb begin - automatic logic [31:0] next_c = field_storage.ECC_PRIVKEY_IN[i0].PRIVKEY_IN.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ECC_PRIVKEY_IN[i0].PRIVKEY_IN.value; + load_next_c = '0; if(decoded_reg_strb.ECC_PRIVKEY_IN[i0] && decoded_req_is_wr && hwif_in.ecc_ready) begin // SW write next_c = (field_storage.ECC_PRIVKEY_IN[i0].PRIVKEY_IN.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -999,7 +1025,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ECC_PRIVKEY_IN[i0].PRIVKEY_IN.value <= 'h0; + field_storage.ECC_PRIVKEY_IN[i0].PRIVKEY_IN.value <= 32'h0; end else if(field_combo.ECC_PRIVKEY_IN[i0].PRIVKEY_IN.load_next) begin field_storage.ECC_PRIVKEY_IN[i0].PRIVKEY_IN.value <= field_combo.ECC_PRIVKEY_IN[i0].PRIVKEY_IN.next; end @@ -1008,8 +1034,10 @@ module ecc_reg ( end // Field: ecc_reg.ecc_kv_rd_pkey_ctrl.read_en always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_rd_pkey_ctrl.read_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_pkey_ctrl.read_en.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_rd_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_rd_pkey_ctrl.read_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1022,7 +1050,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_pkey_ctrl.read_en.value <= 'h0; + field_storage.ecc_kv_rd_pkey_ctrl.read_en.value <= 1'h0; end else if(field_combo.ecc_kv_rd_pkey_ctrl.read_en.load_next) begin field_storage.ecc_kv_rd_pkey_ctrl.read_en.value <= field_combo.ecc_kv_rd_pkey_ctrl.read_en.next; end @@ -1030,8 +1058,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_rd_pkey_ctrl.read_en.value = field_storage.ecc_kv_rd_pkey_ctrl.read_en.value; // Field: ecc_reg.ecc_kv_rd_pkey_ctrl.read_entry always_comb begin - automatic logic [4:0] next_c = field_storage.ecc_kv_rd_pkey_ctrl.read_entry.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_pkey_ctrl.read_entry.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_rd_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_rd_pkey_ctrl.read_entry.value & ~decoded_wr_biten[5:1]) | (decoded_wr_data[5:1] & decoded_wr_biten[5:1]); load_next_c = '1; @@ -1041,7 +1071,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_pkey_ctrl.read_entry.value <= 'h0; + field_storage.ecc_kv_rd_pkey_ctrl.read_entry.value <= 5'h0; end else if(field_combo.ecc_kv_rd_pkey_ctrl.read_entry.load_next) begin field_storage.ecc_kv_rd_pkey_ctrl.read_entry.value <= field_combo.ecc_kv_rd_pkey_ctrl.read_entry.next; end @@ -1049,8 +1079,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_rd_pkey_ctrl.read_entry.value = field_storage.ecc_kv_rd_pkey_ctrl.read_entry.value; // Field: ecc_reg.ecc_kv_rd_pkey_ctrl.pcr_hash_extend always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_rd_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; @@ -1060,7 +1092,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.value <= 'h0; + field_storage.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.value <= 1'h0; end else if(field_combo.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.load_next) begin field_storage.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.value <= field_combo.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.next; end @@ -1068,8 +1100,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.value = field_storage.ecc_kv_rd_pkey_ctrl.pcr_hash_extend.value; // Field: ecc_reg.ecc_kv_rd_pkey_ctrl.rsvd always_comb begin - automatic logic [24:0] next_c = field_storage.ecc_kv_rd_pkey_ctrl.rsvd.value; - automatic logic load_next_c = '0; + automatic logic [24:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_pkey_ctrl.rsvd.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_rd_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_rd_pkey_ctrl.rsvd.value & ~decoded_wr_biten[31:7]) | (decoded_wr_data[31:7] & decoded_wr_biten[31:7]); load_next_c = '1; @@ -1079,7 +1113,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_pkey_ctrl.rsvd.value <= 'h0; + field_storage.ecc_kv_rd_pkey_ctrl.rsvd.value <= 25'h0; end else if(field_combo.ecc_kv_rd_pkey_ctrl.rsvd.load_next) begin field_storage.ecc_kv_rd_pkey_ctrl.rsvd.value <= field_combo.ecc_kv_rd_pkey_ctrl.rsvd.next; end @@ -1087,8 +1121,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_rd_pkey_ctrl.rsvd.value = field_storage.ecc_kv_rd_pkey_ctrl.rsvd.value; // Field: ecc_reg.ecc_kv_rd_pkey_status.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_rd_pkey_status.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_pkey_status.VALID.value; + load_next_c = '0; if(hwif_in.ecc_kv_rd_pkey_status.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -1101,15 +1137,17 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_pkey_status.VALID.value <= 'h0; + field_storage.ecc_kv_rd_pkey_status.VALID.value <= 1'h0; end else if(field_combo.ecc_kv_rd_pkey_status.VALID.load_next) begin field_storage.ecc_kv_rd_pkey_status.VALID.value <= field_combo.ecc_kv_rd_pkey_status.VALID.next; end end // Field: ecc_reg.ecc_kv_rd_seed_ctrl.read_en always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_rd_seed_ctrl.read_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_seed_ctrl.read_en.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_rd_seed_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_rd_seed_ctrl.read_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1122,7 +1160,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_seed_ctrl.read_en.value <= 'h0; + field_storage.ecc_kv_rd_seed_ctrl.read_en.value <= 1'h0; end else if(field_combo.ecc_kv_rd_seed_ctrl.read_en.load_next) begin field_storage.ecc_kv_rd_seed_ctrl.read_en.value <= field_combo.ecc_kv_rd_seed_ctrl.read_en.next; end @@ -1130,8 +1168,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_rd_seed_ctrl.read_en.value = field_storage.ecc_kv_rd_seed_ctrl.read_en.value; // Field: ecc_reg.ecc_kv_rd_seed_ctrl.read_entry always_comb begin - automatic logic [4:0] next_c = field_storage.ecc_kv_rd_seed_ctrl.read_entry.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_seed_ctrl.read_entry.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_rd_seed_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_rd_seed_ctrl.read_entry.value & ~decoded_wr_biten[5:1]) | (decoded_wr_data[5:1] & decoded_wr_biten[5:1]); load_next_c = '1; @@ -1141,7 +1181,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_seed_ctrl.read_entry.value <= 'h0; + field_storage.ecc_kv_rd_seed_ctrl.read_entry.value <= 5'h0; end else if(field_combo.ecc_kv_rd_seed_ctrl.read_entry.load_next) begin field_storage.ecc_kv_rd_seed_ctrl.read_entry.value <= field_combo.ecc_kv_rd_seed_ctrl.read_entry.next; end @@ -1149,8 +1189,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_rd_seed_ctrl.read_entry.value = field_storage.ecc_kv_rd_seed_ctrl.read_entry.value; // Field: ecc_reg.ecc_kv_rd_seed_ctrl.pcr_hash_extend always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_rd_seed_ctrl.pcr_hash_extend.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_seed_ctrl.pcr_hash_extend.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_rd_seed_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_rd_seed_ctrl.pcr_hash_extend.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; @@ -1160,7 +1202,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_seed_ctrl.pcr_hash_extend.value <= 'h0; + field_storage.ecc_kv_rd_seed_ctrl.pcr_hash_extend.value <= 1'h0; end else if(field_combo.ecc_kv_rd_seed_ctrl.pcr_hash_extend.load_next) begin field_storage.ecc_kv_rd_seed_ctrl.pcr_hash_extend.value <= field_combo.ecc_kv_rd_seed_ctrl.pcr_hash_extend.next; end @@ -1168,8 +1210,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_rd_seed_ctrl.pcr_hash_extend.value = field_storage.ecc_kv_rd_seed_ctrl.pcr_hash_extend.value; // Field: ecc_reg.ecc_kv_rd_seed_ctrl.rsvd always_comb begin - automatic logic [24:0] next_c = field_storage.ecc_kv_rd_seed_ctrl.rsvd.value; - automatic logic load_next_c = '0; + automatic logic [24:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_seed_ctrl.rsvd.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_rd_seed_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_rd_seed_ctrl.rsvd.value & ~decoded_wr_biten[31:7]) | (decoded_wr_data[31:7] & decoded_wr_biten[31:7]); load_next_c = '1; @@ -1179,7 +1223,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_seed_ctrl.rsvd.value <= 'h0; + field_storage.ecc_kv_rd_seed_ctrl.rsvd.value <= 25'h0; end else if(field_combo.ecc_kv_rd_seed_ctrl.rsvd.load_next) begin field_storage.ecc_kv_rd_seed_ctrl.rsvd.value <= field_combo.ecc_kv_rd_seed_ctrl.rsvd.next; end @@ -1187,8 +1231,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_rd_seed_ctrl.rsvd.value = field_storage.ecc_kv_rd_seed_ctrl.rsvd.value; // Field: ecc_reg.ecc_kv_rd_seed_status.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_rd_seed_status.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_rd_seed_status.VALID.value; + load_next_c = '0; if(hwif_in.ecc_kv_rd_seed_status.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -1201,15 +1247,17 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_rd_seed_status.VALID.value <= 'h0; + field_storage.ecc_kv_rd_seed_status.VALID.value <= 1'h0; end else if(field_combo.ecc_kv_rd_seed_status.VALID.load_next) begin field_storage.ecc_kv_rd_seed_status.VALID.value <= field_combo.ecc_kv_rd_seed_status.VALID.next; end end // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.write_en always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_wr_pkey_ctrl.write_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_wr_pkey_ctrl.write_en.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_wr_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_wr_pkey_ctrl.write_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1222,7 +1270,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_wr_pkey_ctrl.write_en.value <= 'h0; + field_storage.ecc_kv_wr_pkey_ctrl.write_en.value <= 1'h0; end else if(field_combo.ecc_kv_wr_pkey_ctrl.write_en.load_next) begin field_storage.ecc_kv_wr_pkey_ctrl.write_en.value <= field_combo.ecc_kv_wr_pkey_ctrl.write_en.next; end @@ -1230,8 +1278,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_wr_pkey_ctrl.write_en.value = field_storage.ecc_kv_wr_pkey_ctrl.write_en.value; // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.write_entry always_comb begin - automatic logic [4:0] next_c = field_storage.ecc_kv_wr_pkey_ctrl.write_entry.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_wr_pkey_ctrl.write_entry.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_wr_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_wr_pkey_ctrl.write_entry.value & ~decoded_wr_biten[5:1]) | (decoded_wr_data[5:1] & decoded_wr_biten[5:1]); load_next_c = '1; @@ -1241,7 +1291,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_wr_pkey_ctrl.write_entry.value <= 'h0; + field_storage.ecc_kv_wr_pkey_ctrl.write_entry.value <= 5'h0; end else if(field_combo.ecc_kv_wr_pkey_ctrl.write_entry.load_next) begin field_storage.ecc_kv_wr_pkey_ctrl.write_entry.value <= field_combo.ecc_kv_wr_pkey_ctrl.write_entry.next; end @@ -1249,8 +1299,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_wr_pkey_ctrl.write_entry.value = field_storage.ecc_kv_wr_pkey_ctrl.write_entry.value; // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_wr_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; @@ -1260,7 +1312,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.value <= 'h0; + field_storage.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.value <= 1'h0; end else if(field_combo.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.load_next) begin field_storage.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.value <= field_combo.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.next; end @@ -1268,8 +1320,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.value = field_storage.ecc_kv_wr_pkey_ctrl.hmac_key_dest_valid.value; // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_wr_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value & ~decoded_wr_biten[7:7]) | (decoded_wr_data[7:7] & decoded_wr_biten[7:7]); load_next_c = '1; @@ -1279,7 +1333,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value <= 'h0; + field_storage.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value <= 1'h0; end else if(field_combo.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.load_next) begin field_storage.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value <= field_combo.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.next; end @@ -1287,8 +1341,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value = field_storage.ecc_kv_wr_pkey_ctrl.hmac_block_dest_valid.value; // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_wr_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value & ~decoded_wr_biten[8:8]) | (decoded_wr_data[8:8] & decoded_wr_biten[8:8]); load_next_c = '1; @@ -1298,7 +1354,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value <= 'h0; + field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value <= 1'h0; end else if(field_combo.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.load_next) begin field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value <= field_combo.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.next; end @@ -1306,8 +1362,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value = field_storage.ecc_kv_wr_pkey_ctrl.sha_block_dest_valid.value; // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_wr_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.value & ~decoded_wr_biten[9:9]) | (decoded_wr_data[9:9] & decoded_wr_biten[9:9]); load_next_c = '1; @@ -1317,7 +1375,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.value <= 'h0; + field_storage.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.value <= 1'h0; end else if(field_combo.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.load_next) begin field_storage.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.value <= field_combo.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.next; end @@ -1325,8 +1383,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.value = field_storage.ecc_kv_wr_pkey_ctrl.ecc_pkey_dest_valid.value; // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_wr_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.value & ~decoded_wr_biten[10:10]) | (decoded_wr_data[10:10] & decoded_wr_biten[10:10]); load_next_c = '1; @@ -1336,7 +1396,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.value <= 'h0; + field_storage.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.value <= 1'h0; end else if(field_combo.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.load_next) begin field_storage.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.value <= field_combo.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.next; end @@ -1344,8 +1404,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.value = field_storage.ecc_kv_wr_pkey_ctrl.ecc_seed_dest_valid.value; // Field: ecc_reg.ecc_kv_wr_pkey_ctrl.rsvd always_comb begin - automatic logic [20:0] next_c = field_storage.ecc_kv_wr_pkey_ctrl.rsvd.value; - automatic logic load_next_c = '0; + automatic logic [20:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_wr_pkey_ctrl.rsvd.value; + load_next_c = '0; if(decoded_reg_strb.ecc_kv_wr_pkey_ctrl && decoded_req_is_wr) begin // SW write next_c = (field_storage.ecc_kv_wr_pkey_ctrl.rsvd.value & ~decoded_wr_biten[31:11]) | (decoded_wr_data[31:11] & decoded_wr_biten[31:11]); load_next_c = '1; @@ -1355,7 +1417,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_wr_pkey_ctrl.rsvd.value <= 'h0; + field_storage.ecc_kv_wr_pkey_ctrl.rsvd.value <= 21'h0; end else if(field_combo.ecc_kv_wr_pkey_ctrl.rsvd.load_next) begin field_storage.ecc_kv_wr_pkey_ctrl.rsvd.value <= field_combo.ecc_kv_wr_pkey_ctrl.rsvd.next; end @@ -1363,8 +1425,10 @@ module ecc_reg ( assign hwif_out.ecc_kv_wr_pkey_ctrl.rsvd.value = field_storage.ecc_kv_wr_pkey_ctrl.rsvd.value; // Field: ecc_reg.ecc_kv_wr_pkey_status.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.ecc_kv_wr_pkey_status.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.ecc_kv_wr_pkey_status.VALID.value; + load_next_c = '0; if(hwif_in.ecc_kv_wr_pkey_status.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -1377,15 +1441,17 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.ecc_kv_wr_pkey_status.VALID.value <= 'h0; + field_storage.ecc_kv_wr_pkey_status.VALID.value <= 1'h0; end else if(field_combo.ecc_kv_wr_pkey_status.VALID.load_next) begin field_storage.ecc_kv_wr_pkey_status.VALID.value <= field_combo.ecc_kv_wr_pkey_status.VALID.next; end end // Field: ecc_reg.intr_block_rf.global_intr_en_r.error_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.error_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1395,15 +1461,17 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.error_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.error_en.value <= field_combo.intr_block_rf.global_intr_en_r.error_en.next; end end // Field: ecc_reg.intr_block_rf.global_intr_en_r.notif_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.notif_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -1413,15 +1481,17 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.notif_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= field_combo.intr_block_rf.global_intr_en_r.notif_en.next; end end // Field: ecc_reg.intr_block_rf.error_intr_en_r.error_internal_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1431,15 +1501,17 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error_internal_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_internal_en.next; end end // Field: ecc_reg.intr_block_rf.notif_intr_en_r.notif_cmd_done_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1449,25 +1521,27 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.next; end end // Field: ecc_reg.intr_block_rf.error_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.error_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.error_global_intr_r.agg_sts.next; end @@ -1476,18 +1550,20 @@ module ecc_reg ( |(field_storage.intr_block_rf.error_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.error_en.value); // Field: ecc_reg.intr_block_rf.notif_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next; end @@ -1496,9 +1572,11 @@ module ecc_reg ( |(field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.notif_en.value); // Field: ecc_reg.intr_block_rf.error_internal_intr_r.error_internal_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_internal_sts.hwset) begin // HW Set @@ -1513,7 +1591,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error_internal_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_internal_sts.next; end @@ -1522,9 +1600,11 @@ module ecc_reg ( |(field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value & field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value); // Field: ecc_reg.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.hwset) begin // HW Set @@ -1539,7 +1619,7 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.next; end @@ -1548,12 +1628,14 @@ module ecc_reg ( |(field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value); // Field: ecc_reg.intr_block_rf.error_intr_trig_r.error_internal_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1562,19 +1644,21 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error_internal_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_internal_trig.next; end end // Field: ecc_reg.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1583,31 +1667,33 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.next; end end // Field: ecc_reg.intr_block_rf.error_internal_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_internal_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error_internal_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error_internal_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error_internal_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_internal_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error_internal_intr_count_r.cnt.next = next_c; @@ -1615,31 +1701,33 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error_internal_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_internal_intr_count_r.cnt.next; end end // Field: ecc_reg.intr_block_rf.notif_cmd_done_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next = next_c; @@ -1647,15 +1735,17 @@ module ecc_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next; end end // Field: ecc_reg.intr_block_rf.error_internal_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; load_next_c = '1; @@ -1664,27 +1754,29 @@ module ecc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.next; end end // Field: ecc_reg.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; @@ -1693,30 +1785,39 @@ module ecc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next; end end + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [96-1:0][31:0] readback_array; for(genvar i0=0; i0<2; i0++) begin @@ -1813,4 +1914,4 @@ module ecc_reg ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; -endmodule \ No newline at end of file +endmodule diff --git a/src/ecc/rtl/ecc_reg_pkg.sv b/src/ecc/rtl/ecc_reg_pkg.sv index da1893d0e..833788a97 100644 --- a/src/ecc/rtl/ecc_reg_pkg.sv +++ b/src/ecc/rtl/ecc_reg_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package ecc_reg_pkg; + + localparam ECC_REG_DATA_WIDTH = 32; + localparam ECC_REG_MIN_ADDR_WIDTH = 12; + typedef struct packed{ logic [31:0] next; } ecc_reg__ECC_NAME__NAME__in_t; @@ -156,7 +160,7 @@ package ecc_reg_pkg; typedef struct packed{ kv_read_ctrl_reg__read_en__in_t read_en; - } __kv_read_ctrl_reg__in_t; + } kv_read_ctrl_reg__in_t; typedef struct packed{ logic next; @@ -175,7 +179,7 @@ package ecc_reg_pkg; kv_status_reg__READY__in_t READY; kv_status_reg__VALID__in_t VALID; kv_status_reg__ERROR__in_t ERROR; - } __kv_status_reg__in_t; + } kv_status_reg__in_t; typedef struct packed{ logic hwclr; @@ -183,22 +187,22 @@ package ecc_reg_pkg; typedef struct packed{ kv_write_ctrl_reg__write_en__in_t write_en; - } __kv_write_ctrl_reg__in_t; + } kv_write_ctrl_reg__in_t; typedef struct packed{ logic hwset; - } ecc_reg__intr_block_t__error_intr_t__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_0d7eaa27__in_t; + } ecc_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_0d7eaa27__in_t; typedef struct packed{ - ecc_reg__intr_block_t__error_intr_t__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_0d7eaa27__in_t error_internal_sts; + ecc_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_0d7eaa27__in_t error_internal_sts; } ecc_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02__in_t; typedef struct packed{ logic hwset; - } ecc_reg__intr_block_t__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; + } ecc_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; typedef struct packed{ - ecc_reg__intr_block_t__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; + ecc_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; } ecc_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e__in_t; typedef struct packed{ @@ -225,12 +229,12 @@ package ecc_reg_pkg; ecc_reg__ECC_IV__in_t [12-1:0]ECC_IV; ecc_reg__ECC_NONCE__in_t [12-1:0]ECC_NONCE; ecc_reg__ECC_PRIVKEY_IN__in_t [12-1:0]ECC_PRIVKEY_IN; - __kv_read_ctrl_reg__in_t ecc_kv_rd_pkey_ctrl; - __kv_status_reg__in_t ecc_kv_rd_pkey_status; - __kv_read_ctrl_reg__in_t ecc_kv_rd_seed_ctrl; - __kv_status_reg__in_t ecc_kv_rd_seed_status; - __kv_write_ctrl_reg__in_t ecc_kv_wr_pkey_ctrl; - __kv_status_reg__in_t ecc_kv_wr_pkey_status; + kv_read_ctrl_reg__in_t ecc_kv_rd_pkey_ctrl; + kv_status_reg__in_t ecc_kv_rd_pkey_status; + kv_read_ctrl_reg__in_t ecc_kv_rd_seed_ctrl; + kv_status_reg__in_t ecc_kv_rd_seed_status; + kv_write_ctrl_reg__in_t ecc_kv_wr_pkey_ctrl; + kv_status_reg__in_t ecc_kv_wr_pkey_status; ecc_reg__intr_block_t__in_t intr_block_rf; } ecc_reg__in_t; @@ -353,7 +357,7 @@ package ecc_reg_pkg; kv_read_ctrl_reg__read_entry__out_t read_entry; kv_read_ctrl_reg__pcr_hash_extend__out_t pcr_hash_extend; kv_read_ctrl_reg__rsvd__out_t rsvd; - } __kv_read_ctrl_reg__out_t; + } kv_read_ctrl_reg__out_t; typedef struct packed{ logic value; @@ -396,7 +400,7 @@ package ecc_reg_pkg; kv_write_ctrl_reg__ecc_pkey_dest_valid__out_t ecc_pkey_dest_valid; kv_write_ctrl_reg__ecc_seed_dest_valid__out_t ecc_seed_dest_valid; kv_write_ctrl_reg__rsvd__out_t rsvd; - } __kv_write_ctrl_reg__out_t; + } kv_write_ctrl_reg__out_t; typedef struct packed{ logic intr; @@ -433,12 +437,18 @@ package ecc_reg_pkg; ecc_reg__ECC_IV__out_t [12-1:0]ECC_IV; ecc_reg__ECC_NONCE__out_t [12-1:0]ECC_NONCE; ecc_reg__ECC_PRIVKEY_IN__out_t [12-1:0]ECC_PRIVKEY_IN; - __kv_read_ctrl_reg__out_t ecc_kv_rd_pkey_ctrl; - __kv_read_ctrl_reg__out_t ecc_kv_rd_seed_ctrl; - __kv_write_ctrl_reg__out_t ecc_kv_wr_pkey_ctrl; + kv_read_ctrl_reg__out_t ecc_kv_rd_pkey_ctrl; + kv_read_ctrl_reg__out_t ecc_kv_rd_seed_ctrl; + kv_write_ctrl_reg__out_t ecc_kv_wr_pkey_ctrl; ecc_reg__intr_block_t__out_t intr_block_rf; } ecc_reg__out_t; + typedef enum { + kv_status_reg__ERROR__kv_error_e__SUCCESS = 'h0, + kv_status_reg__ERROR__kv_error_e__KV_READ_FAIL = 'h1, + kv_status_reg__ERROR__kv_error_e__KV_WRITE_FAIL = 'h2 + } kv_status_reg__ERROR__kv_error_e_e; + localparam ECC_REG_ADDR_WIDTH = 32'd12; endpackage \ No newline at end of file diff --git a/src/hmac/rtl/hmac_reg.sv b/src/hmac/rtl/hmac_reg.sv index feabf783e..6b80b0098 100644 --- a/src/hmac/rtl/hmac_reg.sv +++ b/src/hmac/rtl/hmac_reg.sv @@ -58,7 +58,9 @@ module hmac_reg ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -108,50 +110,50 @@ module hmac_reg ( always_comb begin for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.HMAC384_NAME[i0] = cpuif_req_masked & (cpuif_addr == 'h0 + i0*'h4); + decoded_reg_strb.HMAC384_NAME[i0] = cpuif_req_masked & (cpuif_addr == 12'h0 + i0*12'h4); end for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.HMAC384_VERSION[i0] = cpuif_req_masked & (cpuif_addr == 'h8 + i0*'h4); + decoded_reg_strb.HMAC384_VERSION[i0] = cpuif_req_masked & (cpuif_addr == 12'h8 + i0*12'h4); end - decoded_reg_strb.HMAC384_CTRL = cpuif_req_masked & (cpuif_addr == 'h10); - decoded_reg_strb.HMAC384_STATUS = cpuif_req_masked & (cpuif_addr == 'h18); + decoded_reg_strb.HMAC384_CTRL = cpuif_req_masked & (cpuif_addr == 12'h10); + decoded_reg_strb.HMAC384_STATUS = cpuif_req_masked & (cpuif_addr == 12'h18); for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.HMAC384_KEY[i0] = cpuif_req_masked & (cpuif_addr == 'h40 + i0*'h4); + decoded_reg_strb.HMAC384_KEY[i0] = cpuif_req_masked & (cpuif_addr == 12'h40 + i0*12'h4); end for(int i0=0; i0<32; i0++) begin - decoded_reg_strb.HMAC384_BLOCK[i0] = cpuif_req_masked & (cpuif_addr == 'h80 + i0*'h4); + decoded_reg_strb.HMAC384_BLOCK[i0] = cpuif_req_masked & (cpuif_addr == 12'h80 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.HMAC384_TAG[i0] = cpuif_req_masked & (cpuif_addr == 'h100 + i0*'h4); + decoded_reg_strb.HMAC384_TAG[i0] = cpuif_req_masked & (cpuif_addr == 12'h100 + i0*12'h4); end for(int i0=0; i0<5; i0++) begin - decoded_reg_strb.HMAC384_LFSR_SEED[i0] = cpuif_req_masked & (cpuif_addr == 'h130 + i0*'h4); - end - decoded_reg_strb.HMAC384_KV_RD_KEY_CTRL = cpuif_req_masked & (cpuif_addr == 'h600); - decoded_reg_strb.HMAC384_KV_RD_KEY_STATUS = cpuif_req_masked & (cpuif_addr == 'h604); - decoded_reg_strb.HMAC384_KV_RD_BLOCK_CTRL = cpuif_req_masked & (cpuif_addr == 'h608); - decoded_reg_strb.HMAC384_KV_RD_BLOCK_STATUS = cpuif_req_masked & (cpuif_addr == 'h60c); - decoded_reg_strb.HMAC384_KV_WR_CTRL = cpuif_req_masked & (cpuif_addr == 'h610); - decoded_reg_strb.HMAC384_KV_WR_STATUS = cpuif_req_masked & (cpuif_addr == 'h614); - decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h800); - decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h804); - decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h808); - decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h80c); - decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h810); - decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h814); - decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h818); - decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h81c); - decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h820); - decoded_reg_strb.intr_block_rf.error0_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h900); - decoded_reg_strb.intr_block_rf.error1_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h904); - decoded_reg_strb.intr_block_rf.error2_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h908); - decoded_reg_strb.intr_block_rf.error3_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h90c); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h980); - decoded_reg_strb.intr_block_rf.error0_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha00); - decoded_reg_strb.intr_block_rf.error1_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha04); - decoded_reg_strb.intr_block_rf.error2_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha08); - decoded_reg_strb.intr_block_rf.error3_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha0c); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha10); + decoded_reg_strb.HMAC384_LFSR_SEED[i0] = cpuif_req_masked & (cpuif_addr == 12'h130 + i0*12'h4); + end + decoded_reg_strb.HMAC384_KV_RD_KEY_CTRL = cpuif_req_masked & (cpuif_addr == 12'h600); + decoded_reg_strb.HMAC384_KV_RD_KEY_STATUS = cpuif_req_masked & (cpuif_addr == 12'h604); + decoded_reg_strb.HMAC384_KV_RD_BLOCK_CTRL = cpuif_req_masked & (cpuif_addr == 12'h608); + decoded_reg_strb.HMAC384_KV_RD_BLOCK_STATUS = cpuif_req_masked & (cpuif_addr == 12'h60c); + decoded_reg_strb.HMAC384_KV_WR_CTRL = cpuif_req_masked & (cpuif_addr == 12'h610); + decoded_reg_strb.HMAC384_KV_WR_STATUS = cpuif_req_masked & (cpuif_addr == 12'h614); + decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h800); + decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h804); + decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h808); + decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h80c); + decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h810); + decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h814); + decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h818); + decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h81c); + decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h820); + decoded_reg_strb.intr_block_rf.error0_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h900); + decoded_reg_strb.intr_block_rf.error1_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h904); + decoded_reg_strb.intr_block_rf.error2_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h908); + decoded_reg_strb.intr_block_rf.error3_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h90c); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h980); + decoded_reg_strb.intr_block_rf.error0_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha00); + decoded_reg_strb.intr_block_rf.error1_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha04); + decoded_reg_strb.intr_block_rf.error2_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha08); + decoded_reg_strb.intr_block_rf.error3_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha0c); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha10); end // Pass down signals to next stage @@ -160,10 +162,6 @@ module hmac_reg ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -706,12 +704,14 @@ module hmac_reg ( // Field: hmac_reg.HMAC384_CTRL.INIT always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_CTRL.INIT.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_CTRL.INIT.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_CTRL.INIT.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -720,7 +720,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_CTRL.INIT.value <= 'h0; + field_storage.HMAC384_CTRL.INIT.value <= 1'h0; end else if(field_combo.HMAC384_CTRL.INIT.load_next) begin field_storage.HMAC384_CTRL.INIT.value <= field_combo.HMAC384_CTRL.INIT.next; end @@ -728,12 +728,14 @@ module hmac_reg ( assign hwif_out.HMAC384_CTRL.INIT.value = field_storage.HMAC384_CTRL.INIT.value; // Field: hmac_reg.HMAC384_CTRL.NEXT always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_CTRL.NEXT.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_CTRL.NEXT.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_CTRL.NEXT.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -742,7 +744,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_CTRL.NEXT.value <= 'h0; + field_storage.HMAC384_CTRL.NEXT.value <= 1'h0; end else if(field_combo.HMAC384_CTRL.NEXT.load_next) begin field_storage.HMAC384_CTRL.NEXT.value <= field_combo.HMAC384_CTRL.NEXT.next; end @@ -750,12 +752,14 @@ module hmac_reg ( assign hwif_out.HMAC384_CTRL.NEXT.value = field_storage.HMAC384_CTRL.NEXT.value; // Field: hmac_reg.HMAC384_CTRL.ZEROIZE always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_CTRL.ZEROIZE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_CTRL.ZEROIZE.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_CTRL.ZEROIZE.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -764,7 +768,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_CTRL.ZEROIZE.value <= 'h0; + field_storage.HMAC384_CTRL.ZEROIZE.value <= 1'h0; end else if(field_combo.HMAC384_CTRL.ZEROIZE.load_next) begin field_storage.HMAC384_CTRL.ZEROIZE.value <= field_combo.HMAC384_CTRL.ZEROIZE.next; end @@ -773,8 +777,10 @@ module hmac_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: hmac_reg.HMAC384_KEY[].KEY always_comb begin - automatic logic [31:0] next_c = field_storage.HMAC384_KEY[i0].KEY.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KEY[i0].KEY.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KEY[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KEY[i0].KEY.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -790,7 +796,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KEY[i0].KEY.value <= 'h0; + field_storage.HMAC384_KEY[i0].KEY.value <= 32'h0; end else if(field_combo.HMAC384_KEY[i0].KEY.load_next) begin field_storage.HMAC384_KEY[i0].KEY.value <= field_combo.HMAC384_KEY[i0].KEY.next; end @@ -800,8 +806,10 @@ module hmac_reg ( for(genvar i0=0; i0<32; i0++) begin // Field: hmac_reg.HMAC384_BLOCK[].BLOCK always_comb begin - automatic logic [31:0] next_c = field_storage.HMAC384_BLOCK[i0].BLOCK.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_BLOCK[i0].BLOCK.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_BLOCK[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_BLOCK[i0].BLOCK.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -817,7 +825,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_BLOCK[i0].BLOCK.value <= 'h0; + field_storage.HMAC384_BLOCK[i0].BLOCK.value <= 32'h0; end else if(field_combo.HMAC384_BLOCK[i0].BLOCK.load_next) begin field_storage.HMAC384_BLOCK[i0].BLOCK.value <= field_combo.HMAC384_BLOCK[i0].BLOCK.next; end @@ -827,21 +835,23 @@ module hmac_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: hmac_reg.HMAC384_TAG[].TAG always_comb begin - automatic logic [31:0] next_c = field_storage.HMAC384_TAG[i0].TAG.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.HMAC384_TAG[i0].TAG.next; - load_next_c = '1; - end else if(hwif_in.HMAC384_TAG[i0].TAG.hwclr) begin // HW Clear + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_TAG[i0].TAG.value; + load_next_c = '0; + if(hwif_in.HMAC384_TAG[i0].TAG.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; + end else begin // HW Write + next_c = hwif_in.HMAC384_TAG[i0].TAG.next; + load_next_c = '1; end field_combo.HMAC384_TAG[i0].TAG.next = next_c; field_combo.HMAC384_TAG[i0].TAG.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_TAG[i0].TAG.value <= 'h0; + field_storage.HMAC384_TAG[i0].TAG.value <= 32'h0; end else if(field_combo.HMAC384_TAG[i0].TAG.load_next) begin field_storage.HMAC384_TAG[i0].TAG.value <= field_combo.HMAC384_TAG[i0].TAG.next; end @@ -850,8 +860,10 @@ module hmac_reg ( for(genvar i0=0; i0<5; i0++) begin // Field: hmac_reg.HMAC384_LFSR_SEED[].LFSR_SEED always_comb begin - automatic logic [31:0] next_c = field_storage.HMAC384_LFSR_SEED[i0].LFSR_SEED.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_LFSR_SEED[i0].LFSR_SEED.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_LFSR_SEED[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_LFSR_SEED[i0].LFSR_SEED.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -861,7 +873,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_LFSR_SEED[i0].LFSR_SEED.value <= 'h3cabffb0; + field_storage.HMAC384_LFSR_SEED[i0].LFSR_SEED.value <= 32'h3cabffb0; end else if(field_combo.HMAC384_LFSR_SEED[i0].LFSR_SEED.load_next) begin field_storage.HMAC384_LFSR_SEED[i0].LFSR_SEED.value <= field_combo.HMAC384_LFSR_SEED[i0].LFSR_SEED.next; end @@ -870,8 +882,10 @@ module hmac_reg ( end // Field: hmac_reg.HMAC384_KV_RD_KEY_CTRL.read_en always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_RD_KEY_CTRL.read_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_KEY_CTRL.read_en.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_RD_KEY_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_RD_KEY_CTRL.read_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -884,7 +898,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_KEY_CTRL.read_en.value <= 'h0; + field_storage.HMAC384_KV_RD_KEY_CTRL.read_en.value <= 1'h0; end else if(field_combo.HMAC384_KV_RD_KEY_CTRL.read_en.load_next) begin field_storage.HMAC384_KV_RD_KEY_CTRL.read_en.value <= field_combo.HMAC384_KV_RD_KEY_CTRL.read_en.next; end @@ -892,8 +906,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_RD_KEY_CTRL.read_en.value = field_storage.HMAC384_KV_RD_KEY_CTRL.read_en.value; // Field: hmac_reg.HMAC384_KV_RD_KEY_CTRL.read_entry always_comb begin - automatic logic [4:0] next_c = field_storage.HMAC384_KV_RD_KEY_CTRL.read_entry.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_KEY_CTRL.read_entry.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_RD_KEY_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_RD_KEY_CTRL.read_entry.value & ~decoded_wr_biten[5:1]) | (decoded_wr_data[5:1] & decoded_wr_biten[5:1]); load_next_c = '1; @@ -903,7 +919,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_KEY_CTRL.read_entry.value <= 'h0; + field_storage.HMAC384_KV_RD_KEY_CTRL.read_entry.value <= 5'h0; end else if(field_combo.HMAC384_KV_RD_KEY_CTRL.read_entry.load_next) begin field_storage.HMAC384_KV_RD_KEY_CTRL.read_entry.value <= field_combo.HMAC384_KV_RD_KEY_CTRL.read_entry.next; end @@ -911,8 +927,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_RD_KEY_CTRL.read_entry.value = field_storage.HMAC384_KV_RD_KEY_CTRL.read_entry.value; // Field: hmac_reg.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_RD_KEY_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; @@ -922,7 +940,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.value <= 'h0; + field_storage.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.value <= 1'h0; end else if(field_combo.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.load_next) begin field_storage.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.value <= field_combo.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.next; end @@ -930,8 +948,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.value = field_storage.HMAC384_KV_RD_KEY_CTRL.pcr_hash_extend.value; // Field: hmac_reg.HMAC384_KV_RD_KEY_CTRL.rsvd always_comb begin - automatic logic [24:0] next_c = field_storage.HMAC384_KV_RD_KEY_CTRL.rsvd.value; - automatic logic load_next_c = '0; + automatic logic [24:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_KEY_CTRL.rsvd.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_RD_KEY_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_RD_KEY_CTRL.rsvd.value & ~decoded_wr_biten[31:7]) | (decoded_wr_data[31:7] & decoded_wr_biten[31:7]); load_next_c = '1; @@ -941,7 +961,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_KEY_CTRL.rsvd.value <= 'h0; + field_storage.HMAC384_KV_RD_KEY_CTRL.rsvd.value <= 25'h0; end else if(field_combo.HMAC384_KV_RD_KEY_CTRL.rsvd.load_next) begin field_storage.HMAC384_KV_RD_KEY_CTRL.rsvd.value <= field_combo.HMAC384_KV_RD_KEY_CTRL.rsvd.next; end @@ -949,8 +969,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_RD_KEY_CTRL.rsvd.value = field_storage.HMAC384_KV_RD_KEY_CTRL.rsvd.value; // Field: hmac_reg.HMAC384_KV_RD_KEY_STATUS.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_RD_KEY_STATUS.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_KEY_STATUS.VALID.value; + load_next_c = '0; if(hwif_in.HMAC384_KV_RD_KEY_STATUS.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -963,15 +985,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_KEY_STATUS.VALID.value <= 'h0; + field_storage.HMAC384_KV_RD_KEY_STATUS.VALID.value <= 1'h0; end else if(field_combo.HMAC384_KV_RD_KEY_STATUS.VALID.load_next) begin field_storage.HMAC384_KV_RD_KEY_STATUS.VALID.value <= field_combo.HMAC384_KV_RD_KEY_STATUS.VALID.next; end end // Field: hmac_reg.HMAC384_KV_RD_BLOCK_CTRL.read_en always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_en.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_RD_BLOCK_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -984,7 +1008,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_en.value <= 'h0; + field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_en.value <= 1'h0; end else if(field_combo.HMAC384_KV_RD_BLOCK_CTRL.read_en.load_next) begin field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_en.value <= field_combo.HMAC384_KV_RD_BLOCK_CTRL.read_en.next; end @@ -992,8 +1016,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_RD_BLOCK_CTRL.read_en.value = field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_en.value; // Field: hmac_reg.HMAC384_KV_RD_BLOCK_CTRL.read_entry always_comb begin - automatic logic [4:0] next_c = field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_entry.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_entry.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_RD_BLOCK_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_entry.value & ~decoded_wr_biten[5:1]) | (decoded_wr_data[5:1] & decoded_wr_biten[5:1]); load_next_c = '1; @@ -1003,7 +1029,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_entry.value <= 'h0; + field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_entry.value <= 5'h0; end else if(field_combo.HMAC384_KV_RD_BLOCK_CTRL.read_entry.load_next) begin field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_entry.value <= field_combo.HMAC384_KV_RD_BLOCK_CTRL.read_entry.next; end @@ -1011,8 +1037,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_RD_BLOCK_CTRL.read_entry.value = field_storage.HMAC384_KV_RD_BLOCK_CTRL.read_entry.value; // Field: hmac_reg.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_RD_BLOCK_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; @@ -1022,7 +1050,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.value <= 'h0; + field_storage.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.value <= 1'h0; end else if(field_combo.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.load_next) begin field_storage.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.value <= field_combo.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.next; end @@ -1030,8 +1058,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.value = field_storage.HMAC384_KV_RD_BLOCK_CTRL.pcr_hash_extend.value; // Field: hmac_reg.HMAC384_KV_RD_BLOCK_CTRL.rsvd always_comb begin - automatic logic [24:0] next_c = field_storage.HMAC384_KV_RD_BLOCK_CTRL.rsvd.value; - automatic logic load_next_c = '0; + automatic logic [24:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_BLOCK_CTRL.rsvd.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_RD_BLOCK_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_RD_BLOCK_CTRL.rsvd.value & ~decoded_wr_biten[31:7]) | (decoded_wr_data[31:7] & decoded_wr_biten[31:7]); load_next_c = '1; @@ -1041,7 +1071,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_BLOCK_CTRL.rsvd.value <= 'h0; + field_storage.HMAC384_KV_RD_BLOCK_CTRL.rsvd.value <= 25'h0; end else if(field_combo.HMAC384_KV_RD_BLOCK_CTRL.rsvd.load_next) begin field_storage.HMAC384_KV_RD_BLOCK_CTRL.rsvd.value <= field_combo.HMAC384_KV_RD_BLOCK_CTRL.rsvd.next; end @@ -1049,8 +1079,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_RD_BLOCK_CTRL.rsvd.value = field_storage.HMAC384_KV_RD_BLOCK_CTRL.rsvd.value; // Field: hmac_reg.HMAC384_KV_RD_BLOCK_STATUS.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_RD_BLOCK_STATUS.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_RD_BLOCK_STATUS.VALID.value; + load_next_c = '0; if(hwif_in.HMAC384_KV_RD_BLOCK_STATUS.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -1063,15 +1095,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_RD_BLOCK_STATUS.VALID.value <= 'h0; + field_storage.HMAC384_KV_RD_BLOCK_STATUS.VALID.value <= 1'h0; end else if(field_combo.HMAC384_KV_RD_BLOCK_STATUS.VALID.load_next) begin field_storage.HMAC384_KV_RD_BLOCK_STATUS.VALID.value <= field_combo.HMAC384_KV_RD_BLOCK_STATUS.VALID.next; end end // Field: hmac_reg.HMAC384_KV_WR_CTRL.write_en always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_WR_CTRL.write_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_WR_CTRL.write_en.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_WR_CTRL.write_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1084,7 +1118,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_WR_CTRL.write_en.value <= 'h0; + field_storage.HMAC384_KV_WR_CTRL.write_en.value <= 1'h0; end else if(field_combo.HMAC384_KV_WR_CTRL.write_en.load_next) begin field_storage.HMAC384_KV_WR_CTRL.write_en.value <= field_combo.HMAC384_KV_WR_CTRL.write_en.next; end @@ -1092,8 +1126,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_WR_CTRL.write_en.value = field_storage.HMAC384_KV_WR_CTRL.write_en.value; // Field: hmac_reg.HMAC384_KV_WR_CTRL.write_entry always_comb begin - automatic logic [4:0] next_c = field_storage.HMAC384_KV_WR_CTRL.write_entry.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_WR_CTRL.write_entry.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_WR_CTRL.write_entry.value & ~decoded_wr_biten[5:1]) | (decoded_wr_data[5:1] & decoded_wr_biten[5:1]); load_next_c = '1; @@ -1103,7 +1139,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_WR_CTRL.write_entry.value <= 'h0; + field_storage.HMAC384_KV_WR_CTRL.write_entry.value <= 5'h0; end else if(field_combo.HMAC384_KV_WR_CTRL.write_entry.load_next) begin field_storage.HMAC384_KV_WR_CTRL.write_entry.value <= field_combo.HMAC384_KV_WR_CTRL.write_entry.next; end @@ -1111,8 +1147,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_WR_CTRL.write_entry.value = field_storage.HMAC384_KV_WR_CTRL.write_entry.value; // Field: hmac_reg.HMAC384_KV_WR_CTRL.hmac_key_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; @@ -1122,7 +1160,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.value <= 'h0; + field_storage.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.value <= 1'h0; end else if(field_combo.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.load_next) begin field_storage.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.value <= field_combo.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.next; end @@ -1130,8 +1168,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.value = field_storage.HMAC384_KV_WR_CTRL.hmac_key_dest_valid.value; // Field: hmac_reg.HMAC384_KV_WR_CTRL.hmac_block_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.value & ~decoded_wr_biten[7:7]) | (decoded_wr_data[7:7] & decoded_wr_biten[7:7]); load_next_c = '1; @@ -1141,7 +1181,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.value <= 'h0; + field_storage.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.value <= 1'h0; end else if(field_combo.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.load_next) begin field_storage.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.value <= field_combo.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.next; end @@ -1149,8 +1189,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.value = field_storage.HMAC384_KV_WR_CTRL.hmac_block_dest_valid.value; // Field: hmac_reg.HMAC384_KV_WR_CTRL.sha_block_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_WR_CTRL.sha_block_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_WR_CTRL.sha_block_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_WR_CTRL.sha_block_dest_valid.value & ~decoded_wr_biten[8:8]) | (decoded_wr_data[8:8] & decoded_wr_biten[8:8]); load_next_c = '1; @@ -1160,7 +1202,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_WR_CTRL.sha_block_dest_valid.value <= 'h0; + field_storage.HMAC384_KV_WR_CTRL.sha_block_dest_valid.value <= 1'h0; end else if(field_combo.HMAC384_KV_WR_CTRL.sha_block_dest_valid.load_next) begin field_storage.HMAC384_KV_WR_CTRL.sha_block_dest_valid.value <= field_combo.HMAC384_KV_WR_CTRL.sha_block_dest_valid.next; end @@ -1168,8 +1210,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_WR_CTRL.sha_block_dest_valid.value = field_storage.HMAC384_KV_WR_CTRL.sha_block_dest_valid.value; // Field: hmac_reg.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.value & ~decoded_wr_biten[9:9]) | (decoded_wr_data[9:9] & decoded_wr_biten[9:9]); load_next_c = '1; @@ -1179,7 +1223,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.value <= 'h0; + field_storage.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.value <= 1'h0; end else if(field_combo.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.load_next) begin field_storage.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.value <= field_combo.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.next; end @@ -1187,8 +1231,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.value = field_storage.HMAC384_KV_WR_CTRL.ecc_pkey_dest_valid.value; // Field: hmac_reg.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.value & ~decoded_wr_biten[10:10]) | (decoded_wr_data[10:10] & decoded_wr_biten[10:10]); load_next_c = '1; @@ -1198,7 +1244,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.value <= 'h0; + field_storage.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.value <= 1'h0; end else if(field_combo.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.load_next) begin field_storage.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.value <= field_combo.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.next; end @@ -1206,8 +1252,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.value = field_storage.HMAC384_KV_WR_CTRL.ecc_seed_dest_valid.value; // Field: hmac_reg.HMAC384_KV_WR_CTRL.rsvd always_comb begin - automatic logic [20:0] next_c = field_storage.HMAC384_KV_WR_CTRL.rsvd.value; - automatic logic load_next_c = '0; + automatic logic [20:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_WR_CTRL.rsvd.value; + load_next_c = '0; if(decoded_reg_strb.HMAC384_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.HMAC384_KV_WR_CTRL.rsvd.value & ~decoded_wr_biten[31:11]) | (decoded_wr_data[31:11] & decoded_wr_biten[31:11]); load_next_c = '1; @@ -1217,7 +1265,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_WR_CTRL.rsvd.value <= 'h0; + field_storage.HMAC384_KV_WR_CTRL.rsvd.value <= 21'h0; end else if(field_combo.HMAC384_KV_WR_CTRL.rsvd.load_next) begin field_storage.HMAC384_KV_WR_CTRL.rsvd.value <= field_combo.HMAC384_KV_WR_CTRL.rsvd.next; end @@ -1225,8 +1273,10 @@ module hmac_reg ( assign hwif_out.HMAC384_KV_WR_CTRL.rsvd.value = field_storage.HMAC384_KV_WR_CTRL.rsvd.value; // Field: hmac_reg.HMAC384_KV_WR_STATUS.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.HMAC384_KV_WR_STATUS.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.HMAC384_KV_WR_STATUS.VALID.value; + load_next_c = '0; if(hwif_in.HMAC384_KV_WR_STATUS.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -1239,15 +1289,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.HMAC384_KV_WR_STATUS.VALID.value <= 'h0; + field_storage.HMAC384_KV_WR_STATUS.VALID.value <= 1'h0; end else if(field_combo.HMAC384_KV_WR_STATUS.VALID.load_next) begin field_storage.HMAC384_KV_WR_STATUS.VALID.value <= field_combo.HMAC384_KV_WR_STATUS.VALID.next; end end // Field: hmac_reg.intr_block_rf.global_intr_en_r.error_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.error_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1257,15 +1309,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.error_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.error_en.value <= field_combo.intr_block_rf.global_intr_en_r.error_en.next; end end // Field: hmac_reg.intr_block_rf.global_intr_en_r.notif_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.notif_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -1275,15 +1329,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.notif_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= field_combo.intr_block_rf.global_intr_en_r.notif_en.next; end end // Field: hmac_reg.intr_block_rf.error_intr_en_r.error0_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error0_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1293,15 +1349,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error0_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= field_combo.intr_block_rf.error_intr_en_r.error0_en.next; end end // Field: hmac_reg.intr_block_rf.error_intr_en_r.error1_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error1_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -1311,15 +1369,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error1_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= field_combo.intr_block_rf.error_intr_en_r.error1_en.next; end end // Field: hmac_reg.intr_block_rf.error_intr_en_r.error2_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error2_en.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -1329,15 +1389,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error2_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= field_combo.intr_block_rf.error_intr_en_r.error2_en.next; end end // Field: hmac_reg.intr_block_rf.error_intr_en_r.error3_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error3_en.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -1347,15 +1409,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error3_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= field_combo.intr_block_rf.error_intr_en_r.error3_en.next; end end // Field: hmac_reg.intr_block_rf.notif_intr_en_r.notif_cmd_done_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1365,25 +1429,27 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.next; end end // Field: hmac_reg.intr_block_rf.error_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.error_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.error_global_intr_r.agg_sts.next; end @@ -1392,18 +1458,20 @@ module hmac_reg ( |(field_storage.intr_block_rf.error_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.error_en.value); // Field: hmac_reg.intr_block_rf.notif_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next; end @@ -1412,9 +1480,11 @@ module hmac_reg ( |(field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.notif_en.value); // Field: hmac_reg.intr_block_rf.error_internal_intr_r.error0_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error0_sts.hwset) begin // HW Set @@ -1429,16 +1499,18 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error0_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error0_sts.next; end end // Field: hmac_reg.intr_block_rf.error_internal_intr_r.error1_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error1_sts.hwset) begin // HW Set @@ -1453,16 +1525,18 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error1_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error1_sts.next; end end // Field: hmac_reg.intr_block_rf.error_internal_intr_r.error2_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error2_sts.hwset) begin // HW Set @@ -1477,16 +1551,18 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error2_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error2_sts.next; end end // Field: hmac_reg.intr_block_rf.error_internal_intr_r.error3_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error3_sts.hwset) begin // HW Set @@ -1501,7 +1577,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error3_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error3_sts.next; end @@ -1513,9 +1589,11 @@ module hmac_reg ( || |(field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value & field_storage.intr_block_rf.error_intr_en_r.error3_en.value); // Field: hmac_reg.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.hwset) begin // HW Set @@ -1530,7 +1608,7 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.next; end @@ -1539,12 +1617,14 @@ module hmac_reg ( |(field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value); // Field: hmac_reg.intr_block_rf.error_intr_trig_r.error0_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1553,19 +1633,21 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error0_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error0_trig.next; end end // Field: hmac_reg.intr_block_rf.error_intr_trig_r.error1_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1574,19 +1656,21 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error1_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error1_trig.next; end end // Field: hmac_reg.intr_block_rf.error_intr_trig_r.error2_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1595,19 +1679,21 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error2_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error2_trig.next; end end // Field: hmac_reg.intr_block_rf.error_intr_trig_r.error3_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1616,19 +1702,21 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error3_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error3_trig.next; end end // Field: hmac_reg.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1637,31 +1725,33 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.next; end end // Field: hmac_reg.intr_block_rf.error0_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error0_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error0_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error0_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error0_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error0_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error0_intr_count_r.cnt.next = next_c; @@ -1669,31 +1759,33 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error0_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= field_combo.intr_block_rf.error0_intr_count_r.cnt.next; end end // Field: hmac_reg.intr_block_rf.error1_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error1_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error1_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error1_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error1_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error1_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error1_intr_count_r.cnt.next = next_c; @@ -1701,31 +1793,33 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error1_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= field_combo.intr_block_rf.error1_intr_count_r.cnt.next; end end // Field: hmac_reg.intr_block_rf.error2_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error2_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error2_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error2_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error2_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error2_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error2_intr_count_r.cnt.next = next_c; @@ -1733,31 +1827,33 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error2_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= field_combo.intr_block_rf.error2_intr_count_r.cnt.next; end end // Field: hmac_reg.intr_block_rf.error3_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error3_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error3_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error3_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error3_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error3_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error3_intr_count_r.cnt.next = next_c; @@ -1765,31 +1861,33 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error3_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= field_combo.intr_block_rf.error3_intr_count_r.cnt.next; end end // Field: hmac_reg.intr_block_rf.notif_cmd_done_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next = next_c; @@ -1797,15 +1895,17 @@ module hmac_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next; end end // Field: hmac_reg.intr_block_rf.error0_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; @@ -1814,27 +1914,29 @@ module hmac_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.next; end end // Field: hmac_reg.intr_block_rf.error1_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; @@ -1843,27 +1945,29 @@ module hmac_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.next; end end // Field: hmac_reg.intr_block_rf.error2_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; @@ -1872,27 +1976,29 @@ module hmac_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.next; end end // Field: hmac_reg.intr_block_rf.error3_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; @@ -1901,27 +2007,29 @@ module hmac_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.next; end end // Field: hmac_reg.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; @@ -1930,30 +2038,39 @@ module hmac_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next; end end + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [42-1:0][31:0] readback_array; for(genvar i0=0; i0<2; i0++) begin @@ -2053,4 +2170,4 @@ module hmac_reg ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; -endmodule \ No newline at end of file +endmodule diff --git a/src/hmac/rtl/hmac_reg_pkg.sv b/src/hmac/rtl/hmac_reg_pkg.sv index baf7273b5..556a1712a 100644 --- a/src/hmac/rtl/hmac_reg_pkg.sv +++ b/src/hmac/rtl/hmac_reg_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package hmac_reg_pkg; + + localparam HMAC_REG_DATA_WIDTH = 32; + localparam HMAC_REG_MIN_ADDR_WIDTH = 12; + typedef struct packed{ logic [31:0] next; } hmac_reg__HMAC384_NAME__NAME__in_t; @@ -66,7 +70,7 @@ package hmac_reg_pkg; typedef struct packed{ kv_read_ctrl_reg__read_en__in_t read_en; - } __kv_read_ctrl_reg__in_t; + } kv_read_ctrl_reg__in_t; typedef struct packed{ logic next; @@ -85,7 +89,7 @@ package hmac_reg_pkg; kv_status_reg__READY__in_t READY; kv_status_reg__VALID__in_t VALID; kv_status_reg__ERROR__in_t ERROR; - } __kv_status_reg__in_t; + } kv_status_reg__in_t; typedef struct packed{ logic hwclr; @@ -93,37 +97,37 @@ package hmac_reg_pkg; typedef struct packed{ kv_write_ctrl_reg__write_en__in_t write_en; - } __kv_write_ctrl_reg__in_t; + } kv_write_ctrl_reg__in_t; typedef struct packed{ logic hwset; - } hmac_reg__error_intr_t__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t; + } hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t; typedef struct packed{ logic hwset; - } hmac_reg__error_intr_t__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t; + } hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t; typedef struct packed{ logic hwset; - } hmac_reg__error_intr_t__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t; + } hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t; typedef struct packed{ logic hwset; - } hmac_reg__error_intr_t__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t; + } hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t; typedef struct packed{ - hmac_reg__error_intr_t__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t error0_sts; - hmac_reg__error_intr_t__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t error1_sts; - hmac_reg__error_intr_t__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t error2_sts; - hmac_reg__error_intr_t__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t error3_sts; + hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t error0_sts; + hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t error1_sts; + hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t error2_sts; + hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t error3_sts; } hmac_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__in_t; typedef struct packed{ logic hwset; - } hmac_reg__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; + } hmac_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; typedef struct packed{ - hmac_reg__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; + hmac_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; } hmac_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__in_t; typedef struct packed{ @@ -140,12 +144,12 @@ package hmac_reg_pkg; hmac_reg__HMAC384_KEY__in_t [12-1:0]HMAC384_KEY; hmac_reg__HMAC384_BLOCK__in_t [32-1:0]HMAC384_BLOCK; hmac_reg__HMAC384_TAG__in_t [12-1:0]HMAC384_TAG; - __kv_read_ctrl_reg__in_t HMAC384_KV_RD_KEY_CTRL; - __kv_status_reg__in_t HMAC384_KV_RD_KEY_STATUS; - __kv_read_ctrl_reg__in_t HMAC384_KV_RD_BLOCK_CTRL; - __kv_status_reg__in_t HMAC384_KV_RD_BLOCK_STATUS; - __kv_write_ctrl_reg__in_t HMAC384_KV_WR_CTRL; - __kv_status_reg__in_t HMAC384_KV_WR_STATUS; + kv_read_ctrl_reg__in_t HMAC384_KV_RD_KEY_CTRL; + kv_status_reg__in_t HMAC384_KV_RD_KEY_STATUS; + kv_read_ctrl_reg__in_t HMAC384_KV_RD_BLOCK_CTRL; + kv_status_reg__in_t HMAC384_KV_RD_BLOCK_STATUS; + kv_write_ctrl_reg__in_t HMAC384_KV_WR_CTRL; + kv_status_reg__in_t HMAC384_KV_WR_STATUS; hmac_reg__intr_block_t__in_t intr_block_rf; } hmac_reg__in_t; @@ -212,7 +216,7 @@ package hmac_reg_pkg; kv_read_ctrl_reg__read_entry__out_t read_entry; kv_read_ctrl_reg__pcr_hash_extend__out_t pcr_hash_extend; kv_read_ctrl_reg__rsvd__out_t rsvd; - } __kv_read_ctrl_reg__out_t; + } kv_read_ctrl_reg__out_t; typedef struct packed{ logic value; @@ -255,7 +259,7 @@ package hmac_reg_pkg; kv_write_ctrl_reg__ecc_pkey_dest_valid__out_t ecc_pkey_dest_valid; kv_write_ctrl_reg__ecc_seed_dest_valid__out_t ecc_seed_dest_valid; kv_write_ctrl_reg__rsvd__out_t rsvd; - } __kv_write_ctrl_reg__out_t; + } kv_write_ctrl_reg__out_t; typedef struct packed{ logic intr; @@ -285,12 +289,18 @@ package hmac_reg_pkg; hmac_reg__HMAC384_KEY__out_t [12-1:0]HMAC384_KEY; hmac_reg__HMAC384_BLOCK__out_t [32-1:0]HMAC384_BLOCK; hmac_reg__HMAC384_LFSR_SEED__out_t [5-1:0]HMAC384_LFSR_SEED; - __kv_read_ctrl_reg__out_t HMAC384_KV_RD_KEY_CTRL; - __kv_read_ctrl_reg__out_t HMAC384_KV_RD_BLOCK_CTRL; - __kv_write_ctrl_reg__out_t HMAC384_KV_WR_CTRL; + kv_read_ctrl_reg__out_t HMAC384_KV_RD_KEY_CTRL; + kv_read_ctrl_reg__out_t HMAC384_KV_RD_BLOCK_CTRL; + kv_write_ctrl_reg__out_t HMAC384_KV_WR_CTRL; hmac_reg__intr_block_t__out_t intr_block_rf; } hmac_reg__out_t; + typedef enum { + kv_status_reg__ERROR__kv_error_e__SUCCESS = 'h0, + kv_status_reg__ERROR__kv_error_e__KV_READ_FAIL = 'h1, + kv_status_reg__ERROR__kv_error_e__KV_WRITE_FAIL = 'h2 + } kv_status_reg__ERROR__kv_error_e_e; + localparam HMAC_REG_ADDR_WIDTH = 32'd12; endpackage \ No newline at end of file diff --git a/src/keyvault/rtl/kv_reg.sv b/src/keyvault/rtl/kv_reg.sv index 56c24360c..58f372183 100644 --- a/src/keyvault/rtl/kv_reg.sv +++ b/src/keyvault/rtl/kv_reg.sv @@ -58,7 +58,9 @@ module kv_reg ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -76,14 +78,14 @@ module kv_reg ( always_comb begin for(int i0=0; i0<32; i0++) begin - decoded_reg_strb.KEY_CTRL[i0] = cpuif_req_masked & (cpuif_addr == 'h0 + i0*'h4); + decoded_reg_strb.KEY_CTRL[i0] = cpuif_req_masked & (cpuif_addr == 12'h0 + i0*12'h4); end for(int i0=0; i0<32; i0++) begin for(int i1=0; i1<12; i1++) begin - decoded_reg_strb.KEY_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 'h600 + i0*'h30 + i1*'h4); + decoded_reg_strb.KEY_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 12'h600 + i0*12'h30 + i1*12'h4); end end - decoded_reg_strb.CLEAR_SECRETS = cpuif_req_masked & (cpuif_addr == 'hc00); + decoded_reg_strb.CLEAR_SECRETS = cpuif_req_masked & (cpuif_addr == 12'hc00); end // Pass down signals to next stage @@ -92,10 +94,6 @@ module kv_reg ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -192,8 +190,10 @@ module kv_reg ( for(genvar i0=0; i0<32; i0++) begin // Field: kv_reg.KEY_CTRL[].lock_wr always_comb begin - automatic logic [0:0] next_c = field_storage.KEY_CTRL[i0].lock_wr.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.KEY_CTRL[i0].lock_wr.value; + load_next_c = '0; if(decoded_reg_strb.KEY_CTRL[i0] && decoded_req_is_wr && !(hwif_in.KEY_CTRL[i0].lock_wr.swwel)) begin // SW write next_c = (field_storage.KEY_CTRL[i0].lock_wr.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -203,7 +203,7 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.core_only_rst_b) begin if(~hwif_in.core_only_rst_b) begin - field_storage.KEY_CTRL[i0].lock_wr.value <= 'h0; + field_storage.KEY_CTRL[i0].lock_wr.value <= 1'h0; end else if(field_combo.KEY_CTRL[i0].lock_wr.load_next) begin field_storage.KEY_CTRL[i0].lock_wr.value <= field_combo.KEY_CTRL[i0].lock_wr.next; end @@ -211,8 +211,10 @@ module kv_reg ( assign hwif_out.KEY_CTRL[i0].lock_wr.value = field_storage.KEY_CTRL[i0].lock_wr.value; // Field: kv_reg.KEY_CTRL[].lock_use always_comb begin - automatic logic [0:0] next_c = field_storage.KEY_CTRL[i0].lock_use.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.KEY_CTRL[i0].lock_use.value; + load_next_c = '0; if(decoded_reg_strb.KEY_CTRL[i0] && decoded_req_is_wr && !(hwif_in.KEY_CTRL[i0].lock_use.swwel)) begin // SW write next_c = (field_storage.KEY_CTRL[i0].lock_use.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -222,7 +224,7 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.core_only_rst_b) begin if(~hwif_in.core_only_rst_b) begin - field_storage.KEY_CTRL[i0].lock_use.value <= 'h0; + field_storage.KEY_CTRL[i0].lock_use.value <= 1'h0; end else if(field_combo.KEY_CTRL[i0].lock_use.load_next) begin field_storage.KEY_CTRL[i0].lock_use.value <= field_combo.KEY_CTRL[i0].lock_use.next; end @@ -230,12 +232,14 @@ module kv_reg ( assign hwif_out.KEY_CTRL[i0].lock_use.value = field_storage.KEY_CTRL[i0].lock_use.value; // Field: kv_reg.KEY_CTRL[].clear always_comb begin - automatic logic [0:0] next_c = field_storage.KEY_CTRL[i0].clear.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.KEY_CTRL[i0].clear.value; + load_next_c = '0; if(decoded_reg_strb.KEY_CTRL[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.KEY_CTRL[i0].clear.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -244,7 +248,7 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.KEY_CTRL[i0].clear.value <= 'h0; + field_storage.KEY_CTRL[i0].clear.value <= 1'h0; end else if(field_combo.KEY_CTRL[i0].clear.load_next) begin field_storage.KEY_CTRL[i0].clear.value <= field_combo.KEY_CTRL[i0].clear.next; end @@ -252,8 +256,10 @@ module kv_reg ( assign hwif_out.KEY_CTRL[i0].clear.value = field_storage.KEY_CTRL[i0].clear.value; // Field: kv_reg.KEY_CTRL[].rsvd0 always_comb begin - automatic logic [0:0] next_c = field_storage.KEY_CTRL[i0].rsvd0.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.KEY_CTRL[i0].rsvd0.value; + load_next_c = '0; if(decoded_reg_strb.KEY_CTRL[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.KEY_CTRL[i0].rsvd0.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -266,7 +272,7 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.KEY_CTRL[i0].rsvd0.value <= 'h0; + field_storage.KEY_CTRL[i0].rsvd0.value <= 1'h0; end else if(field_combo.KEY_CTRL[i0].rsvd0.load_next) begin field_storage.KEY_CTRL[i0].rsvd0.value <= field_combo.KEY_CTRL[i0].rsvd0.next; end @@ -274,8 +280,10 @@ module kv_reg ( assign hwif_out.KEY_CTRL[i0].rsvd0.value = field_storage.KEY_CTRL[i0].rsvd0.value; // Field: kv_reg.KEY_CTRL[].rsvd1 always_comb begin - automatic logic [4:0] next_c = field_storage.KEY_CTRL[i0].rsvd1.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.KEY_CTRL[i0].rsvd1.value; + load_next_c = '0; if(decoded_reg_strb.KEY_CTRL[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.KEY_CTRL[i0].rsvd1.value & ~decoded_wr_biten[8:4]) | (decoded_wr_data[8:4] & decoded_wr_biten[8:4]); load_next_c = '1; @@ -285,7 +293,7 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.KEY_CTRL[i0].rsvd1.value <= 'h0; + field_storage.KEY_CTRL[i0].rsvd1.value <= 5'h0; end else if(field_combo.KEY_CTRL[i0].rsvd1.load_next) begin field_storage.KEY_CTRL[i0].rsvd1.value <= field_combo.KEY_CTRL[i0].rsvd1.next; end @@ -293,8 +301,10 @@ module kv_reg ( assign hwif_out.KEY_CTRL[i0].rsvd1.value = field_storage.KEY_CTRL[i0].rsvd1.value; // Field: kv_reg.KEY_CTRL[].dest_valid always_comb begin - automatic logic [7:0] next_c = field_storage.KEY_CTRL[i0].dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [7:0] next_c; + automatic logic load_next_c; + next_c = field_storage.KEY_CTRL[i0].dest_valid.value; + load_next_c = '0; if(hwif_in.KEY_CTRL[i0].dest_valid.we) begin // HW Write - we next_c = hwif_in.KEY_CTRL[i0].dest_valid.next; load_next_c = '1; @@ -307,7 +317,7 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.KEY_CTRL[i0].dest_valid.value <= 'h0; + field_storage.KEY_CTRL[i0].dest_valid.value <= 8'h0; end else if(field_combo.KEY_CTRL[i0].dest_valid.load_next) begin field_storage.KEY_CTRL[i0].dest_valid.value <= field_combo.KEY_CTRL[i0].dest_valid.next; end @@ -315,8 +325,10 @@ module kv_reg ( assign hwif_out.KEY_CTRL[i0].dest_valid.value = field_storage.KEY_CTRL[i0].dest_valid.value; // Field: kv_reg.KEY_CTRL[].last_dword always_comb begin - automatic logic [3:0] next_c = field_storage.KEY_CTRL[i0].last_dword.value; - automatic logic load_next_c = '0; + automatic logic [3:0] next_c; + automatic logic load_next_c; + next_c = field_storage.KEY_CTRL[i0].last_dword.value; + load_next_c = '0; if(hwif_in.KEY_CTRL[i0].last_dword.we) begin // HW Write - we next_c = hwif_in.KEY_CTRL[i0].last_dword.next; load_next_c = '1; @@ -329,7 +341,7 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.KEY_CTRL[i0].last_dword.value <= 'h0; + field_storage.KEY_CTRL[i0].last_dword.value <= 4'h0; end else if(field_combo.KEY_CTRL[i0].last_dword.load_next) begin field_storage.KEY_CTRL[i0].last_dword.value <= field_combo.KEY_CTRL[i0].last_dword.next; end @@ -340,8 +352,10 @@ module kv_reg ( for(genvar i1=0; i1<12; i1++) begin // Field: kv_reg.KEY_ENTRY[][].data always_comb begin - automatic logic [31:0] next_c = field_storage.KEY_ENTRY[i0][i1].data.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.KEY_ENTRY[i0][i1].data.value; + load_next_c = '0; if(decoded_reg_strb.KEY_ENTRY[i0][i1] && decoded_req_is_wr && !(hwif_in.KEY_ENTRY[i0][i1].data.swwel)) begin // SW write next_c = (field_storage.KEY_ENTRY[i0][i1].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -357,7 +371,7 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.KEY_ENTRY[i0][i1].data.value <= 'h0; + field_storage.KEY_ENTRY[i0][i1].data.value <= 32'h0; end else if(field_combo.KEY_ENTRY[i0][i1].data.load_next) begin field_storage.KEY_ENTRY[i0][i1].data.value <= field_combo.KEY_ENTRY[i0][i1].data.next; end @@ -367,12 +381,14 @@ module kv_reg ( end // Field: kv_reg.CLEAR_SECRETS.wr_debug_values always_comb begin - automatic logic [0:0] next_c = field_storage.CLEAR_SECRETS.wr_debug_values.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CLEAR_SECRETS.wr_debug_values.value; + load_next_c = '0; if(decoded_reg_strb.CLEAR_SECRETS && decoded_req_is_wr) begin // SW write next_c = (field_storage.CLEAR_SECRETS.wr_debug_values.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -381,7 +397,7 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.CLEAR_SECRETS.wr_debug_values.value <= 'h0; + field_storage.CLEAR_SECRETS.wr_debug_values.value <= 1'h0; end else if(field_combo.CLEAR_SECRETS.wr_debug_values.load_next) begin field_storage.CLEAR_SECRETS.wr_debug_values.value <= field_combo.CLEAR_SECRETS.wr_debug_values.next; end @@ -389,8 +405,10 @@ module kv_reg ( assign hwif_out.CLEAR_SECRETS.wr_debug_values.value = field_storage.CLEAR_SECRETS.wr_debug_values.value; // Field: kv_reg.CLEAR_SECRETS.sel_debug_value always_comb begin - automatic logic [0:0] next_c = field_storage.CLEAR_SECRETS.sel_debug_value.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CLEAR_SECRETS.sel_debug_value.value; + load_next_c = '0; if(decoded_reg_strb.CLEAR_SECRETS && decoded_req_is_wr) begin // SW write next_c = (field_storage.CLEAR_SECRETS.sel_debug_value.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -400,19 +418,28 @@ module kv_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.CLEAR_SECRETS.sel_debug_value.value <= 'h0; + field_storage.CLEAR_SECRETS.sel_debug_value.value <= 1'h0; end else if(field_combo.CLEAR_SECRETS.sel_debug_value.load_next) begin field_storage.CLEAR_SECRETS.sel_debug_value.value <= field_combo.CLEAR_SECRETS.sel_debug_value.next; end end assign hwif_out.CLEAR_SECRETS.sel_debug_value.value = field_storage.CLEAR_SECRETS.sel_debug_value.value; + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [33-1:0][31:0] readback_array; for(genvar i0=0; i0<32; i0++) begin @@ -442,4 +469,4 @@ module kv_reg ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; -endmodule \ No newline at end of file +endmodule diff --git a/src/keyvault/rtl/kv_reg_pkg.sv b/src/keyvault/rtl/kv_reg_pkg.sv index 780e9574b..279f76d66 100644 --- a/src/keyvault/rtl/kv_reg_pkg.sv +++ b/src/keyvault/rtl/kv_reg_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package kv_reg_pkg; + + localparam KV_REG_DATA_WIDTH = 32; + localparam KV_REG_MIN_ADDR_WIDTH = 12; + typedef struct packed{ logic swwel; } kv_reg__kvCtrl__lock_wr__in_t; diff --git a/src/pcrvault/rtl/pv_reg.sv b/src/pcrvault/rtl/pv_reg.sv index d8483f2b2..02ed99447 100644 --- a/src/pcrvault/rtl/pv_reg.sv +++ b/src/pcrvault/rtl/pv_reg.sv @@ -58,7 +58,9 @@ module pv_reg ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -75,11 +77,11 @@ module pv_reg ( always_comb begin for(int i0=0; i0<32; i0++) begin - decoded_reg_strb.PCR_CTRL[i0] = cpuif_req_masked & (cpuif_addr == 'h0 + i0*'h4); + decoded_reg_strb.PCR_CTRL[i0] = cpuif_req_masked & (cpuif_addr == 12'h0 + i0*12'h4); end for(int i0=0; i0<32; i0++) begin for(int i1=0; i1<12; i1++) begin - decoded_reg_strb.PCR_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 'h600 + i0*'h30 + i1*'h4); + decoded_reg_strb.PCR_ENTRY[i0][i1] = cpuif_req_masked & (cpuif_addr == 12'h600 + i0*12'h30 + i1*12'h4); end end end @@ -90,10 +92,6 @@ module pv_reg ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -151,8 +149,10 @@ module pv_reg ( for(genvar i0=0; i0<32; i0++) begin // Field: pv_reg.PCR_CTRL[].lock always_comb begin - automatic logic [0:0] next_c = field_storage.PCR_CTRL[i0].lock.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.PCR_CTRL[i0].lock.value; + load_next_c = '0; if(decoded_reg_strb.PCR_CTRL[i0] && decoded_req_is_wr && !(hwif_in.PCR_CTRL[i0].lock.swwel)) begin // SW write next_c = (field_storage.PCR_CTRL[i0].lock.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -162,7 +162,7 @@ module pv_reg ( end always_ff @(posedge clk or negedge hwif_in.core_only_rst_b) begin if(~hwif_in.core_only_rst_b) begin - field_storage.PCR_CTRL[i0].lock.value <= 'h0; + field_storage.PCR_CTRL[i0].lock.value <= 1'h0; end else if(field_combo.PCR_CTRL[i0].lock.load_next) begin field_storage.PCR_CTRL[i0].lock.value <= field_combo.PCR_CTRL[i0].lock.next; end @@ -170,12 +170,14 @@ module pv_reg ( assign hwif_out.PCR_CTRL[i0].lock.value = field_storage.PCR_CTRL[i0].lock.value; // Field: pv_reg.PCR_CTRL[].clear always_comb begin - automatic logic [0:0] next_c = field_storage.PCR_CTRL[i0].clear.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.PCR_CTRL[i0].clear.value; + load_next_c = '0; if(decoded_reg_strb.PCR_CTRL[i0] && decoded_req_is_wr && !(hwif_in.PCR_CTRL[i0].clear.swwel)) begin // SW write next_c = (field_storage.PCR_CTRL[i0].clear.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -184,7 +186,7 @@ module pv_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.PCR_CTRL[i0].clear.value <= 'h0; + field_storage.PCR_CTRL[i0].clear.value <= 1'h0; end else if(field_combo.PCR_CTRL[i0].clear.load_next) begin field_storage.PCR_CTRL[i0].clear.value <= field_combo.PCR_CTRL[i0].clear.next; end @@ -192,8 +194,10 @@ module pv_reg ( assign hwif_out.PCR_CTRL[i0].clear.value = field_storage.PCR_CTRL[i0].clear.value; // Field: pv_reg.PCR_CTRL[].rsvd0 always_comb begin - automatic logic [0:0] next_c = field_storage.PCR_CTRL[i0].rsvd0.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.PCR_CTRL[i0].rsvd0.value; + load_next_c = '0; if(decoded_reg_strb.PCR_CTRL[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.PCR_CTRL[i0].rsvd0.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -206,7 +210,7 @@ module pv_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.PCR_CTRL[i0].rsvd0.value <= 'h0; + field_storage.PCR_CTRL[i0].rsvd0.value <= 1'h0; end else if(field_combo.PCR_CTRL[i0].rsvd0.load_next) begin field_storage.PCR_CTRL[i0].rsvd0.value <= field_combo.PCR_CTRL[i0].rsvd0.next; end @@ -214,8 +218,10 @@ module pv_reg ( assign hwif_out.PCR_CTRL[i0].rsvd0.value = field_storage.PCR_CTRL[i0].rsvd0.value; // Field: pv_reg.PCR_CTRL[].rsvd1 always_comb begin - automatic logic [4:0] next_c = field_storage.PCR_CTRL[i0].rsvd1.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.PCR_CTRL[i0].rsvd1.value; + load_next_c = '0; if(decoded_reg_strb.PCR_CTRL[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.PCR_CTRL[i0].rsvd1.value & ~decoded_wr_biten[7:3]) | (decoded_wr_data[7:3] & decoded_wr_biten[7:3]); load_next_c = '1; @@ -225,7 +231,7 @@ module pv_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.PCR_CTRL[i0].rsvd1.value <= 'h0; + field_storage.PCR_CTRL[i0].rsvd1.value <= 5'h0; end else if(field_combo.PCR_CTRL[i0].rsvd1.load_next) begin field_storage.PCR_CTRL[i0].rsvd1.value <= field_combo.PCR_CTRL[i0].rsvd1.next; end @@ -236,8 +242,10 @@ module pv_reg ( for(genvar i1=0; i1<12; i1++) begin // Field: pv_reg.PCR_ENTRY[][].data always_comb begin - automatic logic [31:0] next_c = field_storage.PCR_ENTRY[i0][i1].data.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.PCR_ENTRY[i0][i1].data.value; + load_next_c = '0; if(hwif_in.PCR_ENTRY[i0][i1].data.we) begin // HW Write - we next_c = hwif_in.PCR_ENTRY[i0][i1].data.next; load_next_c = '1; @@ -250,7 +258,7 @@ module pv_reg ( end always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin if(~hwif_in.hard_reset_b) begin - field_storage.PCR_ENTRY[i0][i1].data.value <= 'h0; + field_storage.PCR_ENTRY[i0][i1].data.value <= 32'h0; end else if(field_combo.PCR_ENTRY[i0][i1].data.load_next) begin field_storage.PCR_ENTRY[i0][i1].data.value <= field_combo.PCR_ENTRY[i0][i1].data.next; end @@ -258,13 +266,22 @@ module pv_reg ( assign hwif_out.PCR_ENTRY[i0][i1].data.value = field_storage.PCR_ENTRY[i0][i1].data.value; end end + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [416-1:0][31:0] readback_array; for(genvar i0=0; i0<32; i0++) begin @@ -293,4 +310,4 @@ module pv_reg ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; -endmodule \ No newline at end of file +endmodule diff --git a/src/pcrvault/rtl/pv_reg_pkg.sv b/src/pcrvault/rtl/pv_reg_pkg.sv index e0201b175..9ce3d28e4 100644 --- a/src/pcrvault/rtl/pv_reg_pkg.sv +++ b/src/pcrvault/rtl/pv_reg_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package pv_reg_pkg; + + localparam PV_REG_DATA_WIDTH = 32; + localparam PV_REG_MIN_ADDR_WIDTH = 12; + typedef struct packed{ logic swwel; } pv_reg__pvCtrl__lock__in_t; diff --git a/src/sha256/rtl/sha256_reg.sv b/src/sha256/rtl/sha256_reg.sv index e3cb19219..c7dc4ed99 100644 --- a/src/sha256/rtl/sha256_reg.sv +++ b/src/sha256/rtl/sha256_reg.sv @@ -58,7 +58,9 @@ module sha256_reg ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -100,38 +102,38 @@ module sha256_reg ( always_comb begin for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.SHA256_NAME[i0] = cpuif_req_masked & (cpuif_addr == 'h0 + i0*'h4); + decoded_reg_strb.SHA256_NAME[i0] = cpuif_req_masked & (cpuif_addr == 12'h0 + i0*12'h4); end for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.SHA256_VERSION[i0] = cpuif_req_masked & (cpuif_addr == 'h8 + i0*'h4); + decoded_reg_strb.SHA256_VERSION[i0] = cpuif_req_masked & (cpuif_addr == 12'h8 + i0*12'h4); end - decoded_reg_strb.SHA256_CTRL = cpuif_req_masked & (cpuif_addr == 'h10); - decoded_reg_strb.SHA256_STATUS = cpuif_req_masked & (cpuif_addr == 'h18); + decoded_reg_strb.SHA256_CTRL = cpuif_req_masked & (cpuif_addr == 12'h10); + decoded_reg_strb.SHA256_STATUS = cpuif_req_masked & (cpuif_addr == 12'h18); for(int i0=0; i0<16; i0++) begin - decoded_reg_strb.SHA256_BLOCK[i0] = cpuif_req_masked & (cpuif_addr == 'h80 + i0*'h4); + decoded_reg_strb.SHA256_BLOCK[i0] = cpuif_req_masked & (cpuif_addr == 12'h80 + i0*12'h4); end for(int i0=0; i0<8; i0++) begin - decoded_reg_strb.SHA256_DIGEST[i0] = cpuif_req_masked & (cpuif_addr == 'h100 + i0*'h4); - end - decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h800); - decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h804); - decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h808); - decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h80c); - decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h810); - decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h814); - decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h818); - decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h81c); - decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h820); - decoded_reg_strb.intr_block_rf.error0_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h900); - decoded_reg_strb.intr_block_rf.error1_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h904); - decoded_reg_strb.intr_block_rf.error2_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h908); - decoded_reg_strb.intr_block_rf.error3_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h90c); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h980); - decoded_reg_strb.intr_block_rf.error0_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha00); - decoded_reg_strb.intr_block_rf.error1_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha04); - decoded_reg_strb.intr_block_rf.error2_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha08); - decoded_reg_strb.intr_block_rf.error3_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha0c); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha10); + decoded_reg_strb.SHA256_DIGEST[i0] = cpuif_req_masked & (cpuif_addr == 12'h100 + i0*12'h4); + end + decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h800); + decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h804); + decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h808); + decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h80c); + decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h810); + decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h814); + decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h818); + decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h81c); + decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h820); + decoded_reg_strb.intr_block_rf.error0_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h900); + decoded_reg_strb.intr_block_rf.error1_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h904); + decoded_reg_strb.intr_block_rf.error2_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h908); + decoded_reg_strb.intr_block_rf.error3_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h90c); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h980); + decoded_reg_strb.intr_block_rf.error0_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha00); + decoded_reg_strb.intr_block_rf.error1_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha04); + decoded_reg_strb.intr_block_rf.error2_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha08); + decoded_reg_strb.intr_block_rf.error3_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha0c); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha10); end // Pass down signals to next stage @@ -140,10 +142,6 @@ module sha256_reg ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -514,12 +512,14 @@ module sha256_reg ( // Field: sha256_reg.SHA256_CTRL.INIT always_comb begin - automatic logic [0:0] next_c = field_storage.SHA256_CTRL.INIT.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA256_CTRL.INIT.value; + load_next_c = '0; if(decoded_reg_strb.SHA256_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA256_CTRL.INIT.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -528,7 +528,7 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA256_CTRL.INIT.value <= 'h0; + field_storage.SHA256_CTRL.INIT.value <= 1'h0; end else if(field_combo.SHA256_CTRL.INIT.load_next) begin field_storage.SHA256_CTRL.INIT.value <= field_combo.SHA256_CTRL.INIT.next; end @@ -536,12 +536,14 @@ module sha256_reg ( assign hwif_out.SHA256_CTRL.INIT.value = field_storage.SHA256_CTRL.INIT.value; // Field: sha256_reg.SHA256_CTRL.NEXT always_comb begin - automatic logic [0:0] next_c = field_storage.SHA256_CTRL.NEXT.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA256_CTRL.NEXT.value; + load_next_c = '0; if(decoded_reg_strb.SHA256_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA256_CTRL.NEXT.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -550,7 +552,7 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA256_CTRL.NEXT.value <= 'h0; + field_storage.SHA256_CTRL.NEXT.value <= 1'h0; end else if(field_combo.SHA256_CTRL.NEXT.load_next) begin field_storage.SHA256_CTRL.NEXT.value <= field_combo.SHA256_CTRL.NEXT.next; end @@ -558,8 +560,10 @@ module sha256_reg ( assign hwif_out.SHA256_CTRL.NEXT.value = field_storage.SHA256_CTRL.NEXT.value; // Field: sha256_reg.SHA256_CTRL.MODE always_comb begin - automatic logic [0:0] next_c = field_storage.SHA256_CTRL.MODE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA256_CTRL.MODE.value; + load_next_c = '0; if(decoded_reg_strb.SHA256_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA256_CTRL.MODE.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -569,7 +573,7 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA256_CTRL.MODE.value <= 'h1; + field_storage.SHA256_CTRL.MODE.value <= 1'h1; end else if(field_combo.SHA256_CTRL.MODE.load_next) begin field_storage.SHA256_CTRL.MODE.value <= field_combo.SHA256_CTRL.MODE.next; end @@ -577,12 +581,14 @@ module sha256_reg ( assign hwif_out.SHA256_CTRL.MODE.value = field_storage.SHA256_CTRL.MODE.value; // Field: sha256_reg.SHA256_CTRL.ZEROIZE always_comb begin - automatic logic [0:0] next_c = field_storage.SHA256_CTRL.ZEROIZE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA256_CTRL.ZEROIZE.value; + load_next_c = '0; if(decoded_reg_strb.SHA256_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA256_CTRL.ZEROIZE.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -591,7 +597,7 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA256_CTRL.ZEROIZE.value <= 'h0; + field_storage.SHA256_CTRL.ZEROIZE.value <= 1'h0; end else if(field_combo.SHA256_CTRL.ZEROIZE.load_next) begin field_storage.SHA256_CTRL.ZEROIZE.value <= field_combo.SHA256_CTRL.ZEROIZE.next; end @@ -600,8 +606,10 @@ module sha256_reg ( for(genvar i0=0; i0<16; i0++) begin // Field: sha256_reg.SHA256_BLOCK[].BLOCK always_comb begin - automatic logic [31:0] next_c = field_storage.SHA256_BLOCK[i0].BLOCK.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA256_BLOCK[i0].BLOCK.value; + load_next_c = '0; if(decoded_reg_strb.SHA256_BLOCK[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA256_BLOCK[i0].BLOCK.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -614,7 +622,7 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA256_BLOCK[i0].BLOCK.value <= 'h0; + field_storage.SHA256_BLOCK[i0].BLOCK.value <= 32'h0; end else if(field_combo.SHA256_BLOCK[i0].BLOCK.load_next) begin field_storage.SHA256_BLOCK[i0].BLOCK.value <= field_combo.SHA256_BLOCK[i0].BLOCK.next; end @@ -624,21 +632,23 @@ module sha256_reg ( for(genvar i0=0; i0<8; i0++) begin // Field: sha256_reg.SHA256_DIGEST[].DIGEST always_comb begin - automatic logic [31:0] next_c = field_storage.SHA256_DIGEST[i0].DIGEST.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.SHA256_DIGEST[i0].DIGEST.next; - load_next_c = '1; - end else if(hwif_in.SHA256_DIGEST[i0].DIGEST.hwclr) begin // HW Clear + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA256_DIGEST[i0].DIGEST.value; + load_next_c = '0; + if(hwif_in.SHA256_DIGEST[i0].DIGEST.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; + end else begin // HW Write + next_c = hwif_in.SHA256_DIGEST[i0].DIGEST.next; + load_next_c = '1; end field_combo.SHA256_DIGEST[i0].DIGEST.next = next_c; field_combo.SHA256_DIGEST[i0].DIGEST.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA256_DIGEST[i0].DIGEST.value <= 'h0; + field_storage.SHA256_DIGEST[i0].DIGEST.value <= 32'h0; end else if(field_combo.SHA256_DIGEST[i0].DIGEST.load_next) begin field_storage.SHA256_DIGEST[i0].DIGEST.value <= field_combo.SHA256_DIGEST[i0].DIGEST.next; end @@ -646,8 +656,10 @@ module sha256_reg ( end // Field: sha256_reg.intr_block_rf.global_intr_en_r.error_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.error_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -657,15 +669,17 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.error_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.error_en.value <= field_combo.intr_block_rf.global_intr_en_r.error_en.next; end end // Field: sha256_reg.intr_block_rf.global_intr_en_r.notif_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.notif_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -675,15 +689,17 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.notif_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= field_combo.intr_block_rf.global_intr_en_r.notif_en.next; end end // Field: sha256_reg.intr_block_rf.error_intr_en_r.error0_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error0_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -693,15 +709,17 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error0_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= field_combo.intr_block_rf.error_intr_en_r.error0_en.next; end end // Field: sha256_reg.intr_block_rf.error_intr_en_r.error1_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error1_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -711,15 +729,17 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error1_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= field_combo.intr_block_rf.error_intr_en_r.error1_en.next; end end // Field: sha256_reg.intr_block_rf.error_intr_en_r.error2_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error2_en.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -729,15 +749,17 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error2_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= field_combo.intr_block_rf.error_intr_en_r.error2_en.next; end end // Field: sha256_reg.intr_block_rf.error_intr_en_r.error3_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error3_en.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -747,15 +769,17 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error3_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= field_combo.intr_block_rf.error_intr_en_r.error3_en.next; end end // Field: sha256_reg.intr_block_rf.notif_intr_en_r.notif_cmd_done_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -765,25 +789,27 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.next; end end // Field: sha256_reg.intr_block_rf.error_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.error_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.error_global_intr_r.agg_sts.next; end @@ -792,18 +818,20 @@ module sha256_reg ( |(field_storage.intr_block_rf.error_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.error_en.value); // Field: sha256_reg.intr_block_rf.notif_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next; end @@ -812,9 +840,11 @@ module sha256_reg ( |(field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.notif_en.value); // Field: sha256_reg.intr_block_rf.error_internal_intr_r.error0_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error0_sts.hwset) begin // HW Set @@ -829,16 +859,18 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error0_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error0_sts.next; end end // Field: sha256_reg.intr_block_rf.error_internal_intr_r.error1_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error1_sts.hwset) begin // HW Set @@ -853,16 +885,18 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error1_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error1_sts.next; end end // Field: sha256_reg.intr_block_rf.error_internal_intr_r.error2_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error2_sts.hwset) begin // HW Set @@ -877,16 +911,18 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error2_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error2_sts.next; end end // Field: sha256_reg.intr_block_rf.error_internal_intr_r.error3_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error3_sts.hwset) begin // HW Set @@ -901,7 +937,7 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error3_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error3_sts.next; end @@ -913,9 +949,11 @@ module sha256_reg ( || |(field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value & field_storage.intr_block_rf.error_intr_en_r.error3_en.value); // Field: sha256_reg.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.hwset) begin // HW Set @@ -930,7 +968,7 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.next; end @@ -939,12 +977,14 @@ module sha256_reg ( |(field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value); // Field: sha256_reg.intr_block_rf.error_intr_trig_r.error0_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -953,19 +993,21 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error0_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error0_trig.next; end end // Field: sha256_reg.intr_block_rf.error_intr_trig_r.error1_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -974,19 +1016,21 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error1_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error1_trig.next; end end // Field: sha256_reg.intr_block_rf.error_intr_trig_r.error2_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -995,19 +1039,21 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error2_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error2_trig.next; end end // Field: sha256_reg.intr_block_rf.error_intr_trig_r.error3_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1016,19 +1062,21 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error3_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error3_trig.next; end end // Field: sha256_reg.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1037,31 +1085,33 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.next; end end // Field: sha256_reg.intr_block_rf.error0_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error0_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error0_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error0_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error0_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error0_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error0_intr_count_r.cnt.next = next_c; @@ -1069,31 +1119,33 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error0_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= field_combo.intr_block_rf.error0_intr_count_r.cnt.next; end end // Field: sha256_reg.intr_block_rf.error1_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error1_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error1_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error1_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error1_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error1_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error1_intr_count_r.cnt.next = next_c; @@ -1101,31 +1153,33 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error1_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= field_combo.intr_block_rf.error1_intr_count_r.cnt.next; end end // Field: sha256_reg.intr_block_rf.error2_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error2_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error2_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error2_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error2_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error2_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error2_intr_count_r.cnt.next = next_c; @@ -1133,31 +1187,33 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error2_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= field_combo.intr_block_rf.error2_intr_count_r.cnt.next; end end // Field: sha256_reg.intr_block_rf.error3_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error3_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error3_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error3_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error3_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error3_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error3_intr_count_r.cnt.next = next_c; @@ -1165,31 +1221,33 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error3_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= field_combo.intr_block_rf.error3_intr_count_r.cnt.next; end end // Field: sha256_reg.intr_block_rf.notif_cmd_done_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next = next_c; @@ -1197,15 +1255,17 @@ module sha256_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next; end end // Field: sha256_reg.intr_block_rf.error0_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; @@ -1214,27 +1274,29 @@ module sha256_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.next; end end // Field: sha256_reg.intr_block_rf.error1_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; @@ -1243,27 +1305,29 @@ module sha256_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.next; end end // Field: sha256_reg.intr_block_rf.error2_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; @@ -1272,27 +1336,29 @@ module sha256_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.next; end end // Field: sha256_reg.intr_block_rf.error3_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; @@ -1301,27 +1367,29 @@ module sha256_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.next; end end // Field: sha256_reg.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; @@ -1330,30 +1398,39 @@ module sha256_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next; end end + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [32-1:0][31:0] readback_array; for(genvar i0=0; i0<2; i0++) begin diff --git a/src/sha256/rtl/sha256_reg_pkg.sv b/src/sha256/rtl/sha256_reg_pkg.sv index a1c0c5729..3f61362c4 100644 --- a/src/sha256/rtl/sha256_reg_pkg.sv +++ b/src/sha256/rtl/sha256_reg_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package sha256_reg_pkg; + + localparam SHA256_REG_DATA_WIDTH = 32; + localparam SHA256_REG_MIN_ADDR_WIDTH = 12; + typedef struct packed{ logic [31:0] next; } sha256_reg__SHA256_NAME__NAME__in_t; @@ -50,33 +54,33 @@ package sha256_reg_pkg; typedef struct packed{ logic hwset; - } sha256_reg__error_intr_t__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t; + } sha256_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t; typedef struct packed{ logic hwset; - } sha256_reg__error_intr_t__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t; + } sha256_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t; typedef struct packed{ logic hwset; - } sha256_reg__error_intr_t__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t; + } sha256_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t; typedef struct packed{ logic hwset; - } sha256_reg__error_intr_t__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t; + } sha256_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t; typedef struct packed{ - sha256_reg__error_intr_t__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t error0_sts; - sha256_reg__error_intr_t__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t error1_sts; - sha256_reg__error_intr_t__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t error2_sts; - sha256_reg__error_intr_t__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t error3_sts; + sha256_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t error0_sts; + sha256_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t error1_sts; + sha256_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t error2_sts; + sha256_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t error3_sts; } sha256_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__in_t; typedef struct packed{ logic hwset; - } sha256_reg__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; + } sha256_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; typedef struct packed{ - sha256_reg__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; + sha256_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; } sha256_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__in_t; typedef struct packed{ diff --git a/src/sha512/rtl/sha512_reg.sv b/src/sha512/rtl/sha512_reg.sv index bd97bf079..0ad502391 100644 --- a/src/sha512/rtl/sha512_reg.sv +++ b/src/sha512/rtl/sha512_reg.sv @@ -58,7 +58,9 @@ module sha512_reg ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -108,50 +110,50 @@ module sha512_reg ( always_comb begin for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.SHA512_NAME[i0] = cpuif_req_masked & (cpuif_addr == 'h0 + i0*'h4); + decoded_reg_strb.SHA512_NAME[i0] = cpuif_req_masked & (cpuif_addr == 12'h0 + i0*12'h4); end for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.SHA512_VERSION[i0] = cpuif_req_masked & (cpuif_addr == 'h8 + i0*'h4); + decoded_reg_strb.SHA512_VERSION[i0] = cpuif_req_masked & (cpuif_addr == 12'h8 + i0*12'h4); end - decoded_reg_strb.SHA512_CTRL = cpuif_req_masked & (cpuif_addr == 'h10); - decoded_reg_strb.SHA512_STATUS = cpuif_req_masked & (cpuif_addr == 'h18); + decoded_reg_strb.SHA512_CTRL = cpuif_req_masked & (cpuif_addr == 12'h10); + decoded_reg_strb.SHA512_STATUS = cpuif_req_masked & (cpuif_addr == 12'h18); for(int i0=0; i0<32; i0++) begin - decoded_reg_strb.SHA512_BLOCK[i0] = cpuif_req_masked & (cpuif_addr == 'h80 + i0*'h4); + decoded_reg_strb.SHA512_BLOCK[i0] = cpuif_req_masked & (cpuif_addr == 12'h80 + i0*12'h4); end for(int i0=0; i0<16; i0++) begin - decoded_reg_strb.SHA512_DIGEST[i0] = cpuif_req_masked & (cpuif_addr == 'h100 + i0*'h4); + decoded_reg_strb.SHA512_DIGEST[i0] = cpuif_req_masked & (cpuif_addr == 12'h100 + i0*12'h4); end - decoded_reg_strb.SHA512_VAULT_RD_CTRL = cpuif_req_masked & (cpuif_addr == 'h600); - decoded_reg_strb.SHA512_VAULT_RD_STATUS = cpuif_req_masked & (cpuif_addr == 'h604); - decoded_reg_strb.SHA512_KV_WR_CTRL = cpuif_req_masked & (cpuif_addr == 'h608); - decoded_reg_strb.SHA512_KV_WR_STATUS = cpuif_req_masked & (cpuif_addr == 'h60c); + decoded_reg_strb.SHA512_VAULT_RD_CTRL = cpuif_req_masked & (cpuif_addr == 12'h600); + decoded_reg_strb.SHA512_VAULT_RD_STATUS = cpuif_req_masked & (cpuif_addr == 12'h604); + decoded_reg_strb.SHA512_KV_WR_CTRL = cpuif_req_masked & (cpuif_addr == 12'h608); + decoded_reg_strb.SHA512_KV_WR_STATUS = cpuif_req_masked & (cpuif_addr == 12'h60c); for(int i0=0; i0<8; i0++) begin - decoded_reg_strb.SHA512_GEN_PCR_HASH_NONCE[i0] = cpuif_req_masked & (cpuif_addr == 'h610 + i0*'h4); + decoded_reg_strb.SHA512_GEN_PCR_HASH_NONCE[i0] = cpuif_req_masked & (cpuif_addr == 12'h610 + i0*12'h4); end - decoded_reg_strb.SHA512_GEN_PCR_HASH_CTRL = cpuif_req_masked & (cpuif_addr == 'h630); - decoded_reg_strb.SHA512_GEN_PCR_HASH_STATUS = cpuif_req_masked & (cpuif_addr == 'h634); + decoded_reg_strb.SHA512_GEN_PCR_HASH_CTRL = cpuif_req_masked & (cpuif_addr == 12'h630); + decoded_reg_strb.SHA512_GEN_PCR_HASH_STATUS = cpuif_req_masked & (cpuif_addr == 12'h634); for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.SHA512_GEN_PCR_HASH_DIGEST[i0] = cpuif_req_masked & (cpuif_addr == 'h638 + i0*'h4); - end - decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h800); - decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h804); - decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h808); - decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h80c); - decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h810); - decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h814); - decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h818); - decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h81c); - decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h820); - decoded_reg_strb.intr_block_rf.error0_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h900); - decoded_reg_strb.intr_block_rf.error1_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h904); - decoded_reg_strb.intr_block_rf.error2_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h908); - decoded_reg_strb.intr_block_rf.error3_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h90c); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h980); - decoded_reg_strb.intr_block_rf.error0_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha00); - decoded_reg_strb.intr_block_rf.error1_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha04); - decoded_reg_strb.intr_block_rf.error2_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha08); - decoded_reg_strb.intr_block_rf.error3_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha0c); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha10); + decoded_reg_strb.SHA512_GEN_PCR_HASH_DIGEST[i0] = cpuif_req_masked & (cpuif_addr == 12'h638 + i0*12'h4); + end + decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h800); + decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h804); + decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h808); + decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h80c); + decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h810); + decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h814); + decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h818); + decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h81c); + decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h820); + decoded_reg_strb.intr_block_rf.error0_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h900); + decoded_reg_strb.intr_block_rf.error1_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h904); + decoded_reg_strb.intr_block_rf.error2_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h908); + decoded_reg_strb.intr_block_rf.error3_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h90c); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h980); + decoded_reg_strb.intr_block_rf.error0_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha00); + decoded_reg_strb.intr_block_rf.error1_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha04); + decoded_reg_strb.intr_block_rf.error2_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha08); + decoded_reg_strb.intr_block_rf.error3_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha0c); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha10); end // Pass down signals to next stage @@ -160,10 +162,6 @@ module sha512_reg ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -699,12 +697,14 @@ module sha512_reg ( // Field: sha512_reg.SHA512_CTRL.INIT always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_CTRL.INIT.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_CTRL.INIT.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_CTRL.INIT.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -713,7 +713,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_CTRL.INIT.value <= 'h0; + field_storage.SHA512_CTRL.INIT.value <= 1'h0; end else if(field_combo.SHA512_CTRL.INIT.load_next) begin field_storage.SHA512_CTRL.INIT.value <= field_combo.SHA512_CTRL.INIT.next; end @@ -721,12 +721,14 @@ module sha512_reg ( assign hwif_out.SHA512_CTRL.INIT.value = field_storage.SHA512_CTRL.INIT.value; // Field: sha512_reg.SHA512_CTRL.NEXT always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_CTRL.NEXT.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_CTRL.NEXT.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_CTRL.NEXT.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -735,7 +737,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_CTRL.NEXT.value <= 'h0; + field_storage.SHA512_CTRL.NEXT.value <= 1'h0; end else if(field_combo.SHA512_CTRL.NEXT.load_next) begin field_storage.SHA512_CTRL.NEXT.value <= field_combo.SHA512_CTRL.NEXT.next; end @@ -743,8 +745,10 @@ module sha512_reg ( assign hwif_out.SHA512_CTRL.NEXT.value = field_storage.SHA512_CTRL.NEXT.value; // Field: sha512_reg.SHA512_CTRL.MODE always_comb begin - automatic logic [1:0] next_c = field_storage.SHA512_CTRL.MODE.value; - automatic logic load_next_c = '0; + automatic logic [1:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_CTRL.MODE.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_CTRL.MODE.value & ~decoded_wr_biten[3:2]) | (decoded_wr_data[3:2] & decoded_wr_biten[3:2]); load_next_c = '1; @@ -754,7 +758,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_CTRL.MODE.value <= 'h2; + field_storage.SHA512_CTRL.MODE.value <= 2'h2; end else if(field_combo.SHA512_CTRL.MODE.load_next) begin field_storage.SHA512_CTRL.MODE.value <= field_combo.SHA512_CTRL.MODE.next; end @@ -762,12 +766,14 @@ module sha512_reg ( assign hwif_out.SHA512_CTRL.MODE.value = field_storage.SHA512_CTRL.MODE.value; // Field: sha512_reg.SHA512_CTRL.ZEROIZE always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_CTRL.ZEROIZE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_CTRL.ZEROIZE.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_CTRL.ZEROIZE.value & ~decoded_wr_biten[4:4]) | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -776,7 +782,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_CTRL.ZEROIZE.value <= 'h0; + field_storage.SHA512_CTRL.ZEROIZE.value <= 1'h0; end else if(field_combo.SHA512_CTRL.ZEROIZE.load_next) begin field_storage.SHA512_CTRL.ZEROIZE.value <= field_combo.SHA512_CTRL.ZEROIZE.next; end @@ -784,8 +790,10 @@ module sha512_reg ( assign hwif_out.SHA512_CTRL.ZEROIZE.value = field_storage.SHA512_CTRL.ZEROIZE.value; // Field: sha512_reg.SHA512_CTRL.LAST always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_CTRL.LAST.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_CTRL.LAST.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_CTRL.LAST.value & ~decoded_wr_biten[5:5]) | (decoded_wr_data[5:5] & decoded_wr_biten[5:5]); load_next_c = '1; @@ -798,7 +806,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_CTRL.LAST.value <= 'h0; + field_storage.SHA512_CTRL.LAST.value <= 1'h0; end else if(field_combo.SHA512_CTRL.LAST.load_next) begin field_storage.SHA512_CTRL.LAST.value <= field_combo.SHA512_CTRL.LAST.next; end @@ -807,8 +815,10 @@ module sha512_reg ( for(genvar i0=0; i0<32; i0++) begin // Field: sha512_reg.SHA512_BLOCK[].BLOCK always_comb begin - automatic logic [31:0] next_c = field_storage.SHA512_BLOCK[i0].BLOCK.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_BLOCK[i0].BLOCK.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_BLOCK[i0] && decoded_req_is_wr && !(hwif_in.SHA512_BLOCK[i0].BLOCK.swwel)) begin // SW write next_c = (field_storage.SHA512_BLOCK[i0].BLOCK.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -824,7 +834,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_BLOCK[i0].BLOCK.value <= 'h0; + field_storage.SHA512_BLOCK[i0].BLOCK.value <= 32'h0; end else if(field_combo.SHA512_BLOCK[i0].BLOCK.load_next) begin field_storage.SHA512_BLOCK[i0].BLOCK.value <= field_combo.SHA512_BLOCK[i0].BLOCK.next; end @@ -834,21 +844,23 @@ module sha512_reg ( for(genvar i0=0; i0<16; i0++) begin // Field: sha512_reg.SHA512_DIGEST[].DIGEST always_comb begin - automatic logic [31:0] next_c = field_storage.SHA512_DIGEST[i0].DIGEST.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.SHA512_DIGEST[i0].DIGEST.next; - load_next_c = '1; - end else if(hwif_in.SHA512_DIGEST[i0].DIGEST.hwclr) begin // HW Clear + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_DIGEST[i0].DIGEST.value; + load_next_c = '0; + if(hwif_in.SHA512_DIGEST[i0].DIGEST.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; + end else begin // HW Write + next_c = hwif_in.SHA512_DIGEST[i0].DIGEST.next; + load_next_c = '1; end field_combo.SHA512_DIGEST[i0].DIGEST.next = next_c; field_combo.SHA512_DIGEST[i0].DIGEST.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_DIGEST[i0].DIGEST.value <= 'h0; + field_storage.SHA512_DIGEST[i0].DIGEST.value <= 32'h0; end else if(field_combo.SHA512_DIGEST[i0].DIGEST.load_next) begin field_storage.SHA512_DIGEST[i0].DIGEST.value <= field_combo.SHA512_DIGEST[i0].DIGEST.next; end @@ -856,8 +868,10 @@ module sha512_reg ( end // Field: sha512_reg.SHA512_VAULT_RD_CTRL.read_en always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_VAULT_RD_CTRL.read_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_VAULT_RD_CTRL.read_en.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_VAULT_RD_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_VAULT_RD_CTRL.read_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -870,7 +884,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_VAULT_RD_CTRL.read_en.value <= 'h0; + field_storage.SHA512_VAULT_RD_CTRL.read_en.value <= 1'h0; end else if(field_combo.SHA512_VAULT_RD_CTRL.read_en.load_next) begin field_storage.SHA512_VAULT_RD_CTRL.read_en.value <= field_combo.SHA512_VAULT_RD_CTRL.read_en.next; end @@ -878,8 +892,10 @@ module sha512_reg ( assign hwif_out.SHA512_VAULT_RD_CTRL.read_en.value = field_storage.SHA512_VAULT_RD_CTRL.read_en.value; // Field: sha512_reg.SHA512_VAULT_RD_CTRL.read_entry always_comb begin - automatic logic [4:0] next_c = field_storage.SHA512_VAULT_RD_CTRL.read_entry.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_VAULT_RD_CTRL.read_entry.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_VAULT_RD_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_VAULT_RD_CTRL.read_entry.value & ~decoded_wr_biten[5:1]) | (decoded_wr_data[5:1] & decoded_wr_biten[5:1]); load_next_c = '1; @@ -889,7 +905,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_VAULT_RD_CTRL.read_entry.value <= 'h0; + field_storage.SHA512_VAULT_RD_CTRL.read_entry.value <= 5'h0; end else if(field_combo.SHA512_VAULT_RD_CTRL.read_entry.load_next) begin field_storage.SHA512_VAULT_RD_CTRL.read_entry.value <= field_combo.SHA512_VAULT_RD_CTRL.read_entry.next; end @@ -897,8 +913,10 @@ module sha512_reg ( assign hwif_out.SHA512_VAULT_RD_CTRL.read_entry.value = field_storage.SHA512_VAULT_RD_CTRL.read_entry.value; // Field: sha512_reg.SHA512_VAULT_RD_CTRL.pcr_hash_extend always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_VAULT_RD_CTRL.pcr_hash_extend.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_VAULT_RD_CTRL.pcr_hash_extend.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_VAULT_RD_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_VAULT_RD_CTRL.pcr_hash_extend.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; @@ -908,7 +926,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_VAULT_RD_CTRL.pcr_hash_extend.value <= 'h0; + field_storage.SHA512_VAULT_RD_CTRL.pcr_hash_extend.value <= 1'h0; end else if(field_combo.SHA512_VAULT_RD_CTRL.pcr_hash_extend.load_next) begin field_storage.SHA512_VAULT_RD_CTRL.pcr_hash_extend.value <= field_combo.SHA512_VAULT_RD_CTRL.pcr_hash_extend.next; end @@ -916,8 +934,10 @@ module sha512_reg ( assign hwif_out.SHA512_VAULT_RD_CTRL.pcr_hash_extend.value = field_storage.SHA512_VAULT_RD_CTRL.pcr_hash_extend.value; // Field: sha512_reg.SHA512_VAULT_RD_CTRL.rsvd always_comb begin - automatic logic [24:0] next_c = field_storage.SHA512_VAULT_RD_CTRL.rsvd.value; - automatic logic load_next_c = '0; + automatic logic [24:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_VAULT_RD_CTRL.rsvd.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_VAULT_RD_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_VAULT_RD_CTRL.rsvd.value & ~decoded_wr_biten[31:7]) | (decoded_wr_data[31:7] & decoded_wr_biten[31:7]); load_next_c = '1; @@ -927,7 +947,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_VAULT_RD_CTRL.rsvd.value <= 'h0; + field_storage.SHA512_VAULT_RD_CTRL.rsvd.value <= 25'h0; end else if(field_combo.SHA512_VAULT_RD_CTRL.rsvd.load_next) begin field_storage.SHA512_VAULT_RD_CTRL.rsvd.value <= field_combo.SHA512_VAULT_RD_CTRL.rsvd.next; end @@ -935,8 +955,10 @@ module sha512_reg ( assign hwif_out.SHA512_VAULT_RD_CTRL.rsvd.value = field_storage.SHA512_VAULT_RD_CTRL.rsvd.value; // Field: sha512_reg.SHA512_VAULT_RD_STATUS.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_VAULT_RD_STATUS.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_VAULT_RD_STATUS.VALID.value; + load_next_c = '0; if(hwif_in.SHA512_VAULT_RD_STATUS.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -949,15 +971,17 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_VAULT_RD_STATUS.VALID.value <= 'h0; + field_storage.SHA512_VAULT_RD_STATUS.VALID.value <= 1'h0; end else if(field_combo.SHA512_VAULT_RD_STATUS.VALID.load_next) begin field_storage.SHA512_VAULT_RD_STATUS.VALID.value <= field_combo.SHA512_VAULT_RD_STATUS.VALID.next; end end // Field: sha512_reg.SHA512_KV_WR_CTRL.write_en always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_KV_WR_CTRL.write_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_KV_WR_CTRL.write_en.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_KV_WR_CTRL.write_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -970,7 +994,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_KV_WR_CTRL.write_en.value <= 'h0; + field_storage.SHA512_KV_WR_CTRL.write_en.value <= 1'h0; end else if(field_combo.SHA512_KV_WR_CTRL.write_en.load_next) begin field_storage.SHA512_KV_WR_CTRL.write_en.value <= field_combo.SHA512_KV_WR_CTRL.write_en.next; end @@ -978,8 +1002,10 @@ module sha512_reg ( assign hwif_out.SHA512_KV_WR_CTRL.write_en.value = field_storage.SHA512_KV_WR_CTRL.write_en.value; // Field: sha512_reg.SHA512_KV_WR_CTRL.write_entry always_comb begin - automatic logic [4:0] next_c = field_storage.SHA512_KV_WR_CTRL.write_entry.value; - automatic logic load_next_c = '0; + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_KV_WR_CTRL.write_entry.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_KV_WR_CTRL.write_entry.value & ~decoded_wr_biten[5:1]) | (decoded_wr_data[5:1] & decoded_wr_biten[5:1]); load_next_c = '1; @@ -989,7 +1015,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_KV_WR_CTRL.write_entry.value <= 'h0; + field_storage.SHA512_KV_WR_CTRL.write_entry.value <= 5'h0; end else if(field_combo.SHA512_KV_WR_CTRL.write_entry.load_next) begin field_storage.SHA512_KV_WR_CTRL.write_entry.value <= field_combo.SHA512_KV_WR_CTRL.write_entry.next; end @@ -997,8 +1023,10 @@ module sha512_reg ( assign hwif_out.SHA512_KV_WR_CTRL.write_entry.value = field_storage.SHA512_KV_WR_CTRL.write_entry.value; // Field: sha512_reg.SHA512_KV_WR_CTRL.hmac_key_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_KV_WR_CTRL.hmac_key_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_KV_WR_CTRL.hmac_key_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_KV_WR_CTRL.hmac_key_dest_valid.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; @@ -1008,7 +1036,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_KV_WR_CTRL.hmac_key_dest_valid.value <= 'h0; + field_storage.SHA512_KV_WR_CTRL.hmac_key_dest_valid.value <= 1'h0; end else if(field_combo.SHA512_KV_WR_CTRL.hmac_key_dest_valid.load_next) begin field_storage.SHA512_KV_WR_CTRL.hmac_key_dest_valid.value <= field_combo.SHA512_KV_WR_CTRL.hmac_key_dest_valid.next; end @@ -1016,8 +1044,10 @@ module sha512_reg ( assign hwif_out.SHA512_KV_WR_CTRL.hmac_key_dest_valid.value = field_storage.SHA512_KV_WR_CTRL.hmac_key_dest_valid.value; // Field: sha512_reg.SHA512_KV_WR_CTRL.hmac_block_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_KV_WR_CTRL.hmac_block_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_KV_WR_CTRL.hmac_block_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_KV_WR_CTRL.hmac_block_dest_valid.value & ~decoded_wr_biten[7:7]) | (decoded_wr_data[7:7] & decoded_wr_biten[7:7]); load_next_c = '1; @@ -1027,7 +1057,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_KV_WR_CTRL.hmac_block_dest_valid.value <= 'h0; + field_storage.SHA512_KV_WR_CTRL.hmac_block_dest_valid.value <= 1'h0; end else if(field_combo.SHA512_KV_WR_CTRL.hmac_block_dest_valid.load_next) begin field_storage.SHA512_KV_WR_CTRL.hmac_block_dest_valid.value <= field_combo.SHA512_KV_WR_CTRL.hmac_block_dest_valid.next; end @@ -1035,8 +1065,10 @@ module sha512_reg ( assign hwif_out.SHA512_KV_WR_CTRL.hmac_block_dest_valid.value = field_storage.SHA512_KV_WR_CTRL.hmac_block_dest_valid.value; // Field: sha512_reg.SHA512_KV_WR_CTRL.sha_block_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_KV_WR_CTRL.sha_block_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_KV_WR_CTRL.sha_block_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_KV_WR_CTRL.sha_block_dest_valid.value & ~decoded_wr_biten[8:8]) | (decoded_wr_data[8:8] & decoded_wr_biten[8:8]); load_next_c = '1; @@ -1046,7 +1078,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_KV_WR_CTRL.sha_block_dest_valid.value <= 'h0; + field_storage.SHA512_KV_WR_CTRL.sha_block_dest_valid.value <= 1'h0; end else if(field_combo.SHA512_KV_WR_CTRL.sha_block_dest_valid.load_next) begin field_storage.SHA512_KV_WR_CTRL.sha_block_dest_valid.value <= field_combo.SHA512_KV_WR_CTRL.sha_block_dest_valid.next; end @@ -1054,8 +1086,10 @@ module sha512_reg ( assign hwif_out.SHA512_KV_WR_CTRL.sha_block_dest_valid.value = field_storage.SHA512_KV_WR_CTRL.sha_block_dest_valid.value; // Field: sha512_reg.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.value & ~decoded_wr_biten[9:9]) | (decoded_wr_data[9:9] & decoded_wr_biten[9:9]); load_next_c = '1; @@ -1065,7 +1099,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.value <= 'h0; + field_storage.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.value <= 1'h0; end else if(field_combo.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.load_next) begin field_storage.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.value <= field_combo.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.next; end @@ -1073,8 +1107,10 @@ module sha512_reg ( assign hwif_out.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.value = field_storage.SHA512_KV_WR_CTRL.ecc_pkey_dest_valid.value; // Field: sha512_reg.SHA512_KV_WR_CTRL.ecc_seed_dest_valid always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.value & ~decoded_wr_biten[10:10]) | (decoded_wr_data[10:10] & decoded_wr_biten[10:10]); load_next_c = '1; @@ -1084,7 +1120,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.value <= 'h0; + field_storage.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.value <= 1'h0; end else if(field_combo.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.load_next) begin field_storage.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.value <= field_combo.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.next; end @@ -1092,8 +1128,10 @@ module sha512_reg ( assign hwif_out.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.value = field_storage.SHA512_KV_WR_CTRL.ecc_seed_dest_valid.value; // Field: sha512_reg.SHA512_KV_WR_CTRL.rsvd always_comb begin - automatic logic [20:0] next_c = field_storage.SHA512_KV_WR_CTRL.rsvd.value; - automatic logic load_next_c = '0; + automatic logic [20:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_KV_WR_CTRL.rsvd.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_KV_WR_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_KV_WR_CTRL.rsvd.value & ~decoded_wr_biten[31:11]) | (decoded_wr_data[31:11] & decoded_wr_biten[31:11]); load_next_c = '1; @@ -1103,7 +1141,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_KV_WR_CTRL.rsvd.value <= 'h0; + field_storage.SHA512_KV_WR_CTRL.rsvd.value <= 21'h0; end else if(field_combo.SHA512_KV_WR_CTRL.rsvd.load_next) begin field_storage.SHA512_KV_WR_CTRL.rsvd.value <= field_combo.SHA512_KV_WR_CTRL.rsvd.next; end @@ -1111,8 +1149,10 @@ module sha512_reg ( assign hwif_out.SHA512_KV_WR_CTRL.rsvd.value = field_storage.SHA512_KV_WR_CTRL.rsvd.value; // Field: sha512_reg.SHA512_KV_WR_STATUS.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_KV_WR_STATUS.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_KV_WR_STATUS.VALID.value; + load_next_c = '0; if(hwif_in.SHA512_KV_WR_STATUS.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -1125,7 +1165,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_KV_WR_STATUS.VALID.value <= 'h0; + field_storage.SHA512_KV_WR_STATUS.VALID.value <= 1'h0; end else if(field_combo.SHA512_KV_WR_STATUS.VALID.load_next) begin field_storage.SHA512_KV_WR_STATUS.VALID.value <= field_combo.SHA512_KV_WR_STATUS.VALID.next; end @@ -1133,8 +1173,10 @@ module sha512_reg ( for(genvar i0=0; i0<8; i0++) begin // Field: sha512_reg.SHA512_GEN_PCR_HASH_NONCE[].NONCE always_comb begin - automatic logic [31:0] next_c = field_storage.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_GEN_PCR_HASH_NONCE[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -1144,7 +1186,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.value <= 'h0; + field_storage.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.value <= 32'h0; end else if(field_combo.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.load_next) begin field_storage.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.value <= field_combo.SHA512_GEN_PCR_HASH_NONCE[i0].NONCE.next; end @@ -1153,12 +1195,14 @@ module sha512_reg ( end // Field: sha512_reg.SHA512_GEN_PCR_HASH_CTRL.START always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_GEN_PCR_HASH_CTRL.START.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_GEN_PCR_HASH_CTRL.START.value; + load_next_c = '0; if(decoded_reg_strb.SHA512_GEN_PCR_HASH_CTRL && decoded_req_is_wr) begin // SW write next_c = (field_storage.SHA512_GEN_PCR_HASH_CTRL.START.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1167,7 +1211,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_GEN_PCR_HASH_CTRL.START.value <= 'h0; + field_storage.SHA512_GEN_PCR_HASH_CTRL.START.value <= 1'h0; end else if(field_combo.SHA512_GEN_PCR_HASH_CTRL.START.load_next) begin field_storage.SHA512_GEN_PCR_HASH_CTRL.START.value <= field_combo.SHA512_GEN_PCR_HASH_CTRL.START.next; end @@ -1175,8 +1219,10 @@ module sha512_reg ( assign hwif_out.SHA512_GEN_PCR_HASH_CTRL.START.value = field_storage.SHA512_GEN_PCR_HASH_CTRL.START.value; // Field: sha512_reg.SHA512_GEN_PCR_HASH_STATUS.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.SHA512_GEN_PCR_HASH_STATUS.VALID.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_GEN_PCR_HASH_STATUS.VALID.value; + load_next_c = '0; if(hwif_in.SHA512_GEN_PCR_HASH_STATUS.VALID.hwset) begin // HW Set next_c = '1; load_next_c = '1; @@ -1189,7 +1235,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_GEN_PCR_HASH_STATUS.VALID.value <= 'h0; + field_storage.SHA512_GEN_PCR_HASH_STATUS.VALID.value <= 1'h0; end else if(field_combo.SHA512_GEN_PCR_HASH_STATUS.VALID.load_next) begin field_storage.SHA512_GEN_PCR_HASH_STATUS.VALID.value <= field_combo.SHA512_GEN_PCR_HASH_STATUS.VALID.next; end @@ -1197,21 +1243,23 @@ module sha512_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: sha512_reg.SHA512_GEN_PCR_HASH_DIGEST[].DIGEST always_comb begin - automatic logic [31:0] next_c = field_storage.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.next; - load_next_c = '1; - end else if(hwif_in.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.hwclr) begin // HW Clear + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.value; + load_next_c = '0; + if(hwif_in.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; + end else begin // HW Write + next_c = hwif_in.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.next; + load_next_c = '1; end field_combo.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.next = next_c; field_combo.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.value <= 'h0; + field_storage.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.value <= 32'h0; end else if(field_combo.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.load_next) begin field_storage.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.value <= field_combo.SHA512_GEN_PCR_HASH_DIGEST[i0].DIGEST.next; end @@ -1219,8 +1267,10 @@ module sha512_reg ( end // Field: sha512_reg.intr_block_rf.global_intr_en_r.error_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.error_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1230,15 +1280,17 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.error_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.error_en.value <= field_combo.intr_block_rf.global_intr_en_r.error_en.next; end end // Field: sha512_reg.intr_block_rf.global_intr_en_r.notif_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.notif_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -1248,15 +1300,17 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.notif_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= field_combo.intr_block_rf.global_intr_en_r.notif_en.next; end end // Field: sha512_reg.intr_block_rf.error_intr_en_r.error0_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error0_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1266,15 +1320,17 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error0_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= field_combo.intr_block_rf.error_intr_en_r.error0_en.next; end end // Field: sha512_reg.intr_block_rf.error_intr_en_r.error1_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error1_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -1284,15 +1340,17 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error1_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= field_combo.intr_block_rf.error_intr_en_r.error1_en.next; end end // Field: sha512_reg.intr_block_rf.error_intr_en_r.error2_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error2_en.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -1302,15 +1360,17 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error2_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= field_combo.intr_block_rf.error_intr_en_r.error2_en.next; end end // Field: sha512_reg.intr_block_rf.error_intr_en_r.error3_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error3_en.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -1320,15 +1380,17 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error3_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= field_combo.intr_block_rf.error_intr_en_r.error3_en.next; end end // Field: sha512_reg.intr_block_rf.notif_intr_en_r.notif_cmd_done_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1338,25 +1400,27 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.next; end end // Field: sha512_reg.intr_block_rf.error_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.error_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.error_global_intr_r.agg_sts.next; end @@ -1365,18 +1429,20 @@ module sha512_reg ( |(field_storage.intr_block_rf.error_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.error_en.value); // Field: sha512_reg.intr_block_rf.notif_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next; end @@ -1385,9 +1451,11 @@ module sha512_reg ( |(field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.notif_en.value); // Field: sha512_reg.intr_block_rf.error_internal_intr_r.error0_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error0_sts.hwset) begin // HW Set @@ -1402,16 +1470,18 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error0_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error0_sts.next; end end // Field: sha512_reg.intr_block_rf.error_internal_intr_r.error1_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error1_sts.hwset) begin // HW Set @@ -1426,16 +1496,18 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error1_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error1_sts.next; end end // Field: sha512_reg.intr_block_rf.error_internal_intr_r.error2_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error2_sts.hwset) begin // HW Set @@ -1450,16 +1522,18 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error2_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error2_sts.next; end end // Field: sha512_reg.intr_block_rf.error_internal_intr_r.error3_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error3_sts.hwset) begin // HW Set @@ -1474,7 +1548,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error3_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error3_sts.next; end @@ -1486,9 +1560,11 @@ module sha512_reg ( || |(field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value & field_storage.intr_block_rf.error_intr_en_r.error3_en.value); // Field: sha512_reg.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.hwset) begin // HW Set @@ -1503,7 +1579,7 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.next; end @@ -1512,12 +1588,14 @@ module sha512_reg ( |(field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value); // Field: sha512_reg.intr_block_rf.error_intr_trig_r.error0_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1526,19 +1604,21 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error0_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error0_trig.next; end end // Field: sha512_reg.intr_block_rf.error_intr_trig_r.error1_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1547,19 +1627,21 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error1_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error1_trig.next; end end // Field: sha512_reg.intr_block_rf.error_intr_trig_r.error2_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1568,19 +1650,21 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error2_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error2_trig.next; end end // Field: sha512_reg.intr_block_rf.error_intr_trig_r.error3_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1589,19 +1673,21 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error3_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error3_trig.next; end end // Field: sha512_reg.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1610,31 +1696,33 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.next; end end // Field: sha512_reg.intr_block_rf.error0_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error0_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error0_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error0_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error0_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error0_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error0_intr_count_r.cnt.next = next_c; @@ -1642,31 +1730,33 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error0_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= field_combo.intr_block_rf.error0_intr_count_r.cnt.next; end end // Field: sha512_reg.intr_block_rf.error1_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error1_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error1_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error1_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error1_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error1_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error1_intr_count_r.cnt.next = next_c; @@ -1674,31 +1764,33 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error1_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= field_combo.intr_block_rf.error1_intr_count_r.cnt.next; end end // Field: sha512_reg.intr_block_rf.error2_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error2_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error2_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error2_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error2_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error2_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error2_intr_count_r.cnt.next = next_c; @@ -1706,31 +1798,33 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error2_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= field_combo.intr_block_rf.error2_intr_count_r.cnt.next; end end // Field: sha512_reg.intr_block_rf.error3_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error3_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error3_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error3_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error3_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error3_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error3_intr_count_r.cnt.next = next_c; @@ -1738,31 +1832,33 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.error_reset_b) begin if(~hwif_in.error_reset_b) begin - field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error3_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= field_combo.intr_block_rf.error3_intr_count_r.cnt.next; end end // Field: sha512_reg.intr_block_rf.notif_cmd_done_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r && decoded_req_is_wr) begin // SW write next_c = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next = next_c; @@ -1770,15 +1866,17 @@ module sha512_reg ( end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next; end end // Field: sha512_reg.intr_block_rf.error0_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; @@ -1787,27 +1885,29 @@ module sha512_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.next; end end // Field: sha512_reg.intr_block_rf.error1_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; @@ -1816,27 +1916,29 @@ module sha512_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.next; end end // Field: sha512_reg.intr_block_rf.error2_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; @@ -1845,27 +1947,29 @@ module sha512_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.next; end end // Field: sha512_reg.intr_block_rf.error3_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; @@ -1874,27 +1978,29 @@ module sha512_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.next; end end // Field: sha512_reg.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; @@ -1903,30 +2009,39 @@ module sha512_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.reset_b) begin if(~hwif_in.reset_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next; end end + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [57-1:0][31:0] readback_array; for(genvar i0=0; i0<2; i0++) begin @@ -2024,4 +2139,4 @@ module sha512_reg ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; -endmodule \ No newline at end of file +endmodule diff --git a/src/sha512/rtl/sha512_reg_pkg.sv b/src/sha512/rtl/sha512_reg_pkg.sv index 6d2cfe3a6..a4a0e0848 100644 --- a/src/sha512/rtl/sha512_reg_pkg.sv +++ b/src/sha512/rtl/sha512_reg_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package sha512_reg_pkg; + + localparam SHA512_REG_DATA_WIDTH = 32; + localparam SHA512_REG_MIN_ADDR_WIDTH = 12; + typedef struct packed{ logic [31:0] next; } sha512_reg__SHA512_NAME__NAME__in_t; @@ -65,7 +69,7 @@ package sha512_reg_pkg; typedef struct packed{ kv_read_ctrl_reg__read_en__in_t read_en; - } __kv_read_ctrl_reg__in_t; + } kv_read_ctrl_reg__in_t; typedef struct packed{ logic next; @@ -84,7 +88,7 @@ package sha512_reg_pkg; kv_status_reg__READY__in_t READY; kv_status_reg__VALID__in_t VALID; kv_status_reg__ERROR__in_t ERROR; - } __kv_status_reg__in_t; + } kv_status_reg__in_t; typedef struct packed{ logic hwclr; @@ -92,7 +96,7 @@ package sha512_reg_pkg; typedef struct packed{ kv_write_ctrl_reg__write_en__in_t write_en; - } __kv_write_ctrl_reg__in_t; + } kv_write_ctrl_reg__in_t; typedef struct packed{ logic next; @@ -119,33 +123,33 @@ package sha512_reg_pkg; typedef struct packed{ logic hwset; - } sha512_reg__error_intr_t__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t; + } sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t; typedef struct packed{ logic hwset; - } sha512_reg__error_intr_t__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t; + } sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t; typedef struct packed{ logic hwset; - } sha512_reg__error_intr_t__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t; + } sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t; typedef struct packed{ logic hwset; - } sha512_reg__error_intr_t__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t; + } sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t; typedef struct packed{ - sha512_reg__error_intr_t__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t error0_sts; - sha512_reg__error_intr_t__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t error1_sts; - sha512_reg__error_intr_t__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t error2_sts; - sha512_reg__error_intr_t__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t error3_sts; + sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error0_sts_enable_528ccada_next_b1018582_resetsignal_939e99d4__in_t error0_sts; + sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error1_sts_enable_938cafef_next_f460eb81_resetsignal_939e99d4__in_t error1_sts; + sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_939e99d4__in_t error2_sts; + sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_939e99d4__in_t error3_sts; } sha512_reg__error_intr_t_error0_sts_28545624_error1_sts_40e0d3e1_error2_sts_b1cf2205_error3_sts_74a35378__in_t; typedef struct packed{ logic hwset; - } sha512_reg__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; + } sha512_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; typedef struct packed{ - sha512_reg__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; + sha512_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; } sha512_reg__notif_intr_t_notif_cmd_done_sts_1c68637e__in_t; typedef struct packed{ @@ -162,10 +166,10 @@ package sha512_reg_pkg; sha512_reg__SHA512_STATUS__in_t SHA512_STATUS; sha512_reg__SHA512_BLOCK__in_t [32-1:0]SHA512_BLOCK; sha512_reg__SHA512_DIGEST__in_t [16-1:0]SHA512_DIGEST; - __kv_read_ctrl_reg__in_t SHA512_VAULT_RD_CTRL; - __kv_status_reg__in_t SHA512_VAULT_RD_STATUS; - __kv_write_ctrl_reg__in_t SHA512_KV_WR_CTRL; - __kv_status_reg__in_t SHA512_KV_WR_STATUS; + kv_read_ctrl_reg__in_t SHA512_VAULT_RD_CTRL; + kv_status_reg__in_t SHA512_VAULT_RD_STATUS; + kv_write_ctrl_reg__in_t SHA512_KV_WR_CTRL; + kv_status_reg__in_t SHA512_KV_WR_STATUS; sha512_reg__SHA512_GEN_PCR_HASH_STATUS__in_t SHA512_GEN_PCR_HASH_STATUS; sha512_reg__SHA512_GEN_PCR_HASH_DIGEST__in_t [12-1:0]SHA512_GEN_PCR_HASH_DIGEST; sha512_reg__intr_block_t__in_t intr_block_rf; @@ -228,7 +232,7 @@ package sha512_reg_pkg; kv_read_ctrl_reg__read_entry__out_t read_entry; kv_read_ctrl_reg__pcr_hash_extend__out_t pcr_hash_extend; kv_read_ctrl_reg__rsvd__out_t rsvd; - } __kv_read_ctrl_reg__out_t; + } kv_read_ctrl_reg__out_t; typedef struct packed{ logic value; @@ -271,7 +275,7 @@ package sha512_reg_pkg; kv_write_ctrl_reg__ecc_pkey_dest_valid__out_t ecc_pkey_dest_valid; kv_write_ctrl_reg__ecc_seed_dest_valid__out_t ecc_seed_dest_valid; kv_write_ctrl_reg__rsvd__out_t rsvd; - } __kv_write_ctrl_reg__out_t; + } kv_write_ctrl_reg__out_t; typedef struct packed{ logic [31:0] value; @@ -315,13 +319,19 @@ package sha512_reg_pkg; typedef struct packed{ sha512_reg__SHA512_CTRL__out_t SHA512_CTRL; sha512_reg__SHA512_BLOCK__out_t [32-1:0]SHA512_BLOCK; - __kv_read_ctrl_reg__out_t SHA512_VAULT_RD_CTRL; - __kv_write_ctrl_reg__out_t SHA512_KV_WR_CTRL; + kv_read_ctrl_reg__out_t SHA512_VAULT_RD_CTRL; + kv_write_ctrl_reg__out_t SHA512_KV_WR_CTRL; sha512_reg__SHA512_GEN_PCR_HASH_NONCE__out_t [8-1:0]SHA512_GEN_PCR_HASH_NONCE; sha512_reg__SHA512_GEN_PCR_HASH_CTRL__out_t SHA512_GEN_PCR_HASH_CTRL; sha512_reg__intr_block_t__out_t intr_block_rf; } sha512_reg__out_t; + typedef enum { + kv_status_reg__ERROR__kv_error_e__SUCCESS = 'h0, + kv_status_reg__ERROR__kv_error_e__KV_READ_FAIL = 'h1, + kv_status_reg__ERROR__kv_error_e__KV_WRITE_FAIL = 'h2 + } kv_status_reg__ERROR__kv_error_e_e; + localparam SHA512_REG_ADDR_WIDTH = 32'd12; endpackage \ No newline at end of file diff --git a/src/soc_ifc/rtl/caliptra_top_reg.h b/src/soc_ifc/rtl/caliptra_top_reg.h index 553225858..790b71cb8 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg.h +++ b/src/soc_ifc/rtl/caliptra_top_reg.h @@ -542,4 +542,4 @@ #define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK (0xffff) -#endif +#endif \ No newline at end of file diff --git a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh index 9677a065e..344d910ea 100644 --- a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh +++ b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh @@ -542,4 +542,4 @@ `define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK (32'hffff) -`endif +`endif \ No newline at end of file diff --git a/src/soc_ifc/rtl/mbox_csr.sv b/src/soc_ifc/rtl/mbox_csr.sv index cefd5b73d..12faac7c4 100644 --- a/src/soc_ifc/rtl/mbox_csr.sv +++ b/src/soc_ifc/rtl/mbox_csr.sv @@ -58,7 +58,9 @@ module mbox_csr ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -81,15 +83,15 @@ module mbox_csr ( logic [31:0] decoded_wr_biten; always_comb begin - decoded_reg_strb.mbox_lock = cpuif_req_masked & (cpuif_addr == 'h0); - decoded_reg_strb.mbox_user = cpuif_req_masked & (cpuif_addr == 'h4); - decoded_reg_strb.mbox_cmd = cpuif_req_masked & (cpuif_addr == 'h8); - decoded_reg_strb.mbox_dlen = cpuif_req_masked & (cpuif_addr == 'hc); - decoded_reg_strb.mbox_datain = cpuif_req_masked & (cpuif_addr == 'h10); - decoded_reg_strb.mbox_dataout = cpuif_req_masked & (cpuif_addr == 'h14); - decoded_reg_strb.mbox_execute = cpuif_req_masked & (cpuif_addr == 'h18); - decoded_reg_strb.mbox_status = cpuif_req_masked & (cpuif_addr == 'h1c); - decoded_reg_strb.mbox_unlock = cpuif_req_masked & (cpuif_addr == 'h20); + decoded_reg_strb.mbox_lock = cpuif_req_masked & (cpuif_addr == 6'h0); + decoded_reg_strb.mbox_user = cpuif_req_masked & (cpuif_addr == 6'h4); + decoded_reg_strb.mbox_cmd = cpuif_req_masked & (cpuif_addr == 6'h8); + decoded_reg_strb.mbox_dlen = cpuif_req_masked & (cpuif_addr == 6'hc); + decoded_reg_strb.mbox_datain = cpuif_req_masked & (cpuif_addr == 6'h10); + decoded_reg_strb.mbox_dataout = cpuif_req_masked & (cpuif_addr == 6'h14); + decoded_reg_strb.mbox_execute = cpuif_req_masked & (cpuif_addr == 6'h18); + decoded_reg_strb.mbox_status = cpuif_req_masked & (cpuif_addr == 6'h1c); + decoded_reg_strb.mbox_unlock = cpuif_req_masked & (cpuif_addr == 6'h20); end // Pass down signals to next stage @@ -98,10 +100,6 @@ module mbox_csr ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -249,8 +247,10 @@ module mbox_csr ( // Field: mbox_csr.mbox_lock.lock always_comb begin - automatic logic [0:0] next_c = field_storage.mbox_lock.lock.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_lock.lock.value; + load_next_c = '0; if(hwif_in.mbox_lock.lock.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; @@ -263,7 +263,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_lock.lock.value <= 'h0; + field_storage.mbox_lock.lock.value <= 1'h0; end else if(field_combo.mbox_lock.lock.load_next) begin field_storage.mbox_lock.lock.value <= field_combo.mbox_lock.lock.next; end @@ -272,8 +272,10 @@ module mbox_csr ( assign hwif_out.mbox_lock.lock.swmod = decoded_reg_strb.mbox_lock && !decoded_req_is_wr; // Field: mbox_csr.mbox_user.user always_comb begin - automatic logic [31:0] next_c = field_storage.mbox_user.user.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_user.user.value; + load_next_c = '0; if(hwif_in.lock_set) begin // HW Write - we next_c = hwif_in.mbox_user.user.next; load_next_c = '1; @@ -283,7 +285,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_user.user.value <= 'h0; + field_storage.mbox_user.user.value <= 32'h0; end else if(field_combo.mbox_user.user.load_next) begin field_storage.mbox_user.user.value <= field_combo.mbox_user.user.next; end @@ -291,8 +293,10 @@ module mbox_csr ( assign hwif_out.mbox_user.user.value = field_storage.mbox_user.user.value; // Field: mbox_csr.mbox_cmd.command always_comb begin - automatic logic [31:0] next_c = field_storage.mbox_cmd.command.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_cmd.command.value; + load_next_c = '0; if(decoded_reg_strb.mbox_cmd && decoded_req_is_wr && hwif_in.valid_requester) begin // SW write next_c = (field_storage.mbox_cmd.command.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -302,7 +306,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_cmd.command.value <= 'h0; + field_storage.mbox_cmd.command.value <= 32'h0; end else if(field_combo.mbox_cmd.command.load_next) begin field_storage.mbox_cmd.command.value <= field_combo.mbox_cmd.command.next; end @@ -310,8 +314,10 @@ module mbox_csr ( assign hwif_out.mbox_cmd.command.swmod = decoded_reg_strb.mbox_cmd && decoded_req_is_wr; // Field: mbox_csr.mbox_dlen.length always_comb begin - automatic logic [31:0] next_c = field_storage.mbox_dlen.length.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_dlen.length.value; + load_next_c = '0; if(decoded_reg_strb.mbox_dlen && decoded_req_is_wr && hwif_in.valid_requester) begin // SW write next_c = (field_storage.mbox_dlen.length.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -321,7 +327,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_dlen.length.value <= 'h0; + field_storage.mbox_dlen.length.value <= 32'h0; end else if(field_combo.mbox_dlen.length.load_next) begin field_storage.mbox_dlen.length.value <= field_combo.mbox_dlen.length.next; end @@ -330,8 +336,10 @@ module mbox_csr ( assign hwif_out.mbox_dlen.length.swmod = decoded_reg_strb.mbox_dlen && decoded_req_is_wr; // Field: mbox_csr.mbox_datain.datain always_comb begin - automatic logic [31:0] next_c = field_storage.mbox_datain.datain.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_datain.datain.value; + load_next_c = '0; if(decoded_reg_strb.mbox_datain && decoded_req_is_wr && hwif_in.valid_requester) begin // SW write next_c = (field_storage.mbox_datain.datain.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -341,7 +349,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_datain.datain.value <= 'h0; + field_storage.mbox_datain.datain.value <= 32'h0; end else if(field_combo.mbox_datain.datain.load_next) begin field_storage.mbox_datain.datain.value <= field_combo.mbox_datain.datain.next; end @@ -349,8 +357,10 @@ module mbox_csr ( assign hwif_out.mbox_datain.datain.swmod = decoded_reg_strb.mbox_datain && decoded_req_is_wr; // Field: mbox_csr.mbox_dataout.dataout always_comb begin - automatic logic [31:0] next_c = field_storage.mbox_dataout.dataout.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_dataout.dataout.value; + load_next_c = '0; if(decoded_reg_strb.mbox_dataout && decoded_req_is_wr && hwif_in.mbox_dataout.dataout.swwe) begin // SW write next_c = (field_storage.mbox_dataout.dataout.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -363,7 +373,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_dataout.dataout.value <= 'h0; + field_storage.mbox_dataout.dataout.value <= 32'h0; end else if(field_combo.mbox_dataout.dataout.load_next) begin field_storage.mbox_dataout.dataout.value <= field_combo.mbox_dataout.dataout.next; end @@ -372,8 +382,10 @@ module mbox_csr ( assign hwif_out.mbox_dataout.dataout.swacc = decoded_reg_strb.mbox_dataout; // Field: mbox_csr.mbox_execute.execute always_comb begin - automatic logic [0:0] next_c = field_storage.mbox_execute.execute.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_execute.execute.value; + load_next_c = '0; if(hwif_in.mbox_execute.execute.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; @@ -386,7 +398,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_execute.execute.value <= 'h0; + field_storage.mbox_execute.execute.value <= 1'h0; end else if(field_combo.mbox_execute.execute.load_next) begin field_storage.mbox_execute.execute.value <= field_combo.mbox_execute.execute.next; end @@ -395,8 +407,10 @@ module mbox_csr ( assign hwif_out.mbox_execute.execute.swmod = decoded_reg_strb.mbox_execute && decoded_req_is_wr; // Field: mbox_csr.mbox_status.status always_comb begin - automatic logic [3:0] next_c = field_storage.mbox_status.status.value; - automatic logic load_next_c = '0; + automatic logic [3:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_status.status.value; + load_next_c = '0; if(hwif_in.mbox_status.status.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; @@ -409,7 +423,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_status.status.value <= 'h0; + field_storage.mbox_status.status.value <= 4'h0; end else if(field_combo.mbox_status.status.load_next) begin field_storage.mbox_status.status.value <= field_combo.mbox_status.status.next; end @@ -418,8 +432,10 @@ module mbox_csr ( assign hwif_out.mbox_status.status.swmod = decoded_reg_strb.mbox_status && decoded_req_is_wr; // Field: mbox_csr.mbox_status.ecc_single_error always_comb begin - automatic logic [0:0] next_c = field_storage.mbox_status.ecc_single_error.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_status.ecc_single_error.value; + load_next_c = '0; if(!field_storage.mbox_execute.execute.value) begin // HW Write - wel next_c = field_storage.mbox_execute.execute.value; load_next_c = '1; @@ -432,7 +448,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_status.ecc_single_error.value <= 'h0; + field_storage.mbox_status.ecc_single_error.value <= 1'h0; end else if(field_combo.mbox_status.ecc_single_error.load_next) begin field_storage.mbox_status.ecc_single_error.value <= field_combo.mbox_status.ecc_single_error.next; end @@ -440,8 +456,10 @@ module mbox_csr ( assign hwif_out.mbox_status.ecc_single_error.value = field_storage.mbox_status.ecc_single_error.value; // Field: mbox_csr.mbox_status.ecc_double_error always_comb begin - automatic logic [0:0] next_c = field_storage.mbox_status.ecc_double_error.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_status.ecc_double_error.value; + load_next_c = '0; if(!field_storage.mbox_execute.execute.value) begin // HW Write - wel next_c = field_storage.mbox_execute.execute.value; load_next_c = '1; @@ -454,7 +472,7 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_status.ecc_double_error.value <= 'h0; + field_storage.mbox_status.ecc_double_error.value <= 1'h0; end else if(field_combo.mbox_status.ecc_double_error.load_next) begin field_storage.mbox_status.ecc_double_error.value <= field_combo.mbox_status.ecc_double_error.next; end @@ -462,18 +480,20 @@ module mbox_csr ( assign hwif_out.mbox_status.ecc_double_error.value = field_storage.mbox_status.ecc_double_error.value; // Field: mbox_csr.mbox_status.mbox_fsm_ps always_comb begin - automatic logic [2:0] next_c = field_storage.mbox_status.mbox_fsm_ps.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.mbox_status.mbox_fsm_ps.next; - load_next_c = '1; - end + automatic logic [2:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_status.mbox_fsm_ps.value; + load_next_c = '0; + + // HW Write + next_c = hwif_in.mbox_status.mbox_fsm_ps.next; + load_next_c = '1; field_combo.mbox_status.mbox_fsm_ps.next = next_c; field_combo.mbox_status.mbox_fsm_ps.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_status.mbox_fsm_ps.value <= 'h0; + field_storage.mbox_status.mbox_fsm_ps.value <= 3'h0; end else if(field_combo.mbox_status.mbox_fsm_ps.load_next) begin field_storage.mbox_status.mbox_fsm_ps.value <= field_combo.mbox_status.mbox_fsm_ps.next; end @@ -481,18 +501,20 @@ module mbox_csr ( assign hwif_out.mbox_status.mbox_fsm_ps.value = field_storage.mbox_status.mbox_fsm_ps.value; // Field: mbox_csr.mbox_status.soc_has_lock always_comb begin - automatic logic [0:0] next_c = field_storage.mbox_status.soc_has_lock.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.mbox_status.soc_has_lock.next; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_status.soc_has_lock.value; + load_next_c = '0; + + // HW Write + next_c = hwif_in.mbox_status.soc_has_lock.next; + load_next_c = '1; field_combo.mbox_status.soc_has_lock.next = next_c; field_combo.mbox_status.soc_has_lock.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_status.soc_has_lock.value <= 'h0; + field_storage.mbox_status.soc_has_lock.value <= 1'h0; end else if(field_combo.mbox_status.soc_has_lock.load_next) begin field_storage.mbox_status.soc_has_lock.value <= field_combo.mbox_status.soc_has_lock.next; end @@ -500,18 +522,20 @@ module mbox_csr ( assign hwif_out.mbox_status.soc_has_lock.value = field_storage.mbox_status.soc_has_lock.value; // Field: mbox_csr.mbox_status.mbox_rdptr always_comb begin - automatic logic [14:0] next_c = field_storage.mbox_status.mbox_rdptr.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.mbox_status.mbox_rdptr.next; - load_next_c = '1; - end + automatic logic [14:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_status.mbox_rdptr.value; + load_next_c = '0; + + // HW Write + next_c = hwif_in.mbox_status.mbox_rdptr.next; + load_next_c = '1; field_combo.mbox_status.mbox_rdptr.next = next_c; field_combo.mbox_status.mbox_rdptr.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_status.mbox_rdptr.value <= 'h0; + field_storage.mbox_status.mbox_rdptr.value <= 15'h0; end else if(field_combo.mbox_status.mbox_rdptr.load_next) begin field_storage.mbox_status.mbox_rdptr.value <= field_combo.mbox_status.mbox_rdptr.next; end @@ -519,12 +543,14 @@ module mbox_csr ( assign hwif_out.mbox_status.mbox_rdptr.value = field_storage.mbox_status.mbox_rdptr.value; // Field: mbox_csr.mbox_unlock.unlock always_comb begin - automatic logic [0:0] next_c = field_storage.mbox_unlock.unlock.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mbox_unlock.unlock.value; + load_next_c = '0; if(decoded_reg_strb.mbox_unlock && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.mbox_unlock.unlock.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -533,19 +559,28 @@ module mbox_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.mbox_unlock.unlock.value <= 'h0; + field_storage.mbox_unlock.unlock.value <= 1'h0; end else if(field_combo.mbox_unlock.unlock.load_next) begin field_storage.mbox_unlock.unlock.value <= field_combo.mbox_unlock.unlock.next; end end assign hwif_out.mbox_unlock.unlock.value = field_storage.mbox_unlock.unlock.value; + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [9-1:0][31:0] readback_array; assign readback_array[0][0:0] = (decoded_reg_strb.mbox_lock && !decoded_req_is_wr) ? field_storage.mbox_lock.lock.value : '0; @@ -580,4 +615,4 @@ module mbox_csr ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; -endmodule \ No newline at end of file +endmodule diff --git a/src/soc_ifc/rtl/mbox_csr_pkg.sv b/src/soc_ifc/rtl/mbox_csr_pkg.sv index 1c9766e24..5242de798 100644 --- a/src/soc_ifc/rtl/mbox_csr_pkg.sv +++ b/src/soc_ifc/rtl/mbox_csr_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package mbox_csr_pkg; + + localparam MBOX_CSR_DATA_WIDTH = 32; + localparam MBOX_CSR_MIN_ADDR_WIDTH = 6; + typedef struct packed{ logic hwclr; } mbox_csr__mbox_lock__lock__in_t; @@ -38,35 +42,35 @@ package mbox_csr_pkg; typedef struct packed{ logic hwclr; - } mbox_csr__mbox_status__status__in_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__status__in_t; typedef struct packed{ logic hwset; - } mbox_csr__mbox_status__ecc_single_error_next_e066e214_wel_e066e214__in_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__ecc_single_error_next_e066e214_wel_e066e214__in_t; typedef struct packed{ logic hwset; - } mbox_csr__mbox_status__ecc_double_error_next_e066e214_wel_e066e214__in_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__ecc_double_error_next_e066e214_wel_e066e214__in_t; typedef struct packed{ logic [2:0] next; - } mbox_csr__mbox_status__mbox_fsm_ps__in_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__mbox_fsm_ps__in_t; typedef struct packed{ logic next; - } mbox_csr__mbox_status__soc_has_lock__in_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__soc_has_lock__in_t; typedef struct packed{ logic [14:0] next; - } mbox_csr__mbox_status__mbox_rdptr__in_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__mbox_rdptr__in_t; typedef struct packed{ - mbox_csr__mbox_status__status__in_t status; - mbox_csr__mbox_status__ecc_single_error_next_e066e214_wel_e066e214__in_t ecc_single_error; - mbox_csr__mbox_status__ecc_double_error_next_e066e214_wel_e066e214__in_t ecc_double_error; - mbox_csr__mbox_status__mbox_fsm_ps__in_t mbox_fsm_ps; - mbox_csr__mbox_status__soc_has_lock__in_t soc_has_lock; - mbox_csr__mbox_status__mbox_rdptr__in_t mbox_rdptr; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__status__in_t status; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__ecc_single_error_next_e066e214_wel_e066e214__in_t ecc_single_error; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__ecc_double_error_next_e066e214_wel_e066e214__in_t ecc_double_error; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__mbox_fsm_ps__in_t mbox_fsm_ps; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__soc_has_lock__in_t soc_has_lock; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__mbox_rdptr__in_t mbox_rdptr; } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__in_t; typedef struct packed{ @@ -145,35 +149,35 @@ package mbox_csr_pkg; typedef struct packed{ logic [3:0] value; logic swmod; - } mbox_csr__mbox_status__status__out_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__status__out_t; typedef struct packed{ logic value; - } mbox_csr__mbox_status__ecc_single_error_next_e066e214_wel_e066e214__out_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__ecc_single_error_next_e066e214_wel_e066e214__out_t; typedef struct packed{ logic value; - } mbox_csr__mbox_status__ecc_double_error_next_e066e214_wel_e066e214__out_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__ecc_double_error_next_e066e214_wel_e066e214__out_t; typedef struct packed{ logic [2:0] value; - } mbox_csr__mbox_status__mbox_fsm_ps__out_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__mbox_fsm_ps__out_t; typedef struct packed{ logic value; - } mbox_csr__mbox_status__soc_has_lock__out_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__soc_has_lock__out_t; typedef struct packed{ logic [14:0] value; - } mbox_csr__mbox_status__mbox_rdptr__out_t; + } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__mbox_rdptr__out_t; typedef struct packed{ - mbox_csr__mbox_status__status__out_t status; - mbox_csr__mbox_status__ecc_single_error_next_e066e214_wel_e066e214__out_t ecc_single_error; - mbox_csr__mbox_status__ecc_double_error_next_e066e214_wel_e066e214__out_t ecc_double_error; - mbox_csr__mbox_status__mbox_fsm_ps__out_t mbox_fsm_ps; - mbox_csr__mbox_status__soc_has_lock__out_t soc_has_lock; - mbox_csr__mbox_status__mbox_rdptr__out_t mbox_rdptr; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__status__out_t status; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__ecc_single_error_next_e066e214_wel_e066e214__out_t ecc_single_error; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__ecc_double_error_next_e066e214_wel_e066e214__out_t ecc_double_error; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__mbox_fsm_ps__out_t mbox_fsm_ps; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__soc_has_lock__out_t soc_has_lock; + mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__mbox_rdptr__out_t mbox_rdptr; } mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__out_t; typedef struct packed{ @@ -196,6 +200,23 @@ package mbox_csr_pkg; mbox_csr__mbox_unlock__out_t mbox_unlock; } mbox_csr__out_t; + typedef enum { + mbox_csr__mbox_status__status__mbox_status_e__CMD_BUSY = 'h0, + mbox_csr__mbox_status__status__mbox_status_e__DATA_READY = 'h1, + mbox_csr__mbox_status__status__mbox_status_e__CMD_COMPLETE = 'h2, + mbox_csr__mbox_status__status__mbox_status_e__CMD_FAILURE = 'h3 + } mbox_csr__mbox_status__status__mbox_status_e_e; + + typedef enum { + mbox_csr__mbox_status__mbox_fsm_ps__mbox_fsm_e__MBOX_IDLE = 'h0, + mbox_csr__mbox_status__mbox_fsm_ps__mbox_fsm_e__MBOX_RDY_FOR_CMD = 'h1, + mbox_csr__mbox_status__mbox_fsm_ps__mbox_fsm_e__MBOX_RDY_FOR_DLEN = 'h3, + mbox_csr__mbox_status__mbox_fsm_ps__mbox_fsm_e__MBOX_RDY_FOR_DATA = 'h2, + mbox_csr__mbox_status__mbox_fsm_ps__mbox_fsm_e__MBOX_EXECUTE_UC = 'h6, + mbox_csr__mbox_status__mbox_fsm_ps__mbox_fsm_e__MBOX_EXECUTE_SOC = 'h4, + mbox_csr__mbox_status__mbox_fsm_ps__mbox_fsm_e__MBOX_ERROR = 'h7 + } mbox_csr__mbox_status__mbox_fsm_ps__mbox_fsm_e_e; + localparam MBOX_CSR_ADDR_WIDTH = 32'd6; endpackage \ No newline at end of file diff --git a/src/soc_ifc/rtl/sha512_acc_csr.sv b/src/soc_ifc/rtl/sha512_acc_csr.sv index 1188e3192..218925afb 100644 --- a/src/soc_ifc/rtl/sha512_acc_csr.sv +++ b/src/soc_ifc/rtl/sha512_acc_csr.sv @@ -58,7 +58,9 @@ module sha512_acc_csr ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -103,37 +105,37 @@ module sha512_acc_csr ( logic [31:0] decoded_wr_biten; always_comb begin - decoded_reg_strb.LOCK = cpuif_req_masked & (cpuif_addr == 'h0); - decoded_reg_strb.USER = cpuif_req_masked & (cpuif_addr == 'h4); - decoded_reg_strb.MODE = cpuif_req_masked & (cpuif_addr == 'h8); - decoded_reg_strb.START_ADDRESS = cpuif_req_masked & (cpuif_addr == 'hc); - decoded_reg_strb.DLEN = cpuif_req_masked & (cpuif_addr == 'h10); - decoded_reg_strb.DATAIN = cpuif_req_masked & (cpuif_addr == 'h14); - decoded_reg_strb.EXECUTE = cpuif_req_masked & (cpuif_addr == 'h18); - decoded_reg_strb.STATUS = cpuif_req_masked & (cpuif_addr == 'h1c); + decoded_reg_strb.LOCK = cpuif_req_masked & (cpuif_addr == 12'h0); + decoded_reg_strb.USER = cpuif_req_masked & (cpuif_addr == 12'h4); + decoded_reg_strb.MODE = cpuif_req_masked & (cpuif_addr == 12'h8); + decoded_reg_strb.START_ADDRESS = cpuif_req_masked & (cpuif_addr == 12'hc); + decoded_reg_strb.DLEN = cpuif_req_masked & (cpuif_addr == 12'h10); + decoded_reg_strb.DATAIN = cpuif_req_masked & (cpuif_addr == 12'h14); + decoded_reg_strb.EXECUTE = cpuif_req_masked & (cpuif_addr == 12'h18); + decoded_reg_strb.STATUS = cpuif_req_masked & (cpuif_addr == 12'h1c); for(int i0=0; i0<16; i0++) begin - decoded_reg_strb.DIGEST[i0] = cpuif_req_masked & (cpuif_addr == 'h20 + i0*'h4); - end - decoded_reg_strb.CONTROL = cpuif_req_masked & (cpuif_addr == 'h60); - decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h800); - decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h804); - decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h808); - decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h80c); - decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h810); - decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h814); - decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h818); - decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h81c); - decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h820); - decoded_reg_strb.intr_block_rf.error0_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h900); - decoded_reg_strb.intr_block_rf.error1_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h904); - decoded_reg_strb.intr_block_rf.error2_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h908); - decoded_reg_strb.intr_block_rf.error3_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h90c); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h980); - decoded_reg_strb.intr_block_rf.error0_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha00); - decoded_reg_strb.intr_block_rf.error1_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha04); - decoded_reg_strb.intr_block_rf.error2_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha08); - decoded_reg_strb.intr_block_rf.error3_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha0c); - decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha10); + decoded_reg_strb.DIGEST[i0] = cpuif_req_masked & (cpuif_addr == 12'h20 + i0*12'h4); + end + decoded_reg_strb.CONTROL = cpuif_req_masked & (cpuif_addr == 12'h60); + decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h800); + decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h804); + decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h808); + decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h80c); + decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h810); + decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h814); + decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h818); + decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h81c); + decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h820); + decoded_reg_strb.intr_block_rf.error0_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h900); + decoded_reg_strb.intr_block_rf.error1_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h904); + decoded_reg_strb.intr_block_rf.error2_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h908); + decoded_reg_strb.intr_block_rf.error3_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h90c); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h980); + decoded_reg_strb.intr_block_rf.error0_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha00); + decoded_reg_strb.intr_block_rf.error1_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha04); + decoded_reg_strb.intr_block_rf.error2_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha08); + decoded_reg_strb.intr_block_rf.error3_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha0c); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha10); end // Pass down signals to next stage @@ -142,10 +144,6 @@ module sha512_acc_csr ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -586,8 +584,10 @@ module sha512_acc_csr ( // Field: sha512_acc_csr.LOCK.LOCK always_comb begin - automatic logic [0:0] next_c = field_storage.LOCK.LOCK.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.LOCK.LOCK.value; + load_next_c = '0; if(decoded_reg_strb.LOCK && !decoded_req_is_wr) begin // SW set on read next_c = '1; load_next_c = '1; @@ -600,7 +600,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.LOCK.LOCK.value <= 'h1; + field_storage.LOCK.LOCK.value <= 1'h1; end else if(field_combo.LOCK.LOCK.load_next) begin field_storage.LOCK.LOCK.value <= field_combo.LOCK.LOCK.next; end @@ -609,8 +609,10 @@ module sha512_acc_csr ( assign hwif_out.LOCK.LOCK.swmod = decoded_reg_strb.LOCK; // Field: sha512_acc_csr.USER.USER always_comb begin - automatic logic [31:0] next_c = field_storage.USER.USER.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.USER.USER.value; + load_next_c = '0; if(hwif_in.lock_set) begin // HW Write - we next_c = hwif_in.USER.USER.next; load_next_c = '1; @@ -620,7 +622,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.USER.USER.value <= 'h0; + field_storage.USER.USER.value <= 32'h0; end else if(field_combo.USER.USER.load_next) begin field_storage.USER.USER.value <= field_combo.USER.USER.next; end @@ -628,8 +630,10 @@ module sha512_acc_csr ( assign hwif_out.USER.USER.value = field_storage.USER.USER.value; // Field: sha512_acc_csr.MODE.MODE always_comb begin - automatic logic [1:0] next_c = field_storage.MODE.MODE.value; - automatic logic load_next_c = '0; + automatic logic [1:0] next_c; + automatic logic load_next_c; + next_c = field_storage.MODE.MODE.value; + load_next_c = '0; if(decoded_reg_strb.MODE && decoded_req_is_wr && hwif_in.valid_user) begin // SW write next_c = (field_storage.MODE.MODE.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]); load_next_c = '1; @@ -639,7 +643,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.MODE.MODE.value <= 'h0; + field_storage.MODE.MODE.value <= 2'h0; end else if(field_combo.MODE.MODE.load_next) begin field_storage.MODE.MODE.value <= field_combo.MODE.MODE.next; end @@ -648,8 +652,10 @@ module sha512_acc_csr ( assign hwif_out.MODE.MODE.swmod = decoded_reg_strb.MODE && decoded_req_is_wr; // Field: sha512_acc_csr.MODE.ENDIAN_TOGGLE always_comb begin - automatic logic [0:0] next_c = field_storage.MODE.ENDIAN_TOGGLE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.MODE.ENDIAN_TOGGLE.value; + load_next_c = '0; if(decoded_reg_strb.MODE && decoded_req_is_wr && hwif_in.valid_user) begin // SW write next_c = (field_storage.MODE.ENDIAN_TOGGLE.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -659,7 +665,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.MODE.ENDIAN_TOGGLE.value <= 'h0; + field_storage.MODE.ENDIAN_TOGGLE.value <= 1'h0; end else if(field_combo.MODE.ENDIAN_TOGGLE.load_next) begin field_storage.MODE.ENDIAN_TOGGLE.value <= field_combo.MODE.ENDIAN_TOGGLE.next; end @@ -667,8 +673,10 @@ module sha512_acc_csr ( assign hwif_out.MODE.ENDIAN_TOGGLE.value = field_storage.MODE.ENDIAN_TOGGLE.value; // Field: sha512_acc_csr.START_ADDRESS.ADDR always_comb begin - automatic logic [31:0] next_c = field_storage.START_ADDRESS.ADDR.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.START_ADDRESS.ADDR.value; + load_next_c = '0; if(decoded_reg_strb.START_ADDRESS && decoded_req_is_wr && hwif_in.valid_user) begin // SW write next_c = (field_storage.START_ADDRESS.ADDR.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -678,7 +686,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.START_ADDRESS.ADDR.value <= 'h0; + field_storage.START_ADDRESS.ADDR.value <= 32'h0; end else if(field_combo.START_ADDRESS.ADDR.load_next) begin field_storage.START_ADDRESS.ADDR.value <= field_combo.START_ADDRESS.ADDR.next; end @@ -686,8 +694,10 @@ module sha512_acc_csr ( assign hwif_out.START_ADDRESS.ADDR.value = field_storage.START_ADDRESS.ADDR.value; // Field: sha512_acc_csr.DLEN.LENGTH always_comb begin - automatic logic [31:0] next_c = field_storage.DLEN.LENGTH.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DLEN.LENGTH.value; + load_next_c = '0; if(decoded_reg_strb.DLEN && decoded_req_is_wr && hwif_in.valid_user) begin // SW write next_c = (field_storage.DLEN.LENGTH.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -697,7 +707,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.DLEN.LENGTH.value <= 'h0; + field_storage.DLEN.LENGTH.value <= 32'h0; end else if(field_combo.DLEN.LENGTH.load_next) begin field_storage.DLEN.LENGTH.value <= field_combo.DLEN.LENGTH.next; end @@ -705,8 +715,10 @@ module sha512_acc_csr ( assign hwif_out.DLEN.LENGTH.value = field_storage.DLEN.LENGTH.value; // Field: sha512_acc_csr.DATAIN.DATAIN always_comb begin - automatic logic [31:0] next_c = field_storage.DATAIN.DATAIN.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DATAIN.DATAIN.value; + load_next_c = '0; if(decoded_reg_strb.DATAIN && decoded_req_is_wr && hwif_in.valid_user) begin // SW write next_c = (field_storage.DATAIN.DATAIN.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -716,7 +728,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.DATAIN.DATAIN.value <= 'h0; + field_storage.DATAIN.DATAIN.value <= 32'h0; end else if(field_combo.DATAIN.DATAIN.load_next) begin field_storage.DATAIN.DATAIN.value <= field_combo.DATAIN.DATAIN.next; end @@ -724,8 +736,10 @@ module sha512_acc_csr ( assign hwif_out.DATAIN.DATAIN.swmod = decoded_reg_strb.DATAIN && decoded_req_is_wr; // Field: sha512_acc_csr.EXECUTE.EXECUTE always_comb begin - automatic logic [0:0] next_c = field_storage.EXECUTE.EXECUTE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.EXECUTE.EXECUTE.value; + load_next_c = '0; if(decoded_reg_strb.EXECUTE && decoded_req_is_wr && hwif_in.valid_user) begin // SW write next_c = (field_storage.EXECUTE.EXECUTE.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -738,7 +752,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.EXECUTE.EXECUTE.value <= 'h0; + field_storage.EXECUTE.EXECUTE.value <= 1'h0; end else if(field_combo.EXECUTE.EXECUTE.load_next) begin field_storage.EXECUTE.EXECUTE.value <= field_combo.EXECUTE.EXECUTE.next; end @@ -746,18 +760,20 @@ module sha512_acc_csr ( assign hwif_out.EXECUTE.EXECUTE.value = field_storage.EXECUTE.EXECUTE.value; // Field: sha512_acc_csr.STATUS.VALID always_comb begin - automatic logic [0:0] next_c = field_storage.STATUS.VALID.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.STATUS.VALID.next; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.STATUS.VALID.value; + load_next_c = '0; + + // HW Write + next_c = hwif_in.STATUS.VALID.next; + load_next_c = '1; field_combo.STATUS.VALID.next = next_c; field_combo.STATUS.VALID.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.STATUS.VALID.value <= 'h0; + field_storage.STATUS.VALID.value <= 1'h0; end else if(field_combo.STATUS.VALID.load_next) begin field_storage.STATUS.VALID.value <= field_combo.STATUS.VALID.next; end @@ -765,18 +781,20 @@ module sha512_acc_csr ( assign hwif_out.STATUS.VALID.value = field_storage.STATUS.VALID.value; // Field: sha512_acc_csr.STATUS.SOC_HAS_LOCK always_comb begin - automatic logic [0:0] next_c = field_storage.STATUS.SOC_HAS_LOCK.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.STATUS.SOC_HAS_LOCK.next; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.STATUS.SOC_HAS_LOCK.value; + load_next_c = '0; + + // HW Write + next_c = hwif_in.STATUS.SOC_HAS_LOCK.next; + load_next_c = '1; field_combo.STATUS.SOC_HAS_LOCK.next = next_c; field_combo.STATUS.SOC_HAS_LOCK.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.STATUS.SOC_HAS_LOCK.value <= 'h0; + field_storage.STATUS.SOC_HAS_LOCK.value <= 1'h0; end else if(field_combo.STATUS.SOC_HAS_LOCK.load_next) begin field_storage.STATUS.SOC_HAS_LOCK.value <= field_combo.STATUS.SOC_HAS_LOCK.next; end @@ -785,21 +803,23 @@ module sha512_acc_csr ( for(genvar i0=0; i0<16; i0++) begin // Field: sha512_acc_csr.DIGEST[].DIGEST always_comb begin - automatic logic [31:0] next_c = field_storage.DIGEST[i0].DIGEST.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.DIGEST[i0].DIGEST.next; - load_next_c = '1; - end else if(hwif_in.DIGEST[i0].DIGEST.hwclr) begin // HW Clear + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.DIGEST[i0].DIGEST.value; + load_next_c = '0; + if(hwif_in.DIGEST[i0].DIGEST.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; + end else begin // HW Write + next_c = hwif_in.DIGEST[i0].DIGEST.next; + load_next_c = '1; end field_combo.DIGEST[i0].DIGEST.next = next_c; field_combo.DIGEST[i0].DIGEST.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.DIGEST[i0].DIGEST.value <= 'h0; + field_storage.DIGEST[i0].DIGEST.value <= 32'h0; end else if(field_combo.DIGEST[i0].DIGEST.load_next) begin field_storage.DIGEST[i0].DIGEST.value <= field_combo.DIGEST[i0].DIGEST.next; end @@ -807,12 +827,14 @@ module sha512_acc_csr ( end // Field: sha512_acc_csr.CONTROL.ZEROIZE always_comb begin - automatic logic [0:0] next_c = field_storage.CONTROL.ZEROIZE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CONTROL.ZEROIZE.value; + load_next_c = '0; if(decoded_reg_strb.CONTROL && decoded_req_is_wr) begin // SW write next_c = (field_storage.CONTROL.ZEROIZE.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -821,7 +843,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CONTROL.ZEROIZE.value <= 'h0; + field_storage.CONTROL.ZEROIZE.value <= 1'h0; end else if(field_combo.CONTROL.ZEROIZE.load_next) begin field_storage.CONTROL.ZEROIZE.value <= field_combo.CONTROL.ZEROIZE.next; end @@ -829,8 +851,10 @@ module sha512_acc_csr ( assign hwif_out.CONTROL.ZEROIZE.value = field_storage.CONTROL.ZEROIZE.value; // Field: sha512_acc_csr.intr_block_rf.global_intr_en_r.error_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.error_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -840,15 +864,17 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.error_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.error_en.value <= field_combo.intr_block_rf.global_intr_en_r.error_en.next; end end // Field: sha512_acc_csr.intr_block_rf.global_intr_en_r.notif_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.notif_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -858,15 +884,17 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.notif_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= field_combo.intr_block_rf.global_intr_en_r.notif_en.next; end end // Field: sha512_acc_csr.intr_block_rf.error_intr_en_r.error0_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error0_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error0_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -876,15 +904,17 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error0_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error0_en.value <= field_combo.intr_block_rf.error_intr_en_r.error0_en.next; end end // Field: sha512_acc_csr.intr_block_rf.error_intr_en_r.error1_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error1_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error1_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -894,15 +924,17 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error1_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error1_en.value <= field_combo.intr_block_rf.error_intr_en_r.error1_en.next; end end // Field: sha512_acc_csr.intr_block_rf.error_intr_en_r.error2_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error2_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error2_en.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -912,15 +944,17 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error2_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error2_en.value <= field_combo.intr_block_rf.error_intr_en_r.error2_en.next; end end // Field: sha512_acc_csr.intr_block_rf.error_intr_en_r.error3_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error3_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error3_en.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -930,15 +964,17 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error3_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error3_en.value <= field_combo.intr_block_rf.error_intr_en_r.error3_en.next; end end // Field: sha512_acc_csr.intr_block_rf.notif_intr_en_r.notif_cmd_done_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -948,25 +984,27 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.next; end end // Field: sha512_acc_csr.intr_block_rf.error_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.error_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.error_global_intr_r.agg_sts.next; end @@ -975,18 +1013,20 @@ module sha512_acc_csr ( |(field_storage.intr_block_rf.error_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.error_en.value); // Field: sha512_acc_csr.intr_block_rf.notif_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next; end @@ -995,9 +1035,11 @@ module sha512_acc_csr ( |(field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.notif_en.value); // Field: sha512_acc_csr.intr_block_rf.error_internal_intr_r.error0_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error0_sts.hwset) begin // HW Set @@ -1012,16 +1054,18 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error0_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error0_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error0_sts.next; end end // Field: sha512_acc_csr.intr_block_rf.error_internal_intr_r.error1_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error1_sts.hwset) begin // HW Set @@ -1036,16 +1080,18 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error1_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error1_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error1_sts.next; end end // Field: sha512_acc_csr.intr_block_rf.error_internal_intr_r.error2_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error2_sts.hwset) begin // HW Set @@ -1060,16 +1106,18 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error2_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error2_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error2_sts.next; end end // Field: sha512_acc_csr.intr_block_rf.error_internal_intr_r.error3_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error3_sts.hwset) begin // HW Set @@ -1084,7 +1132,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error3_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error3_sts.next; end @@ -1096,9 +1144,11 @@ module sha512_acc_csr ( || |(field_storage.intr_block_rf.error_internal_intr_r.error3_sts.value & field_storage.intr_block_rf.error_intr_en_r.error3_en.value); // Field: sha512_acc_csr.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.hwset) begin // HW Set @@ -1113,7 +1163,7 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.next; end @@ -1122,12 +1172,14 @@ module sha512_acc_csr ( |(field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value); // Field: sha512_acc_csr.intr_block_rf.error_intr_trig_r.error0_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1136,19 +1188,21 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error0_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error0_trig.next; end end // Field: sha512_acc_csr.intr_block_rf.error_intr_trig_r.error1_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1157,19 +1211,21 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error1_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error1_trig.next; end end // Field: sha512_acc_csr.intr_block_rf.error_intr_trig_r.error2_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1178,19 +1234,21 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error2_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error2_trig.next; end end // Field: sha512_acc_csr.intr_block_rf.error_intr_trig_r.error3_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1199,19 +1257,21 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error3_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error3_trig.next; end end // Field: sha512_acc_csr.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -1220,31 +1280,33 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.next; end end // Field: sha512_acc_csr.intr_block_rf.error0_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error0_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error0_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error0_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error0_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error0_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error0_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error0_intr_count_r.cnt.next = next_c; @@ -1252,31 +1314,33 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error0_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error0_intr_count_r.cnt.value <= field_combo.intr_block_rf.error0_intr_count_r.cnt.next; end end // Field: sha512_acc_csr.intr_block_rf.error1_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error1_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error1_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error1_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error1_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error1_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error1_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error1_intr_count_r.cnt.next = next_c; @@ -1284,31 +1348,33 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error1_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error1_intr_count_r.cnt.value <= field_combo.intr_block_rf.error1_intr_count_r.cnt.next; end end // Field: sha512_acc_csr.intr_block_rf.error2_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error2_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error2_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error2_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error2_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error2_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error2_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error2_intr_count_r.cnt.next = next_c; @@ -1316,31 +1382,33 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error2_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error2_intr_count_r.cnt.value <= field_combo.intr_block_rf.error2_intr_count_r.cnt.next; end end // Field: sha512_acc_csr.intr_block_rf.error3_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error3_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error3_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error3_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error3_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error3_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error3_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error3_intr_count_r.cnt.next = next_c; @@ -1348,31 +1416,33 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error3_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error3_intr_count_r.cnt.value <= field_combo.intr_block_rf.error3_intr_count_r.cnt.next; end end // Field: sha512_acc_csr.intr_block_rf.notif_cmd_done_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next = next_c; @@ -1380,15 +1450,17 @@ module sha512_acc_csr ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next; end end // Field: sha512_acc_csr.intr_block_rf.error0_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error0_trig.value; load_next_c = '1; @@ -1397,27 +1469,29 @@ module sha512_acc_csr ( load_next_c = '1; end if(field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error0_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error0_intr_count_incr_r.pulse.next; end end // Field: sha512_acc_csr.intr_block_rf.error1_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error1_trig.value; load_next_c = '1; @@ -1426,27 +1500,29 @@ module sha512_acc_csr ( load_next_c = '1; end if(field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error1_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error1_intr_count_incr_r.pulse.next; end end // Field: sha512_acc_csr.intr_block_rf.error2_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error2_trig.value; load_next_c = '1; @@ -1455,27 +1531,29 @@ module sha512_acc_csr ( load_next_c = '1; end if(field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error2_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error2_intr_count_incr_r.pulse.next; end end // Field: sha512_acc_csr.intr_block_rf.error3_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error3_trig.value; load_next_c = '1; @@ -1484,27 +1562,29 @@ module sha512_acc_csr ( load_next_c = '1; end if(field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error3_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error3_intr_count_incr_r.pulse.next; end end // Field: sha512_acc_csr.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; load_next_c = '1; @@ -1513,30 +1593,39 @@ module sha512_acc_csr ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next; end end + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [44-1:0][31:0] readback_array; assign readback_array[0][0:0] = (decoded_reg_strb.LOCK && !decoded_req_is_wr) ? field_storage.LOCK.LOCK.value : '0; @@ -1615,4 +1704,4 @@ module sha512_acc_csr ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; -endmodule \ No newline at end of file +endmodule diff --git a/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv b/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv index 6cb6af010..037662f34 100644 --- a/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv +++ b/src/soc_ifc/rtl/sha512_acc_csr_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package sha512_acc_csr_pkg; + + localparam SHA512_ACC_CSR_DATA_WIDTH = 32; + localparam SHA512_ACC_CSR_MIN_ADDR_WIDTH = 12; + typedef struct packed{ logic [31:0] next; } sha512_acc_csr__USER__USER__in_t; @@ -42,33 +46,33 @@ package sha512_acc_csr_pkg; typedef struct packed{ logic hwset; - } sha512_acc_csr__error_intr_t__error0_sts_enable_528ccada_next_b1018582_resetsignal_f7aac87a__in_t; + } sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error0_sts_enable_528ccada_next_b1018582_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } sha512_acc_csr__error_intr_t__error1_sts_enable_938cafef_next_f460eb81_resetsignal_f7aac87a__in_t; + } sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error1_sts_enable_938cafef_next_f460eb81_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } sha512_acc_csr__error_intr_t__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_f7aac87a__in_t; + } sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } sha512_acc_csr__error_intr_t__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_f7aac87a__in_t; + } sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_f7aac87a__in_t; typedef struct packed{ - sha512_acc_csr__error_intr_t__error0_sts_enable_528ccada_next_b1018582_resetsignal_f7aac87a__in_t error0_sts; - sha512_acc_csr__error_intr_t__error1_sts_enable_938cafef_next_f460eb81_resetsignal_f7aac87a__in_t error1_sts; - sha512_acc_csr__error_intr_t__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_f7aac87a__in_t error2_sts; - sha512_acc_csr__error_intr_t__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_f7aac87a__in_t error3_sts; + sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error0_sts_enable_528ccada_next_b1018582_resetsignal_f7aac87a__in_t error0_sts; + sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error1_sts_enable_938cafef_next_f460eb81_resetsignal_f7aac87a__in_t error1_sts; + sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error2_sts_enable_0dacf7a6_next_4b5b9e74_resetsignal_f7aac87a__in_t error2_sts; + sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__error3_sts_enable_fc3af94b_next_c3125d40_resetsignal_f7aac87a__in_t error3_sts; } sha512_acc_csr__error_intr_t_error0_sts_5ee134bf_error1_sts_aad9583f_error2_sts_6cad4575_error3_sts_735bbeba__in_t; typedef struct packed{ logic hwset; - } sha512_acc_csr__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; + } sha512_acc_csr__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; typedef struct packed{ - sha512_acc_csr__notif_intr_t__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; + sha512_acc_csr__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; } sha512_acc_csr__notif_intr_t_notif_cmd_done_sts_1c68637e__in_t; typedef struct packed{ @@ -209,6 +213,13 @@ package sha512_acc_csr_pkg; sha512_acc_csr__intr_block_t__out_t intr_block_rf; } sha512_acc_csr__out_t; + typedef enum { + sha512_acc_csr__MODE__MODE__sha_cmd_e__SHA_STREAM_384 = 'h0, + sha512_acc_csr__MODE__MODE__sha_cmd_e__SHA_STREAM_512 = 'h1, + sha512_acc_csr__MODE__MODE__sha_cmd_e__SHA_MBOX_384 = 'h2, + sha512_acc_csr__MODE__MODE__sha_cmd_e__SHA_MBOX_512 = 'h3 + } sha512_acc_csr__MODE__MODE__sha_cmd_e_e; + localparam SHA512_ACC_CSR_ADDR_WIDTH = 32'd12; endpackage \ No newline at end of file diff --git a/src/soc_ifc/rtl/soc_ifc_reg.sv b/src/soc_ifc/rtl/soc_ifc_reg.sv index c81364f56..dcf21c35d 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg.sv @@ -58,7 +58,9 @@ module soc_ifc_reg ( // Read & write latencies are balanced. Stalls not required assign cpuif_req_stall_rd = '0; assign cpuif_req_stall_wr = '0; - assign cpuif_req_masked = cpuif_req; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); //-------------------------------------------------------------------------- // Address Decode @@ -179,149 +181,149 @@ module soc_ifc_reg ( logic [31:0] decoded_wr_biten; always_comb begin - decoded_reg_strb.CPTRA_HW_ERROR_FATAL = cpuif_req_masked & (cpuif_addr == 'h0); - decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL = cpuif_req_masked & (cpuif_addr == 'h4); - decoded_reg_strb.CPTRA_FW_ERROR_FATAL = cpuif_req_masked & (cpuif_addr == 'h8); - decoded_reg_strb.CPTRA_FW_ERROR_NON_FATAL = cpuif_req_masked & (cpuif_addr == 'hc); - decoded_reg_strb.CPTRA_HW_ERROR_ENC = cpuif_req_masked & (cpuif_addr == 'h10); - decoded_reg_strb.CPTRA_FW_ERROR_ENC = cpuif_req_masked & (cpuif_addr == 'h14); + decoded_reg_strb.CPTRA_HW_ERROR_FATAL = cpuif_req_masked & (cpuif_addr == 12'h0); + decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL = cpuif_req_masked & (cpuif_addr == 12'h4); + decoded_reg_strb.CPTRA_FW_ERROR_FATAL = cpuif_req_masked & (cpuif_addr == 12'h8); + decoded_reg_strb.CPTRA_FW_ERROR_NON_FATAL = cpuif_req_masked & (cpuif_addr == 12'hc); + decoded_reg_strb.CPTRA_HW_ERROR_ENC = cpuif_req_masked & (cpuif_addr == 12'h10); + decoded_reg_strb.CPTRA_FW_ERROR_ENC = cpuif_req_masked & (cpuif_addr == 12'h14); for(int i0=0; i0<8; i0++) begin - decoded_reg_strb.CPTRA_FW_EXTENDED_ERROR_INFO[i0] = cpuif_req_masked & (cpuif_addr == 'h18 + i0*'h4); + decoded_reg_strb.CPTRA_FW_EXTENDED_ERROR_INFO[i0] = cpuif_req_masked & (cpuif_addr == 12'h18 + i0*12'h4); end - decoded_reg_strb.CPTRA_BOOT_STATUS = cpuif_req_masked & (cpuif_addr == 'h38); - decoded_reg_strb.CPTRA_FLOW_STATUS = cpuif_req_masked & (cpuif_addr == 'h3c); - decoded_reg_strb.CPTRA_RESET_REASON = cpuif_req_masked & (cpuif_addr == 'h40); - decoded_reg_strb.CPTRA_SECURITY_STATE = cpuif_req_masked & (cpuif_addr == 'h44); + decoded_reg_strb.CPTRA_BOOT_STATUS = cpuif_req_masked & (cpuif_addr == 12'h38); + decoded_reg_strb.CPTRA_FLOW_STATUS = cpuif_req_masked & (cpuif_addr == 12'h3c); + decoded_reg_strb.CPTRA_RESET_REASON = cpuif_req_masked & (cpuif_addr == 12'h40); + decoded_reg_strb.CPTRA_SECURITY_STATE = cpuif_req_masked & (cpuif_addr == 12'h44); for(int i0=0; i0<5; i0++) begin - decoded_reg_strb.CPTRA_MBOX_VALID_PAUSER[i0] = cpuif_req_masked & (cpuif_addr == 'h48 + i0*'h4); + decoded_reg_strb.CPTRA_MBOX_VALID_PAUSER[i0] = cpuif_req_masked & (cpuif_addr == 12'h48 + i0*12'h4); end for(int i0=0; i0<5; i0++) begin - decoded_reg_strb.CPTRA_MBOX_PAUSER_LOCK[i0] = cpuif_req_masked & (cpuif_addr == 'h5c + i0*'h4); + decoded_reg_strb.CPTRA_MBOX_PAUSER_LOCK[i0] = cpuif_req_masked & (cpuif_addr == 12'h5c + i0*12'h4); end - decoded_reg_strb.CPTRA_TRNG_VALID_PAUSER = cpuif_req_masked & (cpuif_addr == 'h70); - decoded_reg_strb.CPTRA_TRNG_PAUSER_LOCK = cpuif_req_masked & (cpuif_addr == 'h74); + decoded_reg_strb.CPTRA_TRNG_VALID_PAUSER = cpuif_req_masked & (cpuif_addr == 12'h70); + decoded_reg_strb.CPTRA_TRNG_PAUSER_LOCK = cpuif_req_masked & (cpuif_addr == 12'h74); for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.CPTRA_TRNG_DATA[i0] = cpuif_req_masked & (cpuif_addr == 'h78 + i0*'h4); - end - decoded_reg_strb.CPTRA_TRNG_CTRL = cpuif_req_masked & (cpuif_addr == 'ha8); - decoded_reg_strb.CPTRA_TRNG_STATUS = cpuif_req_masked & (cpuif_addr == 'hac); - decoded_reg_strb.CPTRA_FUSE_WR_DONE = cpuif_req_masked & (cpuif_addr == 'hb0); - decoded_reg_strb.CPTRA_TIMER_CONFIG = cpuif_req_masked & (cpuif_addr == 'hb4); - decoded_reg_strb.CPTRA_BOOTFSM_GO = cpuif_req_masked & (cpuif_addr == 'hb8); - decoded_reg_strb.CPTRA_DBG_MANUF_SERVICE_REG = cpuif_req_masked & (cpuif_addr == 'hbc); - decoded_reg_strb.CPTRA_CLK_GATING_EN = cpuif_req_masked & (cpuif_addr == 'hc0); + decoded_reg_strb.CPTRA_TRNG_DATA[i0] = cpuif_req_masked & (cpuif_addr == 12'h78 + i0*12'h4); + end + decoded_reg_strb.CPTRA_TRNG_CTRL = cpuif_req_masked & (cpuif_addr == 12'ha8); + decoded_reg_strb.CPTRA_TRNG_STATUS = cpuif_req_masked & (cpuif_addr == 12'hac); + decoded_reg_strb.CPTRA_FUSE_WR_DONE = cpuif_req_masked & (cpuif_addr == 12'hb0); + decoded_reg_strb.CPTRA_TIMER_CONFIG = cpuif_req_masked & (cpuif_addr == 12'hb4); + decoded_reg_strb.CPTRA_BOOTFSM_GO = cpuif_req_masked & (cpuif_addr == 12'hb8); + decoded_reg_strb.CPTRA_DBG_MANUF_SERVICE_REG = cpuif_req_masked & (cpuif_addr == 12'hbc); + decoded_reg_strb.CPTRA_CLK_GATING_EN = cpuif_req_masked & (cpuif_addr == 12'hc0); for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.CPTRA_GENERIC_INPUT_WIRES[i0] = cpuif_req_masked & (cpuif_addr == 'hc4 + i0*'h4); + decoded_reg_strb.CPTRA_GENERIC_INPUT_WIRES[i0] = cpuif_req_masked & (cpuif_addr == 12'hc4 + i0*12'h4); end for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.CPTRA_GENERIC_OUTPUT_WIRES[i0] = cpuif_req_masked & (cpuif_addr == 'hcc + i0*'h4); + decoded_reg_strb.CPTRA_GENERIC_OUTPUT_WIRES[i0] = cpuif_req_masked & (cpuif_addr == 12'hcc + i0*12'h4); end - decoded_reg_strb.CPTRA_HW_REV_ID = cpuif_req_masked & (cpuif_addr == 'hd4); + decoded_reg_strb.CPTRA_HW_REV_ID = cpuif_req_masked & (cpuif_addr == 12'hd4); for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.CPTRA_FW_REV_ID[i0] = cpuif_req_masked & (cpuif_addr == 'hd8 + i0*'h4); + decoded_reg_strb.CPTRA_FW_REV_ID[i0] = cpuif_req_masked & (cpuif_addr == 12'hd8 + i0*12'h4); end - decoded_reg_strb.CPTRA_HW_CONFIG = cpuif_req_masked & (cpuif_addr == 'he0); - decoded_reg_strb.CPTRA_WDT_TIMER1_EN = cpuif_req_masked & (cpuif_addr == 'he4); - decoded_reg_strb.CPTRA_WDT_TIMER1_CTRL = cpuif_req_masked & (cpuif_addr == 'he8); + decoded_reg_strb.CPTRA_HW_CONFIG = cpuif_req_masked & (cpuif_addr == 12'he0); + decoded_reg_strb.CPTRA_WDT_TIMER1_EN = cpuif_req_masked & (cpuif_addr == 12'he4); + decoded_reg_strb.CPTRA_WDT_TIMER1_CTRL = cpuif_req_masked & (cpuif_addr == 12'he8); for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0] = cpuif_req_masked & (cpuif_addr == 'hec + i0*'h4); + decoded_reg_strb.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0] = cpuif_req_masked & (cpuif_addr == 12'hec + i0*12'h4); end - decoded_reg_strb.CPTRA_WDT_TIMER2_EN = cpuif_req_masked & (cpuif_addr == 'hf4); - decoded_reg_strb.CPTRA_WDT_TIMER2_CTRL = cpuif_req_masked & (cpuif_addr == 'hf8); + decoded_reg_strb.CPTRA_WDT_TIMER2_EN = cpuif_req_masked & (cpuif_addr == 12'hf4); + decoded_reg_strb.CPTRA_WDT_TIMER2_CTRL = cpuif_req_masked & (cpuif_addr == 12'hf8); for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0] = cpuif_req_masked & (cpuif_addr == 'hfc + i0*'h4); + decoded_reg_strb.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0] = cpuif_req_masked & (cpuif_addr == 12'hfc + i0*12'h4); end - decoded_reg_strb.CPTRA_WDT_STATUS = cpuif_req_masked & (cpuif_addr == 'h104); - decoded_reg_strb.CPTRA_FUSE_VALID_PAUSER = cpuif_req_masked & (cpuif_addr == 'h108); - decoded_reg_strb.CPTRA_FUSE_PAUSER_LOCK = cpuif_req_masked & (cpuif_addr == 'h10c); + decoded_reg_strb.CPTRA_WDT_STATUS = cpuif_req_masked & (cpuif_addr == 12'h104); + decoded_reg_strb.CPTRA_FUSE_VALID_PAUSER = cpuif_req_masked & (cpuif_addr == 12'h108); + decoded_reg_strb.CPTRA_FUSE_PAUSER_LOCK = cpuif_req_masked & (cpuif_addr == 12'h10c); for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.CPTRA_WDT_CFG[i0] = cpuif_req_masked & (cpuif_addr == 'h110 + i0*'h4); + decoded_reg_strb.CPTRA_WDT_CFG[i0] = cpuif_req_masked & (cpuif_addr == 12'h110 + i0*12'h4); end - decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_0 = cpuif_req_masked & (cpuif_addr == 'h118); - decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_1 = cpuif_req_masked & (cpuif_addr == 'h11c); + decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_0 = cpuif_req_masked & (cpuif_addr == 12'h118); + decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_1 = cpuif_req_masked & (cpuif_addr == 12'h11c); for(int i0=0; i0<2; i0++) begin - decoded_reg_strb.CPTRA_RSVD_REG[i0] = cpuif_req_masked & (cpuif_addr == 'h120 + i0*'h4); + decoded_reg_strb.CPTRA_RSVD_REG[i0] = cpuif_req_masked & (cpuif_addr == 12'h120 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.fuse_uds_seed[i0] = cpuif_req_masked & (cpuif_addr == 'h200 + i0*'h4); + decoded_reg_strb.fuse_uds_seed[i0] = cpuif_req_masked & (cpuif_addr == 12'h200 + i0*12'h4); end for(int i0=0; i0<8; i0++) begin - decoded_reg_strb.fuse_field_entropy[i0] = cpuif_req_masked & (cpuif_addr == 'h230 + i0*'h4); + decoded_reg_strb.fuse_field_entropy[i0] = cpuif_req_masked & (cpuif_addr == 12'h230 + i0*12'h4); end for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.fuse_key_manifest_pk_hash[i0] = cpuif_req_masked & (cpuif_addr == 'h250 + i0*'h4); + decoded_reg_strb.fuse_key_manifest_pk_hash[i0] = cpuif_req_masked & (cpuif_addr == 12'h250 + i0*12'h4); end - decoded_reg_strb.fuse_key_manifest_pk_hash_mask = cpuif_req_masked & (cpuif_addr == 'h280); + decoded_reg_strb.fuse_key_manifest_pk_hash_mask = cpuif_req_masked & (cpuif_addr == 12'h280); for(int i0=0; i0<12; i0++) begin - decoded_reg_strb.fuse_owner_pk_hash[i0] = cpuif_req_masked & (cpuif_addr == 'h284 + i0*'h4); + decoded_reg_strb.fuse_owner_pk_hash[i0] = cpuif_req_masked & (cpuif_addr == 12'h284 + i0*12'h4); end - decoded_reg_strb.fuse_fmc_key_manifest_svn = cpuif_req_masked & (cpuif_addr == 'h2b4); + decoded_reg_strb.fuse_fmc_key_manifest_svn = cpuif_req_masked & (cpuif_addr == 12'h2b4); for(int i0=0; i0<4; i0++) begin - decoded_reg_strb.fuse_runtime_svn[i0] = cpuif_req_masked & (cpuif_addr == 'h2b8 + i0*'h4); + decoded_reg_strb.fuse_runtime_svn[i0] = cpuif_req_masked & (cpuif_addr == 12'h2b8 + i0*12'h4); end - decoded_reg_strb.fuse_anti_rollback_disable = cpuif_req_masked & (cpuif_addr == 'h2c8); + decoded_reg_strb.fuse_anti_rollback_disable = cpuif_req_masked & (cpuif_addr == 12'h2c8); for(int i0=0; i0<24; i0++) begin - decoded_reg_strb.fuse_idevid_cert_attr[i0] = cpuif_req_masked & (cpuif_addr == 'h2cc + i0*'h4); + decoded_reg_strb.fuse_idevid_cert_attr[i0] = cpuif_req_masked & (cpuif_addr == 12'h2cc + i0*12'h4); end for(int i0=0; i0<4; i0++) begin - decoded_reg_strb.fuse_idevid_manuf_hsm_id[i0] = cpuif_req_masked & (cpuif_addr == 'h32c + i0*'h4); + decoded_reg_strb.fuse_idevid_manuf_hsm_id[i0] = cpuif_req_masked & (cpuif_addr == 12'h32c + i0*12'h4); end - decoded_reg_strb.fuse_life_cycle = cpuif_req_masked & (cpuif_addr == 'h33c); - decoded_reg_strb.fuse_lms_verify = cpuif_req_masked & (cpuif_addr == 'h340); - decoded_reg_strb.fuse_lms_revocation = cpuif_req_masked & (cpuif_addr == 'h344); - decoded_reg_strb.fuse_soc_stepping_id = cpuif_req_masked & (cpuif_addr == 'h348); + decoded_reg_strb.fuse_life_cycle = cpuif_req_masked & (cpuif_addr == 12'h33c); + decoded_reg_strb.fuse_lms_verify = cpuif_req_masked & (cpuif_addr == 12'h340); + decoded_reg_strb.fuse_lms_revocation = cpuif_req_masked & (cpuif_addr == 12'h344); + decoded_reg_strb.fuse_soc_stepping_id = cpuif_req_masked & (cpuif_addr == 12'h348); for(int i0=0; i0<8; i0++) begin - decoded_reg_strb.internal_obf_key[i0] = cpuif_req_masked & (cpuif_addr == 'h600 + i0*'h4); - end - decoded_reg_strb.internal_iccm_lock = cpuif_req_masked & (cpuif_addr == 'h620); - decoded_reg_strb.internal_fw_update_reset = cpuif_req_masked & (cpuif_addr == 'h624); - decoded_reg_strb.internal_fw_update_reset_wait_cycles = cpuif_req_masked & (cpuif_addr == 'h628); - decoded_reg_strb.internal_nmi_vector = cpuif_req_masked & (cpuif_addr == 'h62c); - decoded_reg_strb.internal_hw_error_fatal_mask = cpuif_req_masked & (cpuif_addr == 'h630); - decoded_reg_strb.internal_hw_error_non_fatal_mask = cpuif_req_masked & (cpuif_addr == 'h634); - decoded_reg_strb.internal_fw_error_fatal_mask = cpuif_req_masked & (cpuif_addr == 'h638); - decoded_reg_strb.internal_fw_error_non_fatal_mask = cpuif_req_masked & (cpuif_addr == 'h63c); - decoded_reg_strb.internal_rv_mtime_l = cpuif_req_masked & (cpuif_addr == 'h640); - decoded_reg_strb.internal_rv_mtime_h = cpuif_req_masked & (cpuif_addr == 'h644); - decoded_reg_strb.internal_rv_mtimecmp_l = cpuif_req_masked & (cpuif_addr == 'h648); - decoded_reg_strb.internal_rv_mtimecmp_h = cpuif_req_masked & (cpuif_addr == 'h64c); - decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h800); - decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h804); - decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 'h808); - decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h80c); - decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 'h810); - decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h814); - decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 'h818); - decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h81c); - decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 'h820); - decoded_reg_strb.intr_block_rf.error_internal_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h900); - decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h904); - decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h908); - decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h90c); - decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h910); - decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h914); - decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h918); - decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h91c); - decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h980); - decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h984); - decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h988); - decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h98c); - decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h990); - decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_r = cpuif_req_masked & (cpuif_addr == 'h994); - decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha00); - decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha04); - decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha08); - decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha0c); - decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha10); - decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha14); - decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha18); - decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha1c); - decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha20); - decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha24); - decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha28); - decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha2c); - decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha30); - decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 'ha34); + decoded_reg_strb.internal_obf_key[i0] = cpuif_req_masked & (cpuif_addr == 12'h600 + i0*12'h4); + end + decoded_reg_strb.internal_iccm_lock = cpuif_req_masked & (cpuif_addr == 12'h620); + decoded_reg_strb.internal_fw_update_reset = cpuif_req_masked & (cpuif_addr == 12'h624); + decoded_reg_strb.internal_fw_update_reset_wait_cycles = cpuif_req_masked & (cpuif_addr == 12'h628); + decoded_reg_strb.internal_nmi_vector = cpuif_req_masked & (cpuif_addr == 12'h62c); + decoded_reg_strb.internal_hw_error_fatal_mask = cpuif_req_masked & (cpuif_addr == 12'h630); + decoded_reg_strb.internal_hw_error_non_fatal_mask = cpuif_req_masked & (cpuif_addr == 12'h634); + decoded_reg_strb.internal_fw_error_fatal_mask = cpuif_req_masked & (cpuif_addr == 12'h638); + decoded_reg_strb.internal_fw_error_non_fatal_mask = cpuif_req_masked & (cpuif_addr == 12'h63c); + decoded_reg_strb.internal_rv_mtime_l = cpuif_req_masked & (cpuif_addr == 12'h640); + decoded_reg_strb.internal_rv_mtime_h = cpuif_req_masked & (cpuif_addr == 12'h644); + decoded_reg_strb.internal_rv_mtimecmp_l = cpuif_req_masked & (cpuif_addr == 12'h648); + decoded_reg_strb.internal_rv_mtimecmp_h = cpuif_req_masked & (cpuif_addr == 12'h64c); + decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h800); + decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h804); + decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 12'h808); + decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h80c); + decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 12'h810); + decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h814); + decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 12'h818); + decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h81c); + decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 12'h820); + decoded_reg_strb.intr_block_rf.error_internal_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h900); + decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h904); + decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h908); + decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h90c); + decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h910); + decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h914); + decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h918); + decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h91c); + decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h980); + decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h984); + decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h988); + decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h98c); + decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h990); + decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_r = cpuif_req_masked & (cpuif_addr == 12'h994); + decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha00); + decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha04); + decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha08); + decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha0c); + decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha10); + decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha14); + decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha18); + decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha1c); + decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha20); + decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha24); + decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha28); + decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha2c); + decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha30); + decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 12'ha34); end // Pass down signals to next stage @@ -330,10 +332,6 @@ module soc_ifc_reg ( assign decoded_wr_data = cpuif_wr_data; assign decoded_wr_biten = cpuif_wr_biten; - - // Writes are always granted with no error response - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; - assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Field logic //-------------------------------------------------------------------------- @@ -1911,8 +1909,10 @@ module soc_ifc_reg ( // Field: soc_ifc_reg.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_HW_ERROR_FATAL && decoded_req_is_wr) begin // SW write 1 clear next_c = field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value & ~(decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1925,7 +1925,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value <= 'h0; + field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value <= 1'h0; end else if(field_combo.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.load_next) begin field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value <= field_combo.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.next; end @@ -1933,8 +1933,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value = field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value; // Field: soc_ifc_reg.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_HW_ERROR_FATAL && decoded_req_is_wr) begin // SW write 1 clear next_c = field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value & ~(decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -1947,7 +1949,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value <= 'h0; + field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value <= 1'h0; end else if(field_combo.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.load_next) begin field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value <= field_combo.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.next; end @@ -1955,8 +1957,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value = field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value; // Field: soc_ifc_reg.CPTRA_HW_ERROR_FATAL.nmi_pin always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_HW_ERROR_FATAL && decoded_req_is_wr) begin // SW write 1 clear next_c = field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value & ~(decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -1969,7 +1973,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value <= 'h0; + field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value <= 1'h0; end else if(field_combo.CPTRA_HW_ERROR_FATAL.nmi_pin.load_next) begin field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value <= field_combo.CPTRA_HW_ERROR_FATAL.nmi_pin.next; end @@ -1977,8 +1981,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_HW_ERROR_FATAL.nmi_pin.value = field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value; // Field: soc_ifc_reg.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && decoded_req_is_wr) begin // SW write 1 clear next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value & ~(decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -1991,7 +1997,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value <= 'h0; + field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value <= 1'h0; end else if(field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.load_next) begin field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value <= field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.next; end @@ -1999,8 +2005,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value; // Field: soc_ifc_reg.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && decoded_req_is_wr) begin // SW write 1 clear next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value & ~(decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -2013,7 +2021,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value <= 'h0; + field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value <= 1'h0; end else if(field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.load_next) begin field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value <= field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.next; end @@ -2021,8 +2029,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value; // Field: soc_ifc_reg.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && decoded_req_is_wr) begin // SW write 1 clear next_c = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value & ~(decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -2035,7 +2045,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value <= 'h0; + field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value <= 1'h0; end else if(field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.load_next) begin field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value <= field_combo.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.next; end @@ -2043,8 +2053,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value = field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value; // Field: soc_ifc_reg.CPTRA_FW_ERROR_FATAL.error_code always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_FW_ERROR_FATAL.error_code.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FW_ERROR_FATAL.error_code.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FW_ERROR_FATAL && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_FW_ERROR_FATAL.error_code.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2057,7 +2069,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FW_ERROR_FATAL.error_code.value <= 'h0; + field_storage.CPTRA_FW_ERROR_FATAL.error_code.value <= 32'h0; end else if(field_combo.CPTRA_FW_ERROR_FATAL.error_code.load_next) begin field_storage.CPTRA_FW_ERROR_FATAL.error_code.value <= field_combo.CPTRA_FW_ERROR_FATAL.error_code.next; end @@ -2066,8 +2078,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_FW_ERROR_FATAL.error_code.swmod = decoded_reg_strb.CPTRA_FW_ERROR_FATAL && decoded_req_is_wr; // Field: soc_ifc_reg.CPTRA_FW_ERROR_NON_FATAL.error_code always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_FW_ERROR_NON_FATAL.error_code.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FW_ERROR_NON_FATAL.error_code.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FW_ERROR_NON_FATAL && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_FW_ERROR_NON_FATAL.error_code.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2080,7 +2094,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FW_ERROR_NON_FATAL.error_code.value <= 'h0; + field_storage.CPTRA_FW_ERROR_NON_FATAL.error_code.value <= 32'h0; end else if(field_combo.CPTRA_FW_ERROR_NON_FATAL.error_code.load_next) begin field_storage.CPTRA_FW_ERROR_NON_FATAL.error_code.value <= field_combo.CPTRA_FW_ERROR_NON_FATAL.error_code.next; end @@ -2089,8 +2103,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_FW_ERROR_NON_FATAL.error_code.swmod = decoded_reg_strb.CPTRA_FW_ERROR_NON_FATAL && decoded_req_is_wr; // Field: soc_ifc_reg.CPTRA_HW_ERROR_ENC.error_code always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_HW_ERROR_ENC.error_code.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_HW_ERROR_ENC.error_code.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_HW_ERROR_ENC && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_HW_ERROR_ENC.error_code.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2100,7 +2116,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_HW_ERROR_ENC.error_code.value <= 'h0; + field_storage.CPTRA_HW_ERROR_ENC.error_code.value <= 32'h0; end else if(field_combo.CPTRA_HW_ERROR_ENC.error_code.load_next) begin field_storage.CPTRA_HW_ERROR_ENC.error_code.value <= field_combo.CPTRA_HW_ERROR_ENC.error_code.next; end @@ -2108,8 +2124,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_HW_ERROR_ENC.error_code.value = field_storage.CPTRA_HW_ERROR_ENC.error_code.value; // Field: soc_ifc_reg.CPTRA_FW_ERROR_ENC.error_code always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_FW_ERROR_ENC.error_code.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FW_ERROR_ENC.error_code.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FW_ERROR_ENC && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_FW_ERROR_ENC.error_code.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2119,7 +2137,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FW_ERROR_ENC.error_code.value <= 'h0; + field_storage.CPTRA_FW_ERROR_ENC.error_code.value <= 32'h0; end else if(field_combo.CPTRA_FW_ERROR_ENC.error_code.load_next) begin field_storage.CPTRA_FW_ERROR_ENC.error_code.value <= field_combo.CPTRA_FW_ERROR_ENC.error_code.next; end @@ -2128,8 +2146,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<8; i0++) begin // Field: soc_ifc_reg.CPTRA_FW_EXTENDED_ERROR_INFO[].error_info always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[i0].error_info.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[i0].error_info.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FW_EXTENDED_ERROR_INFO[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[i0].error_info.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2139,7 +2159,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[i0].error_info.value <= 'h0; + field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[i0].error_info.value <= 32'h0; end else if(field_combo.CPTRA_FW_EXTENDED_ERROR_INFO[i0].error_info.load_next) begin field_storage.CPTRA_FW_EXTENDED_ERROR_INFO[i0].error_info.value <= field_combo.CPTRA_FW_EXTENDED_ERROR_INFO[i0].error_info.next; end @@ -2148,8 +2168,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.CPTRA_BOOT_STATUS.status always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_BOOT_STATUS.status.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_BOOT_STATUS.status.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_BOOT_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_BOOT_STATUS.status.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2159,7 +2181,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_BOOT_STATUS.status.value <= 'h0; + field_storage.CPTRA_BOOT_STATUS.status.value <= 32'h0; end else if(field_combo.CPTRA_BOOT_STATUS.status.load_next) begin field_storage.CPTRA_BOOT_STATUS.status.value <= field_combo.CPTRA_BOOT_STATUS.status.next; end @@ -2167,8 +2189,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_BOOT_STATUS.status.value = field_storage.CPTRA_BOOT_STATUS.status.value; // Field: soc_ifc_reg.CPTRA_FLOW_STATUS.status always_comb begin - automatic logic [23:0] next_c = field_storage.CPTRA_FLOW_STATUS.status.value; - automatic logic load_next_c = '0; + automatic logic [23:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FLOW_STATUS.status.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FLOW_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_FLOW_STATUS.status.value & ~decoded_wr_biten[23:0]) | (decoded_wr_data[23:0] & decoded_wr_biten[23:0]); load_next_c = '1; @@ -2178,15 +2202,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_FLOW_STATUS.status.value <= 'h0; + field_storage.CPTRA_FLOW_STATUS.status.value <= 24'h0; end else if(field_combo.CPTRA_FLOW_STATUS.status.load_next) begin field_storage.CPTRA_FLOW_STATUS.status.value <= field_combo.CPTRA_FLOW_STATUS.status.next; end end // Field: soc_ifc_reg.CPTRA_FLOW_STATUS.idevid_csr_ready always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FLOW_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value & ~decoded_wr_biten[24:24]) | (decoded_wr_data[24:24] & decoded_wr_biten[24:24]); load_next_c = '1; @@ -2196,7 +2222,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value <= 'h0; + field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value <= 1'h0; end else if(field_combo.CPTRA_FLOW_STATUS.idevid_csr_ready.load_next) begin field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value <= field_combo.CPTRA_FLOW_STATUS.idevid_csr_ready.next; end @@ -2204,8 +2230,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_FLOW_STATUS.idevid_csr_ready.value = field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value; // Field: soc_ifc_reg.CPTRA_FLOW_STATUS.ready_for_fw always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FLOW_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value & ~decoded_wr_biten[28:28]) | (decoded_wr_data[28:28] & decoded_wr_biten[28:28]); load_next_c = '1; @@ -2215,7 +2243,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value <= 'h0; + field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value <= 1'h0; end else if(field_combo.CPTRA_FLOW_STATUS.ready_for_fw.load_next) begin field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value <= field_combo.CPTRA_FLOW_STATUS.ready_for_fw.next; end @@ -2223,8 +2251,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_FLOW_STATUS.ready_for_fw.value = field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value; // Field: soc_ifc_reg.CPTRA_FLOW_STATUS.ready_for_runtime always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_FLOW_STATUS.ready_for_runtime.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FLOW_STATUS.ready_for_runtime.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FLOW_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_FLOW_STATUS.ready_for_runtime.value & ~decoded_wr_biten[29:29]) | (decoded_wr_data[29:29] & decoded_wr_biten[29:29]); load_next_c = '1; @@ -2234,7 +2264,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_FLOW_STATUS.ready_for_runtime.value <= 'h0; + field_storage.CPTRA_FLOW_STATUS.ready_for_runtime.value <= 1'h0; end else if(field_combo.CPTRA_FLOW_STATUS.ready_for_runtime.load_next) begin field_storage.CPTRA_FLOW_STATUS.ready_for_runtime.value <= field_combo.CPTRA_FLOW_STATUS.ready_for_runtime.next; end @@ -2242,8 +2272,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_FLOW_STATUS.ready_for_runtime.value = field_storage.CPTRA_FLOW_STATUS.ready_for_runtime.value; // Field: soc_ifc_reg.CPTRA_FLOW_STATUS.mailbox_flow_done always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_FLOW_STATUS.mailbox_flow_done.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FLOW_STATUS.mailbox_flow_done.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FLOW_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_FLOW_STATUS.mailbox_flow_done.value & ~decoded_wr_biten[31:31]) | (decoded_wr_data[31:31] & decoded_wr_biten[31:31]); load_next_c = '1; @@ -2253,7 +2285,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_FLOW_STATUS.mailbox_flow_done.value <= 'h0; + field_storage.CPTRA_FLOW_STATUS.mailbox_flow_done.value <= 1'h0; end else if(field_combo.CPTRA_FLOW_STATUS.mailbox_flow_done.load_next) begin field_storage.CPTRA_FLOW_STATUS.mailbox_flow_done.value <= field_combo.CPTRA_FLOW_STATUS.mailbox_flow_done.next; end @@ -2261,8 +2293,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_FLOW_STATUS.mailbox_flow_done.value = field_storage.CPTRA_FLOW_STATUS.mailbox_flow_done.value; // Field: soc_ifc_reg.CPTRA_RESET_REASON.FW_UPD_RESET always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_RESET_REASON.FW_UPD_RESET.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_RESET_REASON.FW_UPD_RESET.value; + load_next_c = '0; if(hwif_in.CPTRA_RESET_REASON.FW_UPD_RESET.we) begin // HW Write - we next_c = hwif_in.CPTRA_RESET_REASON.FW_UPD_RESET.next; load_next_c = '1; @@ -2272,7 +2306,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_RESET_REASON.FW_UPD_RESET.value <= 'h0; + field_storage.CPTRA_RESET_REASON.FW_UPD_RESET.value <= 1'h0; end else if(field_combo.CPTRA_RESET_REASON.FW_UPD_RESET.load_next) begin field_storage.CPTRA_RESET_REASON.FW_UPD_RESET.value <= field_combo.CPTRA_RESET_REASON.FW_UPD_RESET.next; end @@ -2280,18 +2314,20 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_RESET_REASON.FW_UPD_RESET.value = field_storage.CPTRA_RESET_REASON.FW_UPD_RESET.value; // Field: soc_ifc_reg.CPTRA_RESET_REASON.WARM_RESET always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_RESET_REASON.WARM_RESET.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.CPTRA_RESET_REASON.WARM_RESET.next; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_RESET_REASON.WARM_RESET.value; + load_next_c = '0; + + // HW Write + next_c = hwif_in.CPTRA_RESET_REASON.WARM_RESET.next; + load_next_c = '1; field_combo.CPTRA_RESET_REASON.WARM_RESET.next = next_c; field_combo.CPTRA_RESET_REASON.WARM_RESET.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_RESET_REASON.WARM_RESET.value <= 'h0; + field_storage.CPTRA_RESET_REASON.WARM_RESET.value <= 1'h0; end else if(field_combo.CPTRA_RESET_REASON.WARM_RESET.load_next) begin field_storage.CPTRA_RESET_REASON.WARM_RESET.value <= field_combo.CPTRA_RESET_REASON.WARM_RESET.next; end @@ -2300,8 +2336,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<5; i0++) begin // Field: soc_ifc_reg.CPTRA_MBOX_VALID_PAUSER[].PAUSER always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_MBOX_VALID_PAUSER[i0] && decoded_req_is_wr && !(hwif_in.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.swwel)) begin // SW write next_c = (field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2311,7 +2349,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value <= 'hffffffff; + field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value <= 32'hffffffff; end else if(field_combo.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.load_next) begin field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value <= field_combo.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.next; end @@ -2321,8 +2359,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<5; i0++) begin // Field: soc_ifc_reg.CPTRA_MBOX_PAUSER_LOCK[].LOCK always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_MBOX_PAUSER_LOCK[i0] && decoded_req_is_wr && !(hwif_in.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.swwel)) begin // SW write next_c = (field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -2332,7 +2372,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value <= 'h0; + field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value <= 1'h0; end else if(field_combo.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.load_next) begin field_storage.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.value <= field_combo.CPTRA_MBOX_PAUSER_LOCK[i0].LOCK.next; end @@ -2341,8 +2381,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.CPTRA_TRNG_VALID_PAUSER.PAUSER always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_TRNG_VALID_PAUSER && decoded_req_is_wr && !(hwif_in.CPTRA_TRNG_VALID_PAUSER.PAUSER.swwel)) begin // SW write next_c = (field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2352,7 +2394,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value <= 'hffffffff; + field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value <= 32'hffffffff; end else if(field_combo.CPTRA_TRNG_VALID_PAUSER.PAUSER.load_next) begin field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value <= field_combo.CPTRA_TRNG_VALID_PAUSER.PAUSER.next; end @@ -2360,8 +2402,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_TRNG_VALID_PAUSER.PAUSER.value = field_storage.CPTRA_TRNG_VALID_PAUSER.PAUSER.value; // Field: soc_ifc_reg.CPTRA_TRNG_PAUSER_LOCK.LOCK always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_TRNG_PAUSER_LOCK && decoded_req_is_wr && !(hwif_in.CPTRA_TRNG_PAUSER_LOCK.LOCK.swwel)) begin // SW write next_c = (field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -2371,7 +2415,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value <= 'h0; + field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value <= 1'h0; end else if(field_combo.CPTRA_TRNG_PAUSER_LOCK.LOCK.load_next) begin field_storage.CPTRA_TRNG_PAUSER_LOCK.LOCK.value <= field_combo.CPTRA_TRNG_PAUSER_LOCK.LOCK.next; end @@ -2380,8 +2424,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: soc_ifc_reg.CPTRA_TRNG_DATA[].DATA always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_TRNG_DATA[i0].DATA.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_TRNG_DATA[i0].DATA.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_TRNG_DATA[i0] && decoded_req_is_wr && hwif_in.CPTRA_TRNG_DATA[i0].DATA.swwe) begin // SW write next_c = (field_storage.CPTRA_TRNG_DATA[i0].DATA.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2394,7 +2440,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_TRNG_DATA[i0].DATA.value <= 'h0; + field_storage.CPTRA_TRNG_DATA[i0].DATA.value <= 32'h0; end else if(field_combo.CPTRA_TRNG_DATA[i0].DATA.load_next) begin field_storage.CPTRA_TRNG_DATA[i0].DATA.value <= field_combo.CPTRA_TRNG_DATA[i0].DATA.next; end @@ -2403,12 +2449,14 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.CPTRA_TRNG_CTRL.clear always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_TRNG_CTRL.clear.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_TRNG_CTRL.clear.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_TRNG_CTRL && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_TRNG_CTRL.clear.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -2417,7 +2465,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_TRNG_CTRL.clear.value <= 'h0; + field_storage.CPTRA_TRNG_CTRL.clear.value <= 1'h0; end else if(field_combo.CPTRA_TRNG_CTRL.clear.load_next) begin field_storage.CPTRA_TRNG_CTRL.clear.value <= field_combo.CPTRA_TRNG_CTRL.clear.next; end @@ -2425,8 +2473,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_TRNG_CTRL.clear.value = field_storage.CPTRA_TRNG_CTRL.clear.value; // Field: soc_ifc_reg.CPTRA_TRNG_STATUS.DATA_REQ always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_TRNG_STATUS.DATA_REQ.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_TRNG_STATUS.DATA_REQ.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_TRNG_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_TRNG_STATUS.DATA_REQ.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -2436,7 +2486,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_TRNG_STATUS.DATA_REQ.value <= 'h0; + field_storage.CPTRA_TRNG_STATUS.DATA_REQ.value <= 1'h0; end else if(field_combo.CPTRA_TRNG_STATUS.DATA_REQ.load_next) begin field_storage.CPTRA_TRNG_STATUS.DATA_REQ.value <= field_combo.CPTRA_TRNG_STATUS.DATA_REQ.next; end @@ -2444,8 +2494,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_TRNG_STATUS.DATA_REQ.value = field_storage.CPTRA_TRNG_STATUS.DATA_REQ.value; // Field: soc_ifc_reg.CPTRA_TRNG_STATUS.DATA_WR_DONE always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_TRNG_STATUS.DATA_WR_DONE.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_TRNG_STATUS.DATA_WR_DONE.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_TRNG_STATUS && decoded_req_is_wr && hwif_in.CPTRA_TRNG_STATUS.DATA_WR_DONE.swwe) begin // SW write next_c = (field_storage.CPTRA_TRNG_STATUS.DATA_WR_DONE.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -2458,15 +2510,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_TRNG_STATUS.DATA_WR_DONE.value <= 'h0; + field_storage.CPTRA_TRNG_STATUS.DATA_WR_DONE.value <= 1'h0; end else if(field_combo.CPTRA_TRNG_STATUS.DATA_WR_DONE.load_next) begin field_storage.CPTRA_TRNG_STATUS.DATA_WR_DONE.value <= field_combo.CPTRA_TRNG_STATUS.DATA_WR_DONE.next; end end // Field: soc_ifc_reg.CPTRA_FUSE_WR_DONE.done always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_FUSE_WR_DONE.done.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FUSE_WR_DONE.done.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FUSE_WR_DONE && decoded_req_is_wr && hwif_in.CPTRA_FUSE_WR_DONE.done.swwe) begin // SW write next_c = (field_storage.CPTRA_FUSE_WR_DONE.done.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -2476,7 +2530,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FUSE_WR_DONE.done.value <= 'h0; + field_storage.CPTRA_FUSE_WR_DONE.done.value <= 1'h0; end else if(field_combo.CPTRA_FUSE_WR_DONE.done.load_next) begin field_storage.CPTRA_FUSE_WR_DONE.done.value <= field_combo.CPTRA_FUSE_WR_DONE.done.next; end @@ -2485,8 +2539,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_FUSE_WR_DONE.done.swmod = decoded_reg_strb.CPTRA_FUSE_WR_DONE && decoded_req_is_wr; // Field: soc_ifc_reg.CPTRA_TIMER_CONFIG.clk_period always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_TIMER_CONFIG.clk_period.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_TIMER_CONFIG.clk_period.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_TIMER_CONFIG && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_TIMER_CONFIG.clk_period.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2496,15 +2552,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_TIMER_CONFIG.clk_period.value <= 'h0; + field_storage.CPTRA_TIMER_CONFIG.clk_period.value <= 32'h0; end else if(field_combo.CPTRA_TIMER_CONFIG.clk_period.load_next) begin field_storage.CPTRA_TIMER_CONFIG.clk_period.value <= field_combo.CPTRA_TIMER_CONFIG.clk_period.next; end end // Field: soc_ifc_reg.CPTRA_BOOTFSM_GO.GO always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_BOOTFSM_GO.GO.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_BOOTFSM_GO.GO.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_BOOTFSM_GO && decoded_req_is_wr && hwif_in.soc_req) begin // SW write next_c = (field_storage.CPTRA_BOOTFSM_GO.GO.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -2517,7 +2575,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_BOOTFSM_GO.GO.value <= 'h0; + field_storage.CPTRA_BOOTFSM_GO.GO.value <= 1'h0; end else if(field_combo.CPTRA_BOOTFSM_GO.GO.load_next) begin field_storage.CPTRA_BOOTFSM_GO.GO.value <= field_combo.CPTRA_BOOTFSM_GO.GO.next; end @@ -2525,8 +2583,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_BOOTFSM_GO.GO.value = field_storage.CPTRA_BOOTFSM_GO.GO.value; // Field: soc_ifc_reg.CPTRA_DBG_MANUF_SERVICE_REG.DATA always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_DBG_MANUF_SERVICE_REG && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2539,7 +2599,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value <= 'h0; + field_storage.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value <= 32'h0; end else if(field_combo.CPTRA_DBG_MANUF_SERVICE_REG.DATA.load_next) begin field_storage.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value <= field_combo.CPTRA_DBG_MANUF_SERVICE_REG.DATA.next; end @@ -2547,8 +2607,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value = field_storage.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value; // Field: soc_ifc_reg.CPTRA_CLK_GATING_EN.clk_gating_en always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_CLK_GATING_EN.clk_gating_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_CLK_GATING_EN.clk_gating_en.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_CLK_GATING_EN && decoded_req_is_wr && hwif_in.soc_req) begin // SW write next_c = (field_storage.CPTRA_CLK_GATING_EN.clk_gating_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -2558,7 +2620,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_CLK_GATING_EN.clk_gating_en.value <= 'h0; + field_storage.CPTRA_CLK_GATING_EN.clk_gating_en.value <= 1'h0; end else if(field_combo.CPTRA_CLK_GATING_EN.clk_gating_en.load_next) begin field_storage.CPTRA_CLK_GATING_EN.clk_gating_en.value <= field_combo.CPTRA_CLK_GATING_EN.clk_gating_en.next; end @@ -2567,18 +2629,20 @@ module soc_ifc_reg ( for(genvar i0=0; i0<2; i0++) begin // Field: soc_ifc_reg.CPTRA_GENERIC_INPUT_WIRES[].generic_wires always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_in.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.next; - load_next_c = '1; - end + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.value; + load_next_c = '0; + + // HW Write + next_c = hwif_in.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.next; + load_next_c = '1; field_combo.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.next = next_c; field_combo.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.value <= 'h0; + field_storage.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.value <= 32'h0; end else if(field_combo.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.load_next) begin field_storage.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.value <= field_combo.CPTRA_GENERIC_INPUT_WIRES[i0].generic_wires.next; end @@ -2588,8 +2652,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<2; i0++) begin // Field: soc_ifc_reg.CPTRA_GENERIC_OUTPUT_WIRES[].generic_wires always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_GENERIC_OUTPUT_WIRES[i0] && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2599,7 +2665,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value <= 'h0; + field_storage.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value <= 32'h0; end else if(field_combo.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.load_next) begin field_storage.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value <= field_combo.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.next; end @@ -2609,8 +2675,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<2; i0++) begin // Field: soc_ifc_reg.CPTRA_FW_REV_ID[].REV_ID always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_FW_REV_ID[i0].REV_ID.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FW_REV_ID[i0].REV_ID.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FW_REV_ID[i0] && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_FW_REV_ID[i0].REV_ID.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2620,7 +2688,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_FW_REV_ID[i0].REV_ID.value <= 'h0; + field_storage.CPTRA_FW_REV_ID[i0].REV_ID.value <= 32'h0; end else if(field_combo.CPTRA_FW_REV_ID[i0].REV_ID.load_next) begin field_storage.CPTRA_FW_REV_ID[i0].REV_ID.value <= field_combo.CPTRA_FW_REV_ID[i0].REV_ID.next; end @@ -2629,8 +2697,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.CPTRA_WDT_TIMER1_EN.timer1_en always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_WDT_TIMER1_EN && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -2640,7 +2710,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value <= 'h0; + field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value <= 1'h0; end else if(field_combo.CPTRA_WDT_TIMER1_EN.timer1_en.load_next) begin field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value <= field_combo.CPTRA_WDT_TIMER1_EN.timer1_en.next; end @@ -2648,12 +2718,14 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_WDT_TIMER1_EN.timer1_en.value = field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value; // Field: soc_ifc_reg.CPTRA_WDT_TIMER1_CTRL.timer1_restart always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_WDT_TIMER1_CTRL && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -2662,7 +2734,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value <= 'h0; + field_storage.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value <= 1'h0; end else if(field_combo.CPTRA_WDT_TIMER1_CTRL.timer1_restart.load_next) begin field_storage.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value <= field_combo.CPTRA_WDT_TIMER1_CTRL.timer1_restart.next; end @@ -2671,8 +2743,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<2; i0++) begin // Field: soc_ifc_reg.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[].timer1_timeout_period always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].timer1_timeout_period.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].timer1_timeout_period.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0] && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].timer1_timeout_period.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2682,7 +2756,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].timer1_timeout_period.value <= 'hffffffff; + field_storage.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].timer1_timeout_period.value <= 32'hffffffff; end else if(field_combo.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].timer1_timeout_period.load_next) begin field_storage.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].timer1_timeout_period.value <= field_combo.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i0].timer1_timeout_period.next; end @@ -2691,8 +2765,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.CPTRA_WDT_TIMER2_EN.timer2_en always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_WDT_TIMER2_EN.timer2_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_WDT_TIMER2_EN.timer2_en.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_WDT_TIMER2_EN && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_WDT_TIMER2_EN.timer2_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -2702,7 +2778,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_WDT_TIMER2_EN.timer2_en.value <= 'h0; + field_storage.CPTRA_WDT_TIMER2_EN.timer2_en.value <= 1'h0; end else if(field_combo.CPTRA_WDT_TIMER2_EN.timer2_en.load_next) begin field_storage.CPTRA_WDT_TIMER2_EN.timer2_en.value <= field_combo.CPTRA_WDT_TIMER2_EN.timer2_en.next; end @@ -2710,12 +2786,14 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_WDT_TIMER2_EN.timer2_en.value = field_storage.CPTRA_WDT_TIMER2_EN.timer2_en.value; // Field: soc_ifc_reg.CPTRA_WDT_TIMER2_CTRL.timer2_restart always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_WDT_TIMER2_CTRL.timer2_restart.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_WDT_TIMER2_CTRL.timer2_restart.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_WDT_TIMER2_CTRL && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_WDT_TIMER2_CTRL.timer2_restart.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -2724,7 +2802,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_WDT_TIMER2_CTRL.timer2_restart.value <= 'h0; + field_storage.CPTRA_WDT_TIMER2_CTRL.timer2_restart.value <= 1'h0; end else if(field_combo.CPTRA_WDT_TIMER2_CTRL.timer2_restart.load_next) begin field_storage.CPTRA_WDT_TIMER2_CTRL.timer2_restart.value <= field_combo.CPTRA_WDT_TIMER2_CTRL.timer2_restart.next; end @@ -2733,8 +2811,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<2; i0++) begin // Field: soc_ifc_reg.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[].timer2_timeout_period always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].timer2_timeout_period.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].timer2_timeout_period.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0] && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].timer2_timeout_period.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2744,7 +2824,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].timer2_timeout_period.value <= 'hffffffff; + field_storage.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].timer2_timeout_period.value <= 32'hffffffff; end else if(field_combo.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].timer2_timeout_period.load_next) begin field_storage.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].timer2_timeout_period.value <= field_combo.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i0].timer2_timeout_period.next; end @@ -2753,12 +2833,14 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.CPTRA_WDT_STATUS.t1_timeout always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_WDT_STATUS.t1_timeout.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_WDT_STATUS.t1_timeout.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_WDT_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_WDT_STATUS.t1_timeout.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // HW Write + end else begin // HW Write next_c = hwif_in.CPTRA_WDT_STATUS.t1_timeout.next; load_next_c = '1; end @@ -2767,7 +2849,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_WDT_STATUS.t1_timeout.value <= 'h0; + field_storage.CPTRA_WDT_STATUS.t1_timeout.value <= 1'h0; end else if(field_combo.CPTRA_WDT_STATUS.t1_timeout.load_next) begin field_storage.CPTRA_WDT_STATUS.t1_timeout.value <= field_combo.CPTRA_WDT_STATUS.t1_timeout.next; end @@ -2775,12 +2857,14 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_WDT_STATUS.t1_timeout.value = field_storage.CPTRA_WDT_STATUS.t1_timeout.value; // Field: soc_ifc_reg.CPTRA_WDT_STATUS.t2_timeout always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_WDT_STATUS.t2_timeout.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_WDT_STATUS.t2_timeout.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_WDT_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.CPTRA_WDT_STATUS.t2_timeout.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // HW Write + end else begin // HW Write next_c = hwif_in.CPTRA_WDT_STATUS.t2_timeout.next; load_next_c = '1; end @@ -2789,7 +2873,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_WDT_STATUS.t2_timeout.value <= 'h0; + field_storage.CPTRA_WDT_STATUS.t2_timeout.value <= 1'h0; end else if(field_combo.CPTRA_WDT_STATUS.t2_timeout.load_next) begin field_storage.CPTRA_WDT_STATUS.t2_timeout.value <= field_combo.CPTRA_WDT_STATUS.t2_timeout.next; end @@ -2797,8 +2881,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_WDT_STATUS.t2_timeout.value = field_storage.CPTRA_WDT_STATUS.t2_timeout.value; // Field: soc_ifc_reg.CPTRA_FUSE_VALID_PAUSER.PAUSER always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FUSE_VALID_PAUSER && decoded_req_is_wr && !(hwif_in.CPTRA_FUSE_VALID_PAUSER.PAUSER.swwel)) begin // SW write next_c = (field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2808,7 +2894,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value <= 'hffffffff; + field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value <= 32'hffffffff; end else if(field_combo.CPTRA_FUSE_VALID_PAUSER.PAUSER.load_next) begin field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value <= field_combo.CPTRA_FUSE_VALID_PAUSER.PAUSER.next; end @@ -2816,8 +2902,10 @@ module soc_ifc_reg ( assign hwif_out.CPTRA_FUSE_VALID_PAUSER.PAUSER.value = field_storage.CPTRA_FUSE_VALID_PAUSER.PAUSER.value; // Field: soc_ifc_reg.CPTRA_FUSE_PAUSER_LOCK.LOCK always_comb begin - automatic logic [0:0] next_c = field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_FUSE_PAUSER_LOCK && decoded_req_is_wr && !(hwif_in.CPTRA_FUSE_PAUSER_LOCK.LOCK.swwel)) begin // SW write next_c = (field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -2827,7 +2915,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value <= 'h0; + field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value <= 1'h0; end else if(field_combo.CPTRA_FUSE_PAUSER_LOCK.LOCK.load_next) begin field_storage.CPTRA_FUSE_PAUSER_LOCK.LOCK.value <= field_combo.CPTRA_FUSE_PAUSER_LOCK.LOCK.next; end @@ -2836,8 +2924,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<2; i0++) begin // Field: soc_ifc_reg.CPTRA_WDT_CFG[].TIMEOUT always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_WDT_CFG[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2847,7 +2937,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value <= 'h0; + field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value <= 32'h0; end else if(field_combo.CPTRA_WDT_CFG[i0].TIMEOUT.load_next) begin field_storage.CPTRA_WDT_CFG[i0].TIMEOUT.value <= field_combo.CPTRA_WDT_CFG[i0].TIMEOUT.next; end @@ -2855,8 +2945,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold always_comb begin - automatic logic [15:0] next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.value; - automatic logic load_next_c = '0; + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_0 && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]); load_next_c = '1; @@ -2866,15 +2958,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.value <= 'h0; + field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.value <= 16'h0; end else if(field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.load_next) begin field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.value <= field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_0.low_threshold.next; end end // Field: soc_ifc_reg.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold always_comb begin - automatic logic [15:0] next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.value; - automatic logic load_next_c = '0; + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_0 && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.value & ~decoded_wr_biten[31:16]) | (decoded_wr_data[31:16] & decoded_wr_biten[31:16]); load_next_c = '1; @@ -2884,15 +2978,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.value <= 'h0; + field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.value <= 16'h0; end else if(field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.load_next) begin field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.value <= field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_0.high_threshold.next; end end // Field: soc_ifc_reg.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count always_comb begin - automatic logic [15:0] next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.value; - automatic logic load_next_c = '0; + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_1 && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]); load_next_c = '1; @@ -2902,15 +2998,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.value <= 'h0; + field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.value <= 16'h0; end else if(field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.load_next) begin field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.value <= field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_1.repetition_count.next; end end // Field: soc_ifc_reg.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD always_comb begin - automatic logic [15:0] next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.value; - automatic logic load_next_c = '0; + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_iTRNG_ENTROPY_CONFIG_1 && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.value & ~decoded_wr_biten[31:16]) | (decoded_wr_data[31:16] & decoded_wr_biten[31:16]); load_next_c = '1; @@ -2920,7 +3018,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.value <= 'h0; + field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.value <= 16'h0; end else if(field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.load_next) begin field_storage.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.value <= field_combo.CPTRA_iTRNG_ENTROPY_CONFIG_1.RSVD.next; end @@ -2928,8 +3026,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<2; i0++) begin // Field: soc_ifc_reg.CPTRA_RSVD_REG[].RSVD always_comb begin - automatic logic [31:0] next_c = field_storage.CPTRA_RSVD_REG[i0].RSVD.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.CPTRA_RSVD_REG[i0].RSVD.value; + load_next_c = '0; if(decoded_reg_strb.CPTRA_RSVD_REG[i0] && decoded_req_is_wr) begin // SW write next_c = (field_storage.CPTRA_RSVD_REG[i0].RSVD.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2939,7 +3039,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.CPTRA_RSVD_REG[i0].RSVD.value <= 'h0; + field_storage.CPTRA_RSVD_REG[i0].RSVD.value <= 32'h0; end else if(field_combo.CPTRA_RSVD_REG[i0].RSVD.load_next) begin field_storage.CPTRA_RSVD_REG[i0].RSVD.value <= field_combo.CPTRA_RSVD_REG[i0].RSVD.next; end @@ -2948,8 +3048,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: soc_ifc_reg.fuse_uds_seed[].seed always_comb begin - automatic logic [31:0] next_c = field_storage.fuse_uds_seed[i0].seed.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_uds_seed[i0].seed.value; + load_next_c = '0; if(decoded_reg_strb.fuse_uds_seed[i0] && decoded_req_is_wr && !(hwif_in.fuse_uds_seed[i0].seed.swwel)) begin // SW write next_c = (field_storage.fuse_uds_seed[i0].seed.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2962,7 +3064,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_uds_seed[i0].seed.value <= 'h0; + field_storage.fuse_uds_seed[i0].seed.value <= 32'h0; end else if(field_combo.fuse_uds_seed[i0].seed.load_next) begin field_storage.fuse_uds_seed[i0].seed.value <= field_combo.fuse_uds_seed[i0].seed.next; end @@ -2972,8 +3074,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<8; i0++) begin // Field: soc_ifc_reg.fuse_field_entropy[].seed always_comb begin - automatic logic [31:0] next_c = field_storage.fuse_field_entropy[i0].seed.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_field_entropy[i0].seed.value; + load_next_c = '0; if(decoded_reg_strb.fuse_field_entropy[i0] && decoded_req_is_wr && !(hwif_in.fuse_field_entropy[i0].seed.swwel)) begin // SW write next_c = (field_storage.fuse_field_entropy[i0].seed.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -2986,7 +3090,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_field_entropy[i0].seed.value <= 'h0; + field_storage.fuse_field_entropy[i0].seed.value <= 32'h0; end else if(field_combo.fuse_field_entropy[i0].seed.load_next) begin field_storage.fuse_field_entropy[i0].seed.value <= field_combo.fuse_field_entropy[i0].seed.next; end @@ -2996,8 +3100,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: soc_ifc_reg.fuse_key_manifest_pk_hash[].hash always_comb begin - automatic logic [31:0] next_c = field_storage.fuse_key_manifest_pk_hash[i0].hash.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_key_manifest_pk_hash[i0].hash.value; + load_next_c = '0; if(decoded_reg_strb.fuse_key_manifest_pk_hash[i0] && decoded_req_is_wr && !(hwif_in.fuse_key_manifest_pk_hash[i0].hash.swwel)) begin // SW write next_c = (field_storage.fuse_key_manifest_pk_hash[i0].hash.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3007,7 +3113,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_key_manifest_pk_hash[i0].hash.value <= 'h0; + field_storage.fuse_key_manifest_pk_hash[i0].hash.value <= 32'h0; end else if(field_combo.fuse_key_manifest_pk_hash[i0].hash.load_next) begin field_storage.fuse_key_manifest_pk_hash[i0].hash.value <= field_combo.fuse_key_manifest_pk_hash[i0].hash.next; end @@ -3016,8 +3122,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.fuse_key_manifest_pk_hash_mask.mask always_comb begin - automatic logic [3:0] next_c = field_storage.fuse_key_manifest_pk_hash_mask.mask.value; - automatic logic load_next_c = '0; + automatic logic [3:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_key_manifest_pk_hash_mask.mask.value; + load_next_c = '0; if(decoded_reg_strb.fuse_key_manifest_pk_hash_mask && decoded_req_is_wr && !(hwif_in.fuse_key_manifest_pk_hash_mask.mask.swwel)) begin // SW write next_c = (field_storage.fuse_key_manifest_pk_hash_mask.mask.value & ~decoded_wr_biten[3:0]) | (decoded_wr_data[3:0] & decoded_wr_biten[3:0]); load_next_c = '1; @@ -3027,7 +3135,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_key_manifest_pk_hash_mask.mask.value <= 'h0; + field_storage.fuse_key_manifest_pk_hash_mask.mask.value <= 4'h0; end else if(field_combo.fuse_key_manifest_pk_hash_mask.mask.load_next) begin field_storage.fuse_key_manifest_pk_hash_mask.mask.value <= field_combo.fuse_key_manifest_pk_hash_mask.mask.next; end @@ -3036,8 +3144,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<12; i0++) begin // Field: soc_ifc_reg.fuse_owner_pk_hash[].hash always_comb begin - automatic logic [31:0] next_c = field_storage.fuse_owner_pk_hash[i0].hash.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_owner_pk_hash[i0].hash.value; + load_next_c = '0; if(decoded_reg_strb.fuse_owner_pk_hash[i0] && decoded_req_is_wr && !(hwif_in.fuse_owner_pk_hash[i0].hash.swwel)) begin // SW write next_c = (field_storage.fuse_owner_pk_hash[i0].hash.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3047,7 +3157,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_owner_pk_hash[i0].hash.value <= 'h0; + field_storage.fuse_owner_pk_hash[i0].hash.value <= 32'h0; end else if(field_combo.fuse_owner_pk_hash[i0].hash.load_next) begin field_storage.fuse_owner_pk_hash[i0].hash.value <= field_combo.fuse_owner_pk_hash[i0].hash.next; end @@ -3056,8 +3166,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.fuse_fmc_key_manifest_svn.svn always_comb begin - automatic logic [31:0] next_c = field_storage.fuse_fmc_key_manifest_svn.svn.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_fmc_key_manifest_svn.svn.value; + load_next_c = '0; if(decoded_reg_strb.fuse_fmc_key_manifest_svn && decoded_req_is_wr && !(hwif_in.fuse_fmc_key_manifest_svn.svn.swwel)) begin // SW write next_c = (field_storage.fuse_fmc_key_manifest_svn.svn.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3067,7 +3179,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_fmc_key_manifest_svn.svn.value <= 'h0; + field_storage.fuse_fmc_key_manifest_svn.svn.value <= 32'h0; end else if(field_combo.fuse_fmc_key_manifest_svn.svn.load_next) begin field_storage.fuse_fmc_key_manifest_svn.svn.value <= field_combo.fuse_fmc_key_manifest_svn.svn.next; end @@ -3076,8 +3188,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<4; i0++) begin // Field: soc_ifc_reg.fuse_runtime_svn[].svn always_comb begin - automatic logic [31:0] next_c = field_storage.fuse_runtime_svn[i0].svn.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_runtime_svn[i0].svn.value; + load_next_c = '0; if(decoded_reg_strb.fuse_runtime_svn[i0] && decoded_req_is_wr && !(hwif_in.fuse_runtime_svn[i0].svn.swwel)) begin // SW write next_c = (field_storage.fuse_runtime_svn[i0].svn.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3087,7 +3201,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_runtime_svn[i0].svn.value <= 'h0; + field_storage.fuse_runtime_svn[i0].svn.value <= 32'h0; end else if(field_combo.fuse_runtime_svn[i0].svn.load_next) begin field_storage.fuse_runtime_svn[i0].svn.value <= field_combo.fuse_runtime_svn[i0].svn.next; end @@ -3096,8 +3210,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.fuse_anti_rollback_disable.dis always_comb begin - automatic logic [0:0] next_c = field_storage.fuse_anti_rollback_disable.dis.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_anti_rollback_disable.dis.value; + load_next_c = '0; if(decoded_reg_strb.fuse_anti_rollback_disable && decoded_req_is_wr && !(hwif_in.fuse_anti_rollback_disable.dis.swwel)) begin // SW write next_c = (field_storage.fuse_anti_rollback_disable.dis.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -3107,7 +3223,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_anti_rollback_disable.dis.value <= 'h0; + field_storage.fuse_anti_rollback_disable.dis.value <= 1'h0; end else if(field_combo.fuse_anti_rollback_disable.dis.load_next) begin field_storage.fuse_anti_rollback_disable.dis.value <= field_combo.fuse_anti_rollback_disable.dis.next; end @@ -3116,8 +3232,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<24; i0++) begin // Field: soc_ifc_reg.fuse_idevid_cert_attr[].cert always_comb begin - automatic logic [31:0] next_c = field_storage.fuse_idevid_cert_attr[i0].cert.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_idevid_cert_attr[i0].cert.value; + load_next_c = '0; if(decoded_reg_strb.fuse_idevid_cert_attr[i0] && decoded_req_is_wr && !(hwif_in.fuse_idevid_cert_attr[i0].cert.swwel)) begin // SW write next_c = (field_storage.fuse_idevid_cert_attr[i0].cert.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3127,7 +3245,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_idevid_cert_attr[i0].cert.value <= 'h0; + field_storage.fuse_idevid_cert_attr[i0].cert.value <= 32'h0; end else if(field_combo.fuse_idevid_cert_attr[i0].cert.load_next) begin field_storage.fuse_idevid_cert_attr[i0].cert.value <= field_combo.fuse_idevid_cert_attr[i0].cert.next; end @@ -3137,8 +3255,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<4; i0++) begin // Field: soc_ifc_reg.fuse_idevid_manuf_hsm_id[].hsm_id always_comb begin - automatic logic [31:0] next_c = field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value; + load_next_c = '0; if(decoded_reg_strb.fuse_idevid_manuf_hsm_id[i0] && decoded_req_is_wr && !(hwif_in.fuse_idevid_manuf_hsm_id[i0].hsm_id.swwel)) begin // SW write next_c = (field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3148,7 +3268,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value <= 'h0; + field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value <= 32'h0; end else if(field_combo.fuse_idevid_manuf_hsm_id[i0].hsm_id.load_next) begin field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value <= field_combo.fuse_idevid_manuf_hsm_id[i0].hsm_id.next; end @@ -3157,8 +3277,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.fuse_life_cycle.life_cycle always_comb begin - automatic logic [1:0] next_c = field_storage.fuse_life_cycle.life_cycle.value; - automatic logic load_next_c = '0; + automatic logic [1:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_life_cycle.life_cycle.value; + load_next_c = '0; if(decoded_reg_strb.fuse_life_cycle && decoded_req_is_wr && !(hwif_in.fuse_life_cycle.life_cycle.swwel)) begin // SW write next_c = (field_storage.fuse_life_cycle.life_cycle.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]); load_next_c = '1; @@ -3168,7 +3290,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_life_cycle.life_cycle.value <= 'h0; + field_storage.fuse_life_cycle.life_cycle.value <= 2'h0; end else if(field_combo.fuse_life_cycle.life_cycle.load_next) begin field_storage.fuse_life_cycle.life_cycle.value <= field_combo.fuse_life_cycle.life_cycle.next; end @@ -3176,8 +3298,10 @@ module soc_ifc_reg ( assign hwif_out.fuse_life_cycle.life_cycle.value = field_storage.fuse_life_cycle.life_cycle.value; // Field: soc_ifc_reg.fuse_lms_verify.lms_verify always_comb begin - automatic logic [0:0] next_c = field_storage.fuse_lms_verify.lms_verify.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_lms_verify.lms_verify.value; + load_next_c = '0; if(decoded_reg_strb.fuse_lms_verify && decoded_req_is_wr && !(hwif_in.fuse_lms_verify.lms_verify.swwel)) begin // SW write next_c = (field_storage.fuse_lms_verify.lms_verify.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -3187,7 +3311,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_lms_verify.lms_verify.value <= 'h0; + field_storage.fuse_lms_verify.lms_verify.value <= 1'h0; end else if(field_combo.fuse_lms_verify.lms_verify.load_next) begin field_storage.fuse_lms_verify.lms_verify.value <= field_combo.fuse_lms_verify.lms_verify.next; end @@ -3195,8 +3319,10 @@ module soc_ifc_reg ( assign hwif_out.fuse_lms_verify.lms_verify.value = field_storage.fuse_lms_verify.lms_verify.value; // Field: soc_ifc_reg.fuse_lms_revocation.lms_revocation always_comb begin - automatic logic [31:0] next_c = field_storage.fuse_lms_revocation.lms_revocation.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_lms_revocation.lms_revocation.value; + load_next_c = '0; if(decoded_reg_strb.fuse_lms_revocation && decoded_req_is_wr && !(hwif_in.fuse_lms_revocation.lms_revocation.swwel)) begin // SW write next_c = (field_storage.fuse_lms_revocation.lms_revocation.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3206,7 +3332,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_lms_revocation.lms_revocation.value <= 'h0; + field_storage.fuse_lms_revocation.lms_revocation.value <= 32'h0; end else if(field_combo.fuse_lms_revocation.lms_revocation.load_next) begin field_storage.fuse_lms_revocation.lms_revocation.value <= field_combo.fuse_lms_revocation.lms_revocation.next; end @@ -3214,8 +3340,10 @@ module soc_ifc_reg ( assign hwif_out.fuse_lms_revocation.lms_revocation.value = field_storage.fuse_lms_revocation.lms_revocation.value; // Field: soc_ifc_reg.fuse_soc_stepping_id.soc_stepping_id always_comb begin - automatic logic [15:0] next_c = field_storage.fuse_soc_stepping_id.soc_stepping_id.value; - automatic logic load_next_c = '0; + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.fuse_soc_stepping_id.soc_stepping_id.value; + load_next_c = '0; if(decoded_reg_strb.fuse_soc_stepping_id && decoded_req_is_wr && !(hwif_in.fuse_soc_stepping_id.soc_stepping_id.swwel)) begin // SW write next_c = (field_storage.fuse_soc_stepping_id.soc_stepping_id.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]); load_next_c = '1; @@ -3225,7 +3353,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.fuse_soc_stepping_id.soc_stepping_id.value <= 'h0; + field_storage.fuse_soc_stepping_id.soc_stepping_id.value <= 16'h0; end else if(field_combo.fuse_soc_stepping_id.soc_stepping_id.load_next) begin field_storage.fuse_soc_stepping_id.soc_stepping_id.value <= field_combo.fuse_soc_stepping_id.soc_stepping_id.next; end @@ -3234,8 +3362,10 @@ module soc_ifc_reg ( for(genvar i0=0; i0<8; i0++) begin // Field: soc_ifc_reg.internal_obf_key[].key always_comb begin - automatic logic [31:0] next_c = field_storage.internal_obf_key[i0].key.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_obf_key[i0].key.value; + load_next_c = '0; if(decoded_reg_strb.internal_obf_key[i0] && decoded_req_is_wr && hwif_in.internal_obf_key[i0].key.swwe) begin // SW write next_c = (field_storage.internal_obf_key[i0].key.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3249,6 +3379,7 @@ module soc_ifc_reg ( field_combo.internal_obf_key[i0].key.next = next_c; field_combo.internal_obf_key[i0].key.load_next = load_next_c; end + always_ff @(posedge clk) begin if(field_combo.internal_obf_key[i0].key.load_next) begin field_storage.internal_obf_key[i0].key.value <= field_combo.internal_obf_key[i0].key.next; @@ -3258,8 +3389,10 @@ module soc_ifc_reg ( end // Field: soc_ifc_reg.internal_iccm_lock.lock always_comb begin - automatic logic [0:0] next_c = field_storage.internal_iccm_lock.lock.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_iccm_lock.lock.value; + load_next_c = '0; if(hwif_in.internal_iccm_lock.lock.hwclr) begin // HW Clear next_c = '0; load_next_c = '1; @@ -3272,7 +3405,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_iccm_lock.lock.value <= 'h0; + field_storage.internal_iccm_lock.lock.value <= 1'h0; end else if(field_combo.internal_iccm_lock.lock.load_next) begin field_storage.internal_iccm_lock.lock.value <= field_combo.internal_iccm_lock.lock.next; end @@ -3280,12 +3413,14 @@ module soc_ifc_reg ( assign hwif_out.internal_iccm_lock.lock.value = field_storage.internal_iccm_lock.lock.value; // Field: soc_ifc_reg.internal_fw_update_reset.core_rst always_comb begin - automatic logic [0:0] next_c = field_storage.internal_fw_update_reset.core_rst.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_fw_update_reset.core_rst.value; + load_next_c = '0; if(decoded_reg_strb.internal_fw_update_reset && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_fw_update_reset.core_rst.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -3294,7 +3429,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_fw_update_reset.core_rst.value <= 'h0; + field_storage.internal_fw_update_reset.core_rst.value <= 1'h0; end else if(field_combo.internal_fw_update_reset.core_rst.load_next) begin field_storage.internal_fw_update_reset.core_rst.value <= field_combo.internal_fw_update_reset.core_rst.next; end @@ -3302,8 +3437,10 @@ module soc_ifc_reg ( assign hwif_out.internal_fw_update_reset.core_rst.value = field_storage.internal_fw_update_reset.core_rst.value; // Field: soc_ifc_reg.internal_fw_update_reset_wait_cycles.wait_cycles always_comb begin - automatic logic [7:0] next_c = field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value; - automatic logic load_next_c = '0; + automatic logic [7:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value; + load_next_c = '0; if(decoded_reg_strb.internal_fw_update_reset_wait_cycles && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value & ~decoded_wr_biten[7:0]) | (decoded_wr_data[7:0] & decoded_wr_biten[7:0]); load_next_c = '1; @@ -3313,7 +3450,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value <= 'h5; + field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value <= 8'h5; end else if(field_combo.internal_fw_update_reset_wait_cycles.wait_cycles.load_next) begin field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value <= field_combo.internal_fw_update_reset_wait_cycles.wait_cycles.next; end @@ -3321,8 +3458,10 @@ module soc_ifc_reg ( assign hwif_out.internal_fw_update_reset_wait_cycles.wait_cycles.value = field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value; // Field: soc_ifc_reg.internal_nmi_vector.vec always_comb begin - automatic logic [31:0] next_c = field_storage.internal_nmi_vector.vec.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_nmi_vector.vec.value; + load_next_c = '0; if(decoded_reg_strb.internal_nmi_vector && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_nmi_vector.vec.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3332,7 +3471,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_nmi_vector.vec.value <= 'h0; + field_storage.internal_nmi_vector.vec.value <= 32'h0; end else if(field_combo.internal_nmi_vector.vec.load_next) begin field_storage.internal_nmi_vector.vec.value <= field_combo.internal_nmi_vector.vec.next; end @@ -3340,8 +3479,10 @@ module soc_ifc_reg ( assign hwif_out.internal_nmi_vector.vec.value = field_storage.internal_nmi_vector.vec.value; // Field: soc_ifc_reg.internal_hw_error_fatal_mask.mask_iccm_ecc_unc always_comb begin - automatic logic [0:0] next_c = field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value; + load_next_c = '0; if(decoded_reg_strb.internal_hw_error_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -3351,7 +3492,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value <= 'h0; + field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value <= 1'h0; end else if(field_combo.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.load_next) begin field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value <= field_combo.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.next; end @@ -3359,8 +3500,10 @@ module soc_ifc_reg ( assign hwif_out.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value = field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value; // Field: soc_ifc_reg.internal_hw_error_fatal_mask.mask_dccm_ecc_unc always_comb begin - automatic logic [0:0] next_c = field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value; + load_next_c = '0; if(decoded_reg_strb.internal_hw_error_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -3370,7 +3513,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value <= 'h0; + field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value <= 1'h0; end else if(field_combo.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.load_next) begin field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value <= field_combo.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.next; end @@ -3378,8 +3521,10 @@ module soc_ifc_reg ( assign hwif_out.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value = field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value; // Field: soc_ifc_reg.internal_hw_error_fatal_mask.mask_nmi_pin always_comb begin - automatic logic [0:0] next_c = field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value; + load_next_c = '0; if(decoded_reg_strb.internal_hw_error_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -3389,7 +3534,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value <= 'h0; + field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value <= 1'h0; end else if(field_combo.internal_hw_error_fatal_mask.mask_nmi_pin.load_next) begin field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value <= field_combo.internal_hw_error_fatal_mask.mask_nmi_pin.next; end @@ -3397,8 +3542,10 @@ module soc_ifc_reg ( assign hwif_out.internal_hw_error_fatal_mask.mask_nmi_pin.value = field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value; // Field: soc_ifc_reg.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock always_comb begin - automatic logic [0:0] next_c = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value; + load_next_c = '0; if(decoded_reg_strb.internal_hw_error_non_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -3408,7 +3555,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value <= 'h0; + field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value <= 1'h0; end else if(field_combo.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.load_next) begin field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value <= field_combo.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.next; end @@ -3416,8 +3563,10 @@ module soc_ifc_reg ( assign hwif_out.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value; // Field: soc_ifc_reg.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo always_comb begin - automatic logic [0:0] next_c = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value; + load_next_c = '0; if(decoded_reg_strb.internal_hw_error_non_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -3427,7 +3576,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value <= 'h0; + field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value <= 1'h0; end else if(field_combo.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.load_next) begin field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value <= field_combo.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.next; end @@ -3435,8 +3584,10 @@ module soc_ifc_reg ( assign hwif_out.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value; // Field: soc_ifc_reg.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc always_comb begin - automatic logic [0:0] next_c = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value; + load_next_c = '0; if(decoded_reg_strb.internal_hw_error_non_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -3446,7 +3597,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value <= 'h0; + field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value <= 1'h0; end else if(field_combo.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.load_next) begin field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value <= field_combo.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.next; end @@ -3454,8 +3605,10 @@ module soc_ifc_reg ( assign hwif_out.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value = field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value; // Field: soc_ifc_reg.internal_fw_error_fatal_mask.mask always_comb begin - automatic logic [31:0] next_c = field_storage.internal_fw_error_fatal_mask.mask.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_fw_error_fatal_mask.mask.value; + load_next_c = '0; if(decoded_reg_strb.internal_fw_error_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_fw_error_fatal_mask.mask.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3465,7 +3618,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_fw_error_fatal_mask.mask.value <= 'h0; + field_storage.internal_fw_error_fatal_mask.mask.value <= 32'h0; end else if(field_combo.internal_fw_error_fatal_mask.mask.load_next) begin field_storage.internal_fw_error_fatal_mask.mask.value <= field_combo.internal_fw_error_fatal_mask.mask.next; end @@ -3473,8 +3626,10 @@ module soc_ifc_reg ( assign hwif_out.internal_fw_error_fatal_mask.mask.value = field_storage.internal_fw_error_fatal_mask.mask.value; // Field: soc_ifc_reg.internal_fw_error_non_fatal_mask.mask always_comb begin - automatic logic [31:0] next_c = field_storage.internal_fw_error_non_fatal_mask.mask.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_fw_error_non_fatal_mask.mask.value; + load_next_c = '0; if(decoded_reg_strb.internal_fw_error_non_fatal_mask && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_fw_error_non_fatal_mask.mask.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3484,7 +3639,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.internal_fw_error_non_fatal_mask.mask.value <= 'h0; + field_storage.internal_fw_error_non_fatal_mask.mask.value <= 32'h0; end else if(field_combo.internal_fw_error_non_fatal_mask.mask.load_next) begin field_storage.internal_fw_error_non_fatal_mask.mask.value <= field_combo.internal_fw_error_non_fatal_mask.mask.next; end @@ -3492,26 +3647,28 @@ module soc_ifc_reg ( assign hwif_out.internal_fw_error_non_fatal_mask.mask.value = field_storage.internal_fw_error_non_fatal_mask.mask.value; // Field: soc_ifc_reg.internal_rv_mtime_l.count_l always_comb begin - automatic logic [31:0] next_c = field_storage.internal_rv_mtime_l.count_l.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_rv_mtime_l.count_l.value; + load_next_c = '0; if(decoded_reg_strb.internal_rv_mtime_l && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_rv_mtime_l.count_l.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(hwif_in.internal_rv_mtime_l.count_l.incr) begin // increment - field_combo.internal_rv_mtime_l.count_l.overflow = (((33)'(next_c) + 'h1) > 'hffffffff); - next_c = next_c + 'h1; + field_combo.internal_rv_mtime_l.count_l.overflow = (((33)'(next_c) + 32'h1) > 32'hffffffff); + next_c = next_c + 32'h1; load_next_c = '1; end else begin field_combo.internal_rv_mtime_l.count_l.overflow = '0; end - field_combo.internal_rv_mtime_l.count_l.incrthreshold = (field_storage.internal_rv_mtime_l.count_l.value >= 'hffffffff); + field_combo.internal_rv_mtime_l.count_l.incrthreshold = (field_storage.internal_rv_mtime_l.count_l.value >= 32'hffffffff); field_combo.internal_rv_mtime_l.count_l.next = next_c; field_combo.internal_rv_mtime_l.count_l.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.internal_rv_mtime_l.count_l.value <= 'h0; + field_storage.internal_rv_mtime_l.count_l.value <= 32'h0; end else if(field_combo.internal_rv_mtime_l.count_l.load_next) begin field_storage.internal_rv_mtime_l.count_l.value <= field_combo.internal_rv_mtime_l.count_l.next; end @@ -3521,26 +3678,28 @@ module soc_ifc_reg ( assign hwif_out.internal_rv_mtime_l.count_l.overflow = field_combo.internal_rv_mtime_l.count_l.overflow; // Field: soc_ifc_reg.internal_rv_mtime_h.count_h always_comb begin - automatic logic [31:0] next_c = field_storage.internal_rv_mtime_h.count_h.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_rv_mtime_h.count_h.value; + load_next_c = '0; if(decoded_reg_strb.internal_rv_mtime_h && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_rv_mtime_h.count_h.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(hwif_in.internal_rv_mtime_h.count_h.incr) begin // increment - field_combo.internal_rv_mtime_h.count_h.overflow = (((33)'(next_c) + 'h1) > 'hffffffff); - next_c = next_c + 'h1; + field_combo.internal_rv_mtime_h.count_h.overflow = (((33)'(next_c) + 32'h1) > 32'hffffffff); + next_c = next_c + 32'h1; load_next_c = '1; end else begin field_combo.internal_rv_mtime_h.count_h.overflow = '0; end - field_combo.internal_rv_mtime_h.count_h.incrthreshold = (field_storage.internal_rv_mtime_h.count_h.value >= 'hffffffff); + field_combo.internal_rv_mtime_h.count_h.incrthreshold = (field_storage.internal_rv_mtime_h.count_h.value >= 32'hffffffff); field_combo.internal_rv_mtime_h.count_h.next = next_c; field_combo.internal_rv_mtime_h.count_h.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.internal_rv_mtime_h.count_h.value <= 'h0; + field_storage.internal_rv_mtime_h.count_h.value <= 32'h0; end else if(field_combo.internal_rv_mtime_h.count_h.load_next) begin field_storage.internal_rv_mtime_h.count_h.value <= field_combo.internal_rv_mtime_h.count_h.next; end @@ -3549,8 +3708,10 @@ module soc_ifc_reg ( assign hwif_out.internal_rv_mtime_h.count_h.swmod = decoded_reg_strb.internal_rv_mtime_h && decoded_req_is_wr; // Field: soc_ifc_reg.internal_rv_mtimecmp_l.compare_l always_comb begin - automatic logic [31:0] next_c = field_storage.internal_rv_mtimecmp_l.compare_l.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_rv_mtimecmp_l.compare_l.value; + load_next_c = '0; if(decoded_reg_strb.internal_rv_mtimecmp_l && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_rv_mtimecmp_l.compare_l.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3560,7 +3721,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.internal_rv_mtimecmp_l.compare_l.value <= 'h0; + field_storage.internal_rv_mtimecmp_l.compare_l.value <= 32'h0; end else if(field_combo.internal_rv_mtimecmp_l.compare_l.load_next) begin field_storage.internal_rv_mtimecmp_l.compare_l.value <= field_combo.internal_rv_mtimecmp_l.compare_l.next; end @@ -3568,8 +3729,10 @@ module soc_ifc_reg ( assign hwif_out.internal_rv_mtimecmp_l.compare_l.value = field_storage.internal_rv_mtimecmp_l.compare_l.value; // Field: soc_ifc_reg.internal_rv_mtimecmp_h.compare_h always_comb begin - automatic logic [31:0] next_c = field_storage.internal_rv_mtimecmp_h.compare_h.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.internal_rv_mtimecmp_h.compare_h.value; + load_next_c = '0; if(decoded_reg_strb.internal_rv_mtimecmp_h && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.internal_rv_mtimecmp_h.compare_h.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; @@ -3579,7 +3742,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.internal_rv_mtimecmp_h.compare_h.value <= 'h0; + field_storage.internal_rv_mtimecmp_h.compare_h.value <= 32'h0; end else if(field_combo.internal_rv_mtimecmp_h.compare_h.load_next) begin field_storage.internal_rv_mtimecmp_h.compare_h.value <= field_combo.internal_rv_mtimecmp_h.compare_h.next; end @@ -3587,8 +3750,10 @@ module soc_ifc_reg ( assign hwif_out.internal_rv_mtimecmp_h.compare_h.value = field_storage.internal_rv_mtimecmp_h.compare_h.value; // Field: soc_ifc_reg.intr_block_rf.global_intr_en_r.error_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.error_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -3598,15 +3763,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.error_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.error_en.value <= field_combo.intr_block_rf.global_intr_en_r.error_en.next; end end // Field: soc_ifc_reg.intr_block_rf.global_intr_en_r.notif_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.global_intr_en_r.notif_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -3616,15 +3783,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 'h0; + field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 1'h0; end else if(field_combo.intr_block_rf.global_intr_en_r.notif_en.load_next) begin field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= field_combo.intr_block_rf.global_intr_en_r.notif_en.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_en_r.error_internal_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -3634,15 +3803,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error_internal_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_internal_en.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_en_r.error_inv_dev_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -3652,15 +3823,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error_inv_dev_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_inv_dev_en.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_en_r.error_cmd_fail_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -3670,15 +3843,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error_cmd_fail_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_cmd_fail_en.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_en_r.error_bad_fuse_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -3688,15 +3863,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error_bad_fuse_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_bad_fuse_en.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_en_r.error_iccm_blocked_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value & ~decoded_wr_biten[4:4]) | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]); load_next_c = '1; @@ -3706,15 +3883,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value & ~decoded_wr_biten[5:5]) | (decoded_wr_data[5:5] & decoded_wr_biten[5:5]); load_next_c = '1; @@ -3724,15 +3903,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; @@ -3742,15 +3923,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value & ~decoded_wr_biten[7:7]) | (decoded_wr_data[7:7] & decoded_wr_biten[7:7]); load_next_c = '1; @@ -3760,15 +3943,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value <= 'h0; + field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.load_next) begin field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; @@ -3778,15 +3963,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; @@ -3796,15 +3983,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_en_r.notif_debug_locked_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; @@ -3814,15 +4003,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_en_r.notif_scan_mode_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; @@ -3832,15 +4023,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value & ~decoded_wr_biten[4:4]) | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]); load_next_c = '1; @@ -3850,15 +4043,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value & ~decoded_wr_biten[5:5]) | (decoded_wr_data[5:5] & decoded_wr_biten[5:5]); load_next_c = '1; @@ -3868,25 +4063,27 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value <= 'h0; + field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.load_next) begin field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.next; end end // Field: soc_ifc_reg.intr_block_rf.error_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.error_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.error_global_intr_r.agg_sts.next; end @@ -3895,18 +4092,20 @@ module soc_ifc_reg ( |(field_storage.intr_block_rf.error_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.error_en.value); // Field: soc_ifc_reg.intr_block_rf.notif_global_intr_r.agg_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; - automatic logic load_next_c = '0; - if(1) begin // HW Write - next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; - load_next_c = '1; - end + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; + load_next_c = '1; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next = next_c; field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 'h0; + field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next) begin field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next; end @@ -3915,9 +4114,11 @@ module soc_ifc_reg ( |(field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.notif_en.value); // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_r.error_internal_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_internal_sts.hwset) begin // HW Set @@ -3932,16 +4133,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error_internal_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_internal_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_r.error_inv_dev_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.hwset) begin // HW Set @@ -3956,16 +4159,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.hwset) begin // HW Set @@ -3980,16 +4185,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.hwset) begin // HW Set @@ -4004,16 +4211,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.hwset) begin // HW Set @@ -4028,16 +4237,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.hwset) begin // HW Set @@ -4052,16 +4263,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.hwset) begin // HW Set @@ -4076,16 +4289,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.hwset) begin // HW Set @@ -4100,7 +4315,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.load_next) begin field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.next; end @@ -4116,9 +4331,11 @@ module soc_ifc_reg ( || |(field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value & field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value); // Field: soc_ifc_reg.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.hwset) begin // HW Set @@ -4133,16 +4350,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.hwset) begin // HW Set @@ -4157,16 +4376,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.hwset) begin // HW Set @@ -4181,16 +4402,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.hwset) begin // HW Set @@ -4205,16 +4428,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.hwset) begin // HW Set @@ -4229,16 +4454,18 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value; - automatic logic load_next_c = '0; - if(field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value) begin // stickybit + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value != '0) begin // stickybit next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value; load_next_c = '1; end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.hwset) begin // HW Set @@ -4253,7 +4480,7 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value <= 'h0; + field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.load_next) begin field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.next; end @@ -4267,12 +4494,14 @@ module soc_ifc_reg ( || |(field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value); // Field: soc_ifc_reg.intr_block_rf.error_intr_trig_r.error_internal_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4281,19 +4510,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error_internal_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_internal_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_trig_r.error_inv_dev_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4302,19 +4533,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4323,19 +4556,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4344,19 +4579,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4365,19 +4602,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value | (decoded_wr_data[5:5] & decoded_wr_biten[5:5]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4386,19 +4625,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4407,19 +4648,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value | (decoded_wr_data[7:7] & decoded_wr_biten[7:7]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4428,19 +4671,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value <= 'h0; + field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.load_next) begin field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4449,19 +4694,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4470,19 +4717,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4491,19 +4740,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4512,19 +4763,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4533,19 +4786,21 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write 1 set next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value | (decoded_wr_data[5:5] & decoded_wr_biten[5:5]); load_next_c = '1; - end else if(1) begin // singlepulse clears back to 0 + end else begin // singlepulse clears back to 0 next_c = '0; load_next_c = '1; end @@ -4554,31 +4809,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value <= 'h0; + field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.load_next) begin field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.next; end end // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_internal_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error_internal_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error_internal_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error_internal_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_internal_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error_internal_intr_count_r.cnt.next = next_c; @@ -4586,31 +4843,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error_internal_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_internal_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.error_inv_dev_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error_inv_dev_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error_inv_dev_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error_inv_dev_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_inv_dev_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error_inv_dev_intr_count_r.cnt.next = next_c; @@ -4618,31 +4877,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error_inv_dev_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_inv_dev_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.error_cmd_fail_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error_cmd_fail_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error_cmd_fail_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error_cmd_fail_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_cmd_fail_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error_cmd_fail_intr_count_r.cnt.next = next_c; @@ -4650,31 +4911,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error_cmd_fail_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_cmd_fail_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.error_bad_fuse_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error_bad_fuse_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error_bad_fuse_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error_bad_fuse_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_bad_fuse_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error_bad_fuse_intr_count_r.cnt.next = next_c; @@ -4682,31 +4945,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error_bad_fuse_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_bad_fuse_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.error_iccm_blocked_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.next = next_c; @@ -4714,31 +4979,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.next = next_c; @@ -4746,31 +5013,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.next = next_c; @@ -4778,31 +5047,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.next = next_c; @@ -4810,31 +5081,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin if(~hwif_in.cptra_pwrgood) begin - field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_cmd_avail_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.next = next_c; @@ -4842,31 +5115,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.next = next_c; @@ -4874,31 +5149,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_debug_locked_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_debug_locked_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_debug_locked_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_debug_locked_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_debug_locked_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_debug_locked_intr_count_r.cnt.next = next_c; @@ -4906,31 +5183,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_debug_locked_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_debug_locked_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_scan_mode_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.next = next_c; @@ -4938,31 +5217,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_scan_mode_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.next = next_c; @@ -4970,31 +5251,33 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt always_comb begin - automatic logic [31:0] next_c = field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value; - automatic logic load_next_c = '0; + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value; + load_next_c = '0; if(decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_r && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write next_c = (field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); load_next_c = '1; end if(field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value) begin // increment - if(((33)'(next_c) + 'h1) > 'hffffffff) begin // up-counter saturated - next_c = 'hffffffff; + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; end else begin - next_c = next_c + 'h1; + next_c = next_c + 32'h1; end load_next_c = '1; end - field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value >= 'hffffffff); - field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value >= 'hffffffff); - if(next_c > 'hffffffff) begin - next_c = 'hffffffff; + field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; load_next_c = '1; end field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.next = next_c; @@ -5002,15 +5285,17 @@ module soc_ifc_reg ( end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value <= 'h0; + field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value <= 32'h0; end else if(field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.load_next) begin field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.next; end end // Field: soc_ifc_reg.intr_block_rf.error_internal_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; load_next_c = '1; @@ -5019,27 +5304,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value; load_next_c = '1; @@ -5048,27 +5335,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value; load_next_c = '1; @@ -5077,27 +5366,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value; load_next_c = '1; @@ -5106,27 +5397,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value; load_next_c = '1; @@ -5135,27 +5428,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value; load_next_c = '1; @@ -5164,27 +5459,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value; load_next_c = '1; @@ -5193,27 +5490,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value; load_next_c = '1; @@ -5222,27 +5521,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value; load_next_c = '1; @@ -5251,27 +5552,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value; load_next_c = '1; @@ -5280,27 +5583,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value; load_next_c = '1; @@ -5309,27 +5614,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value; load_next_c = '1; @@ -5338,27 +5645,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value; load_next_c = '1; @@ -5367,27 +5676,29 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.next; end end // Field: soc_ifc_reg.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse always_comb begin - automatic logic [0:0] next_c = field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value; - automatic logic load_next_c = '0; + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value; + load_next_c = '0; if(field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value) begin // HW Write - we next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value; load_next_c = '1; @@ -5396,30 +5707,39 @@ module soc_ifc_reg ( load_next_c = '1; end if(field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value) begin // decrement - field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.underflow = (next_c < ('h1)); - next_c = next_c - 'h1; + field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; load_next_c = '1; end else begin field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.underflow = '0; end - field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value <= 'd0); + field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value <= 1'd0); field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.next = next_c; field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.load_next = load_next_c; end always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin if(~hwif_in.cptra_rst_b) begin - field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value <= 'h0; + field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value <= 1'h0; end else if(field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.load_next) begin field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.next; end end + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_err; logic readback_done; logic [31:0] readback_data; - + // Assign readback values to a flattened array logic [186-1:0][31:0] readback_array; assign readback_array[0][0:0] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value : '0; @@ -5451,7 +5771,7 @@ module soc_ifc_reg ( assign readback_array[17][1:0] = (decoded_reg_strb.CPTRA_SECURITY_STATE && !decoded_req_is_wr) ? hwif_in.CPTRA_SECURITY_STATE.device_lifecycle.next : '0; assign readback_array[17][2:2] = (decoded_reg_strb.CPTRA_SECURITY_STATE && !decoded_req_is_wr) ? hwif_in.CPTRA_SECURITY_STATE.debug_locked.next : '0; assign readback_array[17][3:3] = (decoded_reg_strb.CPTRA_SECURITY_STATE && !decoded_req_is_wr) ? hwif_in.CPTRA_SECURITY_STATE.scan_mode.next : '0; - assign readback_array[17][31:4] = (decoded_reg_strb.CPTRA_SECURITY_STATE && !decoded_req_is_wr) ? 'h0 : '0; + assign readback_array[17][31:4] = (decoded_reg_strb.CPTRA_SECURITY_STATE && !decoded_req_is_wr) ? 28'h0 : '0; for(genvar i0=0; i0<5; i0++) begin assign readback_array[i0*1 + 18][31:0] = (decoded_reg_strb.CPTRA_MBOX_VALID_PAUSER[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_MBOX_VALID_PAUSER[i0].PAUSER.value : '0; end @@ -5484,7 +5804,7 @@ module soc_ifc_reg ( for(genvar i0=0; i0<2; i0++) begin assign readback_array[i0*1 + 51][31:0] = (decoded_reg_strb.CPTRA_GENERIC_OUTPUT_WIRES[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_GENERIC_OUTPUT_WIRES[i0].generic_wires.value : '0; end - assign readback_array[53][15:0] = (decoded_reg_strb.CPTRA_HW_REV_ID && !decoded_req_is_wr) ? 'h1 : '0; + assign readback_array[53][15:0] = (decoded_reg_strb.CPTRA_HW_REV_ID && !decoded_req_is_wr) ? 16'h1 : '0; assign readback_array[53][31:16] = (decoded_reg_strb.CPTRA_HW_REV_ID && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_REV_ID.SOC_STEPPING_ID.next : '0; for(genvar i0=0; i0<2; i0++) begin assign readback_array[i0*1 + 54][31:0] = (decoded_reg_strb.CPTRA_FW_REV_ID[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_FW_REV_ID[i0].REV_ID.value : '0; @@ -5683,4 +6003,4 @@ module soc_ifc_reg ( assign cpuif_rd_ack = readback_done; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; -endmodule \ No newline at end of file +endmodule diff --git a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv index 960293743..92e1f8e7a 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv +++ b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv @@ -2,6 +2,10 @@ // https://github.com/SystemRDL/PeakRDL-regblock package soc_ifc_reg_pkg; + + localparam SOC_IFC_REG_DATA_WIDTH = 32; + localparam SOC_IFC_REG_MIN_ADDR_WIDTH = 12; + typedef struct packed{ logic next; logic we; @@ -339,78 +343,78 @@ package soc_ifc_reg_pkg; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__error_intr_t__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_f7aac87a__in_t; + } soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__error_intr_t__error_inv_dev_sts_enable_e83f2724_next_8318aff8_resetsignal_f7aac87a__in_t; + } soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_inv_dev_sts_enable_e83f2724_next_8318aff8_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__error_intr_t__error_cmd_fail_sts_enable_d535c05b_next_eee7e362_resetsignal_f7aac87a__in_t; + } soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_cmd_fail_sts_enable_d535c05b_next_eee7e362_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__error_intr_t__error_bad_fuse_sts_enable_fceb289f_next_14761353_resetsignal_f7aac87a__in_t; + } soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_bad_fuse_sts_enable_fceb289f_next_14761353_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__error_intr_t__error_iccm_blocked_sts_enable_4ccfea15_next_86c0a4d2_resetsignal_f7aac87a__in_t; + } soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_iccm_blocked_sts_enable_4ccfea15_next_86c0a4d2_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__error_intr_t__error_mbox_ecc_unc_sts_enable_18d80a94_next_91af8aa5_resetsignal_f7aac87a__in_t; + } soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_mbox_ecc_unc_sts_enable_18d80a94_next_91af8aa5_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__error_intr_t__error_wdt_timer1_timeout_sts_enable_fa7e6d0f_next_293a6067_resetsignal_f7aac87a__in_t; + } soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_wdt_timer1_timeout_sts_enable_fa7e6d0f_next_293a6067_resetsignal_f7aac87a__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__error_intr_t__error_wdt_timer2_timeout_sts_enable_38137b0c_next_1084f7bd_resetsignal_f7aac87a__in_t; + } soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_wdt_timer2_timeout_sts_enable_38137b0c_next_1084f7bd_resetsignal_f7aac87a__in_t; typedef struct packed{ - soc_ifc_reg__intr_block_t__error_intr_t__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_f7aac87a__in_t error_internal_sts; - soc_ifc_reg__intr_block_t__error_intr_t__error_inv_dev_sts_enable_e83f2724_next_8318aff8_resetsignal_f7aac87a__in_t error_inv_dev_sts; - soc_ifc_reg__intr_block_t__error_intr_t__error_cmd_fail_sts_enable_d535c05b_next_eee7e362_resetsignal_f7aac87a__in_t error_cmd_fail_sts; - soc_ifc_reg__intr_block_t__error_intr_t__error_bad_fuse_sts_enable_fceb289f_next_14761353_resetsignal_f7aac87a__in_t error_bad_fuse_sts; - soc_ifc_reg__intr_block_t__error_intr_t__error_iccm_blocked_sts_enable_4ccfea15_next_86c0a4d2_resetsignal_f7aac87a__in_t error_iccm_blocked_sts; - soc_ifc_reg__intr_block_t__error_intr_t__error_mbox_ecc_unc_sts_enable_18d80a94_next_91af8aa5_resetsignal_f7aac87a__in_t error_mbox_ecc_unc_sts; - soc_ifc_reg__intr_block_t__error_intr_t__error_wdt_timer1_timeout_sts_enable_fa7e6d0f_next_293a6067_resetsignal_f7aac87a__in_t error_wdt_timer1_timeout_sts; - soc_ifc_reg__intr_block_t__error_intr_t__error_wdt_timer2_timeout_sts_enable_38137b0c_next_1084f7bd_resetsignal_f7aac87a__in_t error_wdt_timer2_timeout_sts; + soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_f7aac87a__in_t error_internal_sts; + soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_inv_dev_sts_enable_e83f2724_next_8318aff8_resetsignal_f7aac87a__in_t error_inv_dev_sts; + soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_cmd_fail_sts_enable_d535c05b_next_eee7e362_resetsignal_f7aac87a__in_t error_cmd_fail_sts; + soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_bad_fuse_sts_enable_fceb289f_next_14761353_resetsignal_f7aac87a__in_t error_bad_fuse_sts; + soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_iccm_blocked_sts_enable_4ccfea15_next_86c0a4d2_resetsignal_f7aac87a__in_t error_iccm_blocked_sts; + soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_mbox_ecc_unc_sts_enable_18d80a94_next_91af8aa5_resetsignal_f7aac87a__in_t error_mbox_ecc_unc_sts; + soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_wdt_timer1_timeout_sts_enable_fa7e6d0f_next_293a6067_resetsignal_f7aac87a__in_t error_wdt_timer1_timeout_sts; + soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__error_wdt_timer2_timeout_sts_enable_38137b0c_next_1084f7bd_resetsignal_f7aac87a__in_t error_wdt_timer2_timeout_sts; } soc_ifc_reg__intr_block_t__error_intr_t_error_bad_fuse_sts_23f67582_error_cmd_fail_sts_b85845f8_error_iccm_blocked_sts_e81e6ad2_error_internal_sts_caad62e2_error_inv_dev_sts_6693e7db_error_mbox_ecc_unc_sts_30bff330_error_wdt_timer1_timeout_sts_6aaa9655_error_wdt_timer2_timeout_sts_cda8789f__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__notif_intr_t__notif_cmd_avail_sts_enable_f40f37a0_next_6afe0a88__in_t; + } soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_cmd_avail_sts_enable_f40f37a0_next_6afe0a88__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__notif_intr_t__notif_mbox_ecc_cor_sts_enable_c4f9db68_next_96c01bef__in_t; + } soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_mbox_ecc_cor_sts_enable_c4f9db68_next_96c01bef__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__notif_intr_t__notif_debug_locked_sts_enable_097fcd5b_next_36fa44d8__in_t; + } soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_debug_locked_sts_enable_097fcd5b_next_36fa44d8__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__notif_intr_t__notif_scan_mode_sts_enable_ed1d9036_next_eb34855d__in_t; + } soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_scan_mode_sts_enable_ed1d9036_next_eb34855d__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__notif_intr_t__notif_soc_req_lock_sts_enable_52b75726_next_228b63de__in_t; + } soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_soc_req_lock_sts_enable_52b75726_next_228b63de__in_t; typedef struct packed{ logic hwset; - } soc_ifc_reg__intr_block_t__notif_intr_t__notif_gen_in_toggle_sts_enable_9918ab15_next_e02c99b9__in_t; + } soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_gen_in_toggle_sts_enable_9918ab15_next_e02c99b9__in_t; typedef struct packed{ - soc_ifc_reg__intr_block_t__notif_intr_t__notif_cmd_avail_sts_enable_f40f37a0_next_6afe0a88__in_t notif_cmd_avail_sts; - soc_ifc_reg__intr_block_t__notif_intr_t__notif_mbox_ecc_cor_sts_enable_c4f9db68_next_96c01bef__in_t notif_mbox_ecc_cor_sts; - soc_ifc_reg__intr_block_t__notif_intr_t__notif_debug_locked_sts_enable_097fcd5b_next_36fa44d8__in_t notif_debug_locked_sts; - soc_ifc_reg__intr_block_t__notif_intr_t__notif_scan_mode_sts_enable_ed1d9036_next_eb34855d__in_t notif_scan_mode_sts; - soc_ifc_reg__intr_block_t__notif_intr_t__notif_soc_req_lock_sts_enable_52b75726_next_228b63de__in_t notif_soc_req_lock_sts; - soc_ifc_reg__intr_block_t__notif_intr_t__notif_gen_in_toggle_sts_enable_9918ab15_next_e02c99b9__in_t notif_gen_in_toggle_sts; + soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_cmd_avail_sts_enable_f40f37a0_next_6afe0a88__in_t notif_cmd_avail_sts; + soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_mbox_ecc_cor_sts_enable_c4f9db68_next_96c01bef__in_t notif_mbox_ecc_cor_sts; + soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_debug_locked_sts_enable_097fcd5b_next_36fa44d8__in_t notif_debug_locked_sts; + soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_scan_mode_sts_enable_ed1d9036_next_eb34855d__in_t notif_scan_mode_sts; + soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_soc_req_lock_sts_enable_52b75726_next_228b63de__in_t notif_soc_req_lock_sts; + soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__notif_gen_in_toggle_sts_enable_9918ab15_next_e02c99b9__in_t notif_gen_in_toggle_sts; } soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70__in_t; typedef struct packed{ @@ -1022,6 +1026,12 @@ package soc_ifc_reg_pkg; soc_ifc_reg__intr_block_t__out_t intr_block_rf; } soc_ifc_reg__out_t; + typedef enum { + soc_ifc_reg__CPTRA_SECURITY_STATE__device_lifecycle_e__DEVICE_UNPROVISIONED = 'h0, + soc_ifc_reg__CPTRA_SECURITY_STATE__device_lifecycle_e__DEVICE_MANUFACTURING = 'h1, + soc_ifc_reg__CPTRA_SECURITY_STATE__device_lifecycle_e__DEVICE_PRODUCTION = 'h3 + } soc_ifc_reg__CPTRA_SECURITY_STATE__device_lifecycle_e_e; + localparam SOC_IFC_REG_ADDR_WIDTH = 32'd12; endpackage \ No newline at end of file diff --git a/tools/scripts/reg_gen.py b/tools/scripts/reg_gen.py index eed084da1..2bb316453 100644 --- a/tools/scripts/reg_gen.py +++ b/tools/scripts/reg_gen.py @@ -39,6 +39,7 @@ from math import log, ceil, floor import sys import os +import re import rdl_post_process #output directory for dumping files @@ -57,7 +58,7 @@ def enter_Addrmap(self,node): pkg_file_path = str(self.regfile_name + "_pkg.sv") self.file = open(pkg_file_path, 'r') for line in self.file.readlines(): - if (line != "endpackage"): + if (re.search(r'\bendpackage\b', line) is None): self.orig_file += line self.file.close() self.file = open(pkg_file_path, 'w')