diff --git a/coverage/config/caliptra_cov_cfg.yml b/coverage/config/caliptra_cov_cfg.yml index 8a43e9fa5..3266626ee 100644 --- a/coverage/config/caliptra_cov_cfg.yml +++ b/coverage/config/caliptra_cov_cfg.yml @@ -8,7 +8,7 @@ variables: COV_DISK: ${PRJ_COV_DISK}/integration_lib - NIGHTLY_SAMPLE_CNT: 7 + NIGHTLY_SAMPLE_CNT: 14 #24x7_SAMPLE_CNT: 14 NIGHTLY_SAMPLE_RETAIN_CNT: 30 #24x7_SAMPLE_RETAIN_CNT: 30 diff --git a/coverage/config/caliptra_merge_bench_cov_cfg.yml b/coverage/config/caliptra_merge_bench_cov_cfg.yml index 90e6948d5..919b0d1ed 100644 --- a/coverage/config/caliptra_merge_bench_cov_cfg.yml +++ b/coverage/config/caliptra_merge_bench_cov_cfg.yml @@ -7,9 +7,9 @@ # variables: - COV_DISK: ${PRJ_COV_DISK}/dbgwrap - MERGE_DIR_NAME: dbgwrap_tb_merge_bench_cov_cfg - MERGE_SAMPLE_CNT: 7 + COV_DISK: ${PRJ_COV_DISK}/integration_lib + MERGE_DIR_NAME: caliptra_merge_bench_cov_cfg + MERGE_SAMPLE_CNT: 1 MERGE_SAMPLE_RETAIN_CNT: 30 MERGE_PIPELINE_ID: ${SYSTEM_DEFINITIONID} @@ -20,26 +20,17 @@ merge: merge_opts: -flex_merge reference -flex_merge tgl -merge_across_libs search_dir: - ${COV_DISK}/${SYSTEM_DEFINITIONID}/aes_caliptra_tb: ${MERGE_SAMPLE_CNT} - ${COV_DISK}/${SYSTEM_DEFINITIONID}/csrng_caliptra_tb: ${MERGE_SAMPLE_CNT} - ${COV_DISK}/${SYSTEM_DEFINITIONID}/datavault_caliptra_tb: ${MERGE_SAMPLE_CNT} - ${COV_DISK}/${SYSTEM_DEFINITIONID}/doe_caliptra_tb: ${MERGE_SAMPLE_CNT} - ${COV_DISK}/${SYSTEM_DEFINITIONID}/ecc_caliptra_tb: ${MERGE_SAMPLE_CNT} - ${COV_DISK}/${SYSTEM_DEFINITIONID}/edn_caliptra_tb: ${MERGE_SAMPLE_CNT} - ${COV_DISK}/${SYSTEM_DEFINITIONID}/entropy_src_caliptra_tb: ${MERGE_SAMPLE_CNT} - ${COV_DISK}/${SYSTEM_DEFINITIONID}/hmac_caliptra_tb: ${MERGE_SAMPLE_CNT} - ${COV_DISK}/${SYSTEM_DEFINITIONID}/hmac_drbg_caliptra_tb: ${MERGE_SAMPLE_CNT} - ${COV_DISK}/${SYSTEM_DEFINITIONID}/keyvault_caliptra_tb: ${MERGE_SAMPLE_CNT} - ${COV_DISK}/${SYSTEM_DEFINITIONID}/kmac_caliptra_tb: ${MERGE_SAMPLE_CNT} - ${COV_DISK}/${SYSTEM_DEFINITIONID}/lc_ctrl_caliptra_tb: ${MERGE_SAMPLE_CNT} - ${COV_DISK}/${SYSTEM_DEFINITIONID}/pcrvault_caliptra_tb: ${MERGE_SAMPLE_CNT} - ${COV_DISK}/${SYSTEM_DEFINITIONID}/prim_caliptra_tb: ${MERGE_SAMPLE_CNT} - ${COV_DISK}/${SYSTEM_DEFINITIONID}/prim_generic_caliptra_tb: ${MERGE_SAMPLE_CNT} - ${COV_DISK}/${SYSTEM_DEFINITIONID}/sha256_caliptra_tb: ${MERGE_SAMPLE_CNT} + ${COV_DISK}/${SYSTEM_DEFINITIONID}/caliptra_top_tb: ${MERGE_SAMPLE_CNT} ${COV_DISK}/${SYSTEM_DEFINITIONID}/sha512_caliptra_tb: ${MERGE_SAMPLE_CNT} - ${COV_DISK}/${SYSTEM_DEFINITIONID}/sha512_masked_caliptra_tb: ${MERGE_SAMPLE_CNT} ${COV_DISK}/${SYSTEM_DEFINITIONID}/soc_ifc_caliptra_tb: ${MERGE_SAMPLE_CNT} - ${COV_DISK}/${SYSTEM_DEFINITIONID}/uart_caliptra_tb: ${MERGE_SAMPLE_CNT} + ${COV_DISK}/${SYSTEM_DEFINITIONID}/uvmf_2022: ${MERGE_SAMPLE_CNT} + ${COV_DISK}/${SYSTEM_DEFINITIONID}/uvmf_caliptra_top: ${MERGE_SAMPLE_CNT} + ${COV_DISK}/${SYSTEM_DEFINITIONID}/uvmf_ecc: ${MERGE_SAMPLE_CNT} + ${COV_DISK}/${SYSTEM_DEFINITIONID}/uvmf_hmac: ${MERGE_SAMPLE_CNT} + ${COV_DISK}/${SYSTEM_DEFINITIONID}/uvmf_kv: ${MERGE_SAMPLE_CNT} + ${COV_DISK}/${SYSTEM_DEFINITIONID}/uvmf_pv: ${MERGE_SAMPLE_CNT} + ${COV_DISK}/${SYSTEM_DEFINITIONID}/uvmf_sha512: ${MERGE_SAMPLE_CNT} + ${COV_DISK}/${SYSTEM_DEFINITIONID}/uvmf_soc_ifc: ${MERGE_SAMPLE_CNT} target_dir: ${COV_DISK}/${SYSTEM_DEFINITIONID}/${MERGE_DIR_NAME}/nightly_merge_${BUILD_BUILDID}_${PIPELINE_START_TIME} diff --git a/src/integration/asserts/caliptra_top_sva.sv b/src/integration/asserts/caliptra_top_sva.sv index 15c20b7f4..0c5ce5a1f 100644 --- a/src/integration/asserts/caliptra_top_sva.sv +++ b/src/integration/asserts/caliptra_top_sva.sv @@ -34,6 +34,7 @@ `define SOC_IFC_TOP_PATH `CPTRA_TOP_PATH.soc_ifc_top1 `define WDT_PATH `SOC_IFC_TOP_PATH.i_wdt +`define SVA_RDC_CLK `CPTRA_TOP_PATH.rdc_clk_cg `define SVA_CLK caliptra_top_tb.core_clk `define SVA_RST caliptra_top_tb.cptra_rst_b @@ -56,12 +57,15 @@ module caliptra_top_sva //TODO: add disable condition based on doe cmd reg DOE_lock_uds_set: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) disable iff (~`SVA_RST) $rose(`DOE_PATH.flow_done) && $past(doe_cmd_reg_t'(`DOE_PATH.doe_cmd_reg.cmd) == DOE_UDS) |=> `DOE_PATH.lock_uds_flow ) else $display("SVA ERROR: lock_uds_flow was not set after UDS flow"); + //Note: lock + reset checks will use ungated clock. Using RDC clk throws the SVA off in the very first cycle where lock was 0 + //but there's no $past value to compare against. This problem doesn't exist when using ungated clk because in the first cycle, + //pwrgood is also 0, so SVA is disabled. DOE_lock_uds_cold_reset: assert property ( @(posedge `SVA_CLK) ~`DOE_PATH.hard_rst_b |-> (`DOE_PATH.lock_uds_flow == 0) @@ -75,7 +79,7 @@ module caliptra_top_sva ) else $display("SVA ERROR: lock_uds_flow toggled after warm reset"); DOE_lock_fe_set: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) disable iff (~`SVA_RST) $rose(`DOE_PATH.flow_done) && $past(doe_cmd_reg_t'(`DOE_PATH.doe_cmd_reg.cmd) == DOE_FE) |=> `DOE_PATH.lock_fe_flow ) @@ -94,14 +98,18 @@ module caliptra_top_sva ) else $display("SVA ERROR: lock_fe_flow toggled after warm reset"); + //Corner case: when clear_obf_secrets and reset events happen in the same cycle, reset deassertion will cause SVA to start checking + //But if clear_obf_secrets was already 1 (not a pulse), it expects to see status valid in the next clk, but in design, it takes an extra + //cycle to update status. Adding a 1 cycle delay to avoid this case by starting the check when reset is deasserted DOE_clear_obf_status_valid: assert property ( - @(posedge `SVA_CLK) - `CPTRA_TOP_PATH.clear_obf_secrets |=> (`DOE_REG_PATH.field_storage.DOE_STATUS.VALID.value && `DOE_REG_PATH.field_storage.DOE_STATUS.DEOBF_SECRETS_CLEARED.value) + @(posedge `SVA_RDC_CLK) + disable iff (~`DOE_PATH.rst_b) + `CPTRA_TOP_PATH.clear_obf_secrets && `DOE_PATH.rst_b |=> (`DOE_REG_PATH.field_storage.DOE_STATUS.VALID.value && `DOE_REG_PATH.field_storage.DOE_STATUS.DEOBF_SECRETS_CLEARED.value) ) else $display("SVA ERROR: DOE STATUS valid bit not set after clear obf secrets cmd"); KV_haddr_valid: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) disable iff (~`KEYVAULT_PATH.hsel_i) `KEYVAULT_PATH.hsel_i |-> !$isunknown(`KEYVAULT_PATH.haddr_i) ) @@ -111,14 +119,14 @@ module caliptra_top_sva for(genvar entry=0; entry < KV_NUM_KEYS; entry++) begin for(genvar dword = 0; dword < KV_NUM_DWORDS; dword++) begin KV_debug_value0: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) disable iff(!`KEYVAULT_PATH.cptra_pwrgood) (`KEYVAULT_PATH.flush_keyvault || `SOC_IFC_TOP_PATH.cptra_error_fatal || `CPTRA_TOP_PATH.scan_mode) && (`KEYVAULT_PATH.kv_reg_hwif_out.CLEAR_SECRETS.sel_debug_value.value == 0) && `KEYVAULT_PATH.cptra_pwrgood |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[entry][dword] == CLP_DEBUG_MODE_KV_0) ) else $display("SVA ERROR: KV not flushed with correct debug values"); KV_debug_value1: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) disable iff(!`KEYVAULT_PATH.cptra_pwrgood) (`KEYVAULT_PATH.flush_keyvault || `SOC_IFC_TOP_PATH.cptra_error_fatal || `CPTRA_TOP_PATH.scan_mode) && (`KEYVAULT_PATH.kv_reg_hwif_out.CLEAR_SECRETS.sel_debug_value.value == 1) && `KEYVAULT_PATH.cptra_pwrgood |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[entry][dword] == CLP_DEBUG_MODE_KV_1) ) @@ -131,7 +139,7 @@ module caliptra_top_sva for(genvar dword = 0; dword < KV_NUM_DWORDS; dword++) begin //sha512 block read kv_sha512_block_r_flow: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) $rose(`SHA512_PATH.kv_src_done & ~`SHA512_PATH.pcr_hash_extend_ip) && (dword < (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_CTRL[`SHA512_PATH.kv_read.read_entry].last_dword + 1)) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_read.read_entry][dword] == `SHA512_PATH.block_reg[dword]) ) else $display("SVA ERROR: SHA384 block mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_read.read_entry][dword], `SHA512_PATH.block_reg[dword]); @@ -139,7 +147,7 @@ module caliptra_top_sva //sha512 digest write if (dword < SHA512_DIG_NUM_DWORDS) begin kv_sha512_digest_w_flow: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `SHA512_PATH.kv_dest_done & ~`SHA512_PATH.pcr_hash_extend_ip |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_write_ctrl_reg.write_entry][dword] == `SHA512_PATH.kv_reg[(KV_NUM_DWORDS-1) - dword]) ) else $display("SVA ERROR: SHA384 digest mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`SHA512_PATH.kv_write_ctrl_reg.write_entry][dword], `SHA512_PATH.kv_reg[(KV_NUM_DWORDS-1) - dword]); @@ -147,7 +155,7 @@ module caliptra_top_sva //hmac block read kv_hmac_block_r_flow: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) $rose(`HMAC_PATH.kv_block_done) && (dword < (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_CTRL[`HMAC_PATH.kv_read[1].read_entry].last_dword + 1)) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[1].read_entry][dword] == `HMAC_PATH.block_reg[dword]) ) else $display("SVA ERROR: HMAC384 block mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[1].read_entry][dword], `HMAC_PATH.block_reg[dword]); @@ -155,7 +163,7 @@ module caliptra_top_sva //hmac key read if (dword < HMAC_KEY_NUM_DWORDS) begin kv_hmac_key_r_flow: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) $fell(`HMAC_PATH.kv_key_write_en) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[0].read_entry][dword] == `HMAC_PATH.key_reg[dword]) ) else $display("SVA ERROR: HMAC384 key mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_read[0].read_entry][dword], `HMAC_PATH.key_reg[dword]); @@ -164,7 +172,7 @@ module caliptra_top_sva //hmac tag write if (dword < HMAC_TAG_NUM_DWORDS) begin kv_hmac_tag_w_flow: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `HMAC_PATH.kv_write_done |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_write_ctrl_reg.write_entry][dword] == `HMAC_PATH.kv_reg[(`HMAC_PATH.TAG_NUM_DWORDS-1) - dword]) ) else $display("SVA ERROR: HMAC384 tag mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`HMAC_PATH.kv_write_ctrl_reg.write_entry][dword], `HMAC_PATH.kv_reg[(`HMAC_PATH.TAG_NUM_DWORDS-1) - dword]); @@ -174,32 +182,32 @@ module caliptra_top_sva if (dword < ECC_REG_NUM_DWORDS) begin //ecc privkey read kv_ecc_privkey_r_flow: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) $fell(`ECC_PATH.kv_privkey_write_en) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[0].read_entry][dword] == `ECC_PATH.privkey_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]) ) else $display("SVA ERROR: ECC privkey read mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[0].read_entry][dword], `ECC_PATH.privkey_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]); kv_ecc_seed_r_flow: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) $fell(`ECC_PATH.kv_seed_write_en) |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[1].read_entry][dword] == `ECC_PATH.seed_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]) ) else $display("SVA ERROR: ECC seed mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_read[1].read_entry][dword], `ECC_PATH.seed_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]); //ecc privkey write kv_ecc_privkey_w_flow: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `ECC_PATH.kv_write_done |-> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_write_ctrl_reg.write_entry][dword] == `ECC_PATH.kv_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]) ) else $display("SVA ERROR: ECC privkey write mismatch!, 0x%04x, 0x%04x", `KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`ECC_PATH.kv_write_ctrl_reg.write_entry][dword], `ECC_PATH.kv_reg[(`ECC_PATH.REG_NUM_DWORDS-1) - dword]); //ecc sign r pcr_ecc_sign_r: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `SERVICES_PATH.check_pcr_signing |-> (`SERVICES_PATH.test_vector.R[dword] == `ECC_PATH.hwif_out.ECC_SIGN_R[dword].SIGN_R.value) ) else $display("SVA ERROR: PCR SIGNING SIGN_R mismatch!, 0x%04x, 0x%04x", `SERVICES_PATH.test_vector.R[dword], `ECC_PATH.hwif_out.ECC_SIGN_R[dword].SIGN_R.value); //ecc sign s pcr_ecc_sign_s: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `SERVICES_PATH.check_pcr_signing |-> (`SERVICES_PATH.test_vector.S[dword] == `ECC_PATH.hwif_out.ECC_SIGN_S[dword].SIGN_S.value) ) else $display("SVA ERROR: PCR SIGNING SIGN_S mismatch!, 0x%04x, 0x%04x", `SERVICES_PATH.test_vector.S[dword], `ECC_PATH.hwif_out.ECC_SIGN_S[dword].SIGN_S.value); @@ -212,7 +220,7 @@ module caliptra_top_sva begin: UDS_data_check for(genvar dword = 0; dword < `CLP_OBF_UDS_DWORDS; dword++) begin DOE_UDS_data_check: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) disable iff (`CPTRA_TOP_PATH.scan_mode || !`CPTRA_TOP_PATH.security_state.debug_locked) (`SERVICES_PATH.WriteData == 'hEC && `SERVICES_PATH.mailbox_write) |=> ##[1:$] $rose(`DOE_PATH.lock_uds_flow) |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword] == `SERVICES_PATH.doe_test_vector.uds_plaintext[dword]) @@ -226,7 +234,7 @@ module caliptra_top_sva for(genvar dword = 0; dword < `CLP_OBF_FE_DWORDS; dword++) begin DOE_FE_data_check: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) disable iff (`CPTRA_TOP_PATH.scan_mode || !`CPTRA_TOP_PATH.security_state.debug_locked) (`SERVICES_PATH.WriteData == 'hED && `SERVICES_PATH.mailbox_write) |=> ##[1:$] $rose(`DOE_PATH.lock_fe_flow) |=> (`KEYVAULT_PATH.kv_reg1.hwif_out.KEY_ENTRY[`DOE_REG_PATH.hwif_out.DOE_CTRL.DEST.value][dword] == `SERVICES_PATH.doe_test_vector.fe_plaintext[dword]) ) @@ -247,7 +255,7 @@ module caliptra_top_sva logic cptra_in_debug_scan_mode_fall_trans_f; logic cptra_in_debug_scan_mode_int; - always@(posedge `SVA_CLK or negedge `CPTRA_TOP_PATH.cptra_rst_b) begin + always@(posedge `SVA_RDC_CLK or negedge `CPTRA_TOP_PATH.cptra_rst_b) begin if(!`CPTRA_TOP_PATH.cptra_rst_b) begin clear_obf_secrets_f <= 'b0; clear_obf_secrets_ff <= 'b0; @@ -258,7 +266,7 @@ module caliptra_top_sva end end - always@(posedge `SVA_CLK or negedge `CPTRA_TOP_PATH.cptra_rst_b) begin + always@(posedge `SVA_RDC_CLK or negedge `CPTRA_TOP_PATH.cptra_rst_b) begin if(!`CPTRA_TOP_PATH.cptra_rst_b) begin cptra_in_debug_scan_mode_f <= 'b0; cptra_in_debug_scan_mode_fall_trans_f <= 'b0; @@ -274,14 +282,14 @@ module caliptra_top_sva assign cptra_in_debug_scan_mode_int = cptra_in_debug_scan_mode_fall_trans | cptra_in_debug_scan_mode_fall_trans_f; UDS_fuse_wr_check: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) disable iff(`CPTRA_TOP_PATH.cptra_in_debug_scan_mode || clear_obf_secrets_int || cptra_in_debug_scan_mode_int) (`SOC_IFC_TOP_PATH.soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value) |-> `CPTRA_TOP_PATH.obf_uds_seed_dbg == $past(`CPTRA_TOP_PATH.obf_uds_seed_dbg) ) else $display("SVA ERROR: Unexpected write to obf uds seed!"); FE_fuse_wr_check: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) disable iff(`CPTRA_TOP_PATH.cptra_in_debug_scan_mode || clear_obf_secrets_int || cptra_in_debug_scan_mode_int) (`SOC_IFC_TOP_PATH.soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value) |-> `CPTRA_TOP_PATH.obf_field_entropy_dbg == $past(`CPTRA_TOP_PATH.obf_field_entropy_dbg) ) @@ -291,7 +299,7 @@ module caliptra_top_sva generate for(genvar dword = 0; dword < SHA256_BLOCK_NUM_DWORDS; dword++) begin sha256_block_zeroize: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `SHA256_PATH.hwif_out.SHA256_CTRL.ZEROIZE.value |=> (`SHA256_PATH.hwif_out.SHA256_BLOCK[dword].BLOCK.value == 0) ) else $display("SVA ERROR: SHA256 block zeroize mismatch!"); @@ -299,7 +307,7 @@ module caliptra_top_sva for(genvar dword = 0; dword < SHA256_DIG_NUM_DWORDS; dword++) begin sha256_digest_zeroize: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `SHA256_PATH.hwif_out.SHA256_CTRL.ZEROIZE.value |=> (`SHA256_PATH.digest_reg[dword] == 0) & (`SHA256_PATH.i_sha256_reg.decoded_reg_strb.SHA256_DIGEST[dword] == 0) ) else $display("SVA ERROR: SHA256 digest zeroize mismatch!"); @@ -307,7 +315,7 @@ module caliptra_top_sva for(genvar dword = 0; dword < SHA512_BLOCK_NUM_DWORDS; dword++) begin sha512_block_zeroize: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `SHA512_PATH.hwif_out.SHA512_CTRL.ZEROIZE.value |=> (`SHA512_PATH.hwif_out.SHA512_BLOCK[dword].BLOCK.value == 0) ) else $display("SVA ERROR: SHA512 block zeroize mismatch!"); @@ -315,7 +323,7 @@ module caliptra_top_sva for(genvar dword = 0; dword < SHA512_DIG_NUM_DWORDS; dword++) begin sha512_digest_zeroize: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `SHA512_PATH.hwif_out.SHA512_CTRL.ZEROIZE.value |=> (`SHA512_PATH.digest_reg[dword] == 0) & (`SHA512_PATH.i_sha512_reg.decoded_reg_strb.SHA512_DIGEST[dword] == 0) ) else $display("SVA ERROR: SHA512 digest zeroize mismatch!"); @@ -323,7 +331,7 @@ module caliptra_top_sva for(genvar dword = 0; dword < HMAC_KEY_NUM_DWORDS; dword++) begin hmac_key_zeroize: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `HMAC_PATH.hwif_out.HMAC384_CTRL.ZEROIZE.value |=> (`HMAC_PATH.hwif_out.HMAC384_KEY[dword].KEY.value == 0) ) else $display("SVA ERROR: HMAC384 key zeroize mismatch!"); @@ -331,7 +339,7 @@ module caliptra_top_sva for(genvar dword = 0; dword < HMAC_BLOCK_NUM_DWORDS; dword++) begin hmac_block_zeroize: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `HMAC_PATH.hwif_out.HMAC384_CTRL.ZEROIZE.value |=> (`HMAC_PATH.hwif_out.HMAC384_BLOCK[dword].BLOCK.value == 0) ) else $display("SVA ERROR: HMAC384 block zeroize mismatch!"); @@ -339,7 +347,7 @@ module caliptra_top_sva for(genvar dword = 0; dword < HMAC_TAG_NUM_DWORDS; dword++) begin hmac_tag_zeroize: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `HMAC_PATH.hwif_out.HMAC384_CTRL.ZEROIZE.value |=> (`HMAC_PATH.tag_reg[dword] == 0) & (`HMAC_PATH.i_hmac_reg.decoded_reg_strb.HMAC384_TAG[dword] == 0) ) else $display("SVA ERROR: HMAC384 tag zeroize mismatch!"); @@ -348,7 +356,7 @@ module caliptra_top_sva for(genvar dword = 0; dword < ECC_REG_NUM_DWORDS; dword++) begin ecc_reg_zeroize: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `ECC_PATH.hwif_out.ECC_CTRL.ZEROIZE.value |=> (`ECC_PATH.hwif_out.ECC_SEED[dword].SEED.value == 0) & (`ECC_PATH.hwif_out.ECC_NONCE[dword].NONCE.value == 0) & (`ECC_PATH.hwif_out.ECC_PRIVKEY_IN[dword].PRIVKEY_IN.value == 0) & (`ECC_PATH.hwif_out.ECC_MSG[dword].MSG.value == 0) & (`ECC_PATH.hwif_out.ECC_PUBKEY_X[dword].PUBKEY_X.value == 0) & (`ECC_PATH.hwif_out.ECC_PUBKEY_Y[dword].PUBKEY_Y.value == 0) & (`ECC_PATH.hwif_out.ECC_SIGN_R[dword].SIGN_R.value == 0) & (`ECC_PATH.hwif_out.ECC_SIGN_S[dword].SIGN_S.value == 0) & (`ECC_PATH.hwif_out.ECC_VERIFY_R[dword].VERIFY_R.value == 0) & (`ECC_PATH.hwif_out.ECC_IV[dword].IV.value == 0) & @@ -359,7 +367,7 @@ module caliptra_top_sva for(genvar addr = 0; addr < ECC_MEM_ADDR; addr++) begin ecc_mem_zeroize: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `ECC_PATH.hwif_out.ECC_CTRL.ZEROIZE.value |=> (`ECC_PATH.ecc_arith_unit_i.ram_tdp_file_i.mem[addr] == 0) ) else $display("SVA ERROR: ECC mem zeroize mismatch!"); @@ -375,7 +383,7 @@ module caliptra_top_sva endgenerate sha512_masked_core_digest_zeroize: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `ECC_PATH.hwif_out.ECC_CTRL.ZEROIZE.value |=> (`SHA512_MASKED_PATH.digest == 0) & (`SHA512_MASKED_PATH.a_reg == 0) & (`SHA512_MASKED_PATH.b_reg == 0) & (`SHA512_MASKED_PATH.c_reg == 0) & (`SHA512_MASKED_PATH.d_reg == 0) & (`SHA512_MASKED_PATH.e_reg == 0) & (`SHA512_MASKED_PATH.f_reg == 0) & (`SHA512_MASKED_PATH.g_reg == 0) & (`SHA512_MASKED_PATH.h_reg == 0) ) else $display("SVA ERROR: SHA512_masked_core digest zeroize mismatch!"); @@ -391,7 +399,7 @@ module caliptra_top_sva generate for(client = 0; client < KV_NUM_WRITE; client++) begin KV_client_wrdata_not_unknown: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) disable iff (!`KEYVAULT_PATH.kv_write[client].write_en || !`KEYVAULT_PATH.rst_b) `KEYVAULT_PATH.kv_write[client].write_en |-> !$isunknown(`KEYVAULT_PATH.kv_write[client].write_data) ) @@ -400,7 +408,7 @@ module caliptra_top_sva for(client = 0; client < KV_NUM_READ; client++) begin KV_client_rddata_not_unknown: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) disable iff (!`KEYVAULT_PATH.rst_b) !$isunknown(`KEYVAULT_PATH.kv_rd_resp[client].read_data) ) @@ -461,25 +469,25 @@ module caliptra_top_sva //VALID flag SVA sha512_valid_flag: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `SHA512_PATH.digest_valid_reg |-> `SHA512_PATH.ready_reg ) else $display("SVA ERROR: SHA512 VALID flag mismatch!"); sha256_valid_flag: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `SHA256_PATH.digest_valid_reg |-> `SHA256_PATH.ready_reg ) else $display("SVA ERROR: SHA256 VALID flag mismatch!"); HMAC_valid_flag: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `HMAC_PATH.tag_valid_reg |-> `HMAC_PATH.ready_reg ) else $display("SVA ERROR: HMAC VALID flag mismatch!"); ECC_valid_flag: assert property ( - @(posedge `SVA_CLK) + @(posedge `SVA_RDC_CLK) `ECC_PATH.dsa_valid_reg |-> `ECC_PATH.dsa_ready_reg ) else $display("SVA ERROR: ECC VALID flag mismatch!"); diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_rand_sequence.svh b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_rand_sequence.svh index 49086ccac..d8447b61e 100644 --- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_rand_sequence.svh +++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/sequences/src/caliptra_top_rand_sequence.svh @@ -53,8 +53,18 @@ class caliptra_top_rand_sequence extends caliptra_top_bench_sequence_base; IDX_SOC_IFC_ENV_MBOX_MAX, IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_SMALL, IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_MEDIUM, + IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_LARGE, IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_SMALL, IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_MEDIUM, + IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_LARGE, + IDX_SOC_IFC_ENV_MBOX_RAND_MEDIUM_INTERFERENCE, + IDX_SOC_IFC_ENV_MBOX_DLEN_INVALID, + IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_SMALL, + IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_MEDIUM, + IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_LARGE, + IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_SMALL, + IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_MEDIUM, + IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_LARGE, IDX_SOC_IFC_ENV_MBOX_MULTI_AGENT, IDX_SOC_IFC_ENV_RST_WARM, IDX_SOC_IFC_ENV_RST_COLD, @@ -72,25 +82,35 @@ class caliptra_top_rand_sequence extends caliptra_top_bench_sequence_base; // Choose rand weights for each sequence to determine run frequency constraint avail_env_seqs_c { rand_seq_idx dist { - //IDX_SOC_IFC_ENV_MBOX_RAND_FW := 0, - IDX_SOC_IFC_ENV_MBOX_RAND_SMALL := 125, - IDX_SOC_IFC_ENV_MBOX_RAND_MEDIUM := 100, - IDX_SOC_IFC_ENV_MBOX_RAND_LARGE := 1, - IDX_SOC_IFC_ENV_MBOX_MIN := 100, - IDX_SOC_IFC_ENV_MBOX_MAX := 10, - IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_SMALL := 125, - IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_MEDIUM := 100, - IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_SMALL := 100, - IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_MEDIUM := 100, - IDX_SOC_IFC_ENV_MBOX_MULTI_AGENT := 100, - IDX_SOC_IFC_ENV_RST_WARM := 100, - IDX_SOC_IFC_ENV_RST_COLD := 100, - IDX_SOC_IFC_ENV_MBOX_RST_WARM_RAND_MEDIUM := 100, - IDX_SOC_IFC_ENV_MBOX_RST_COLD_RAND_MEDIUM := 100, - IDX_SOC_IFC_ENV_MBOX_SHA_ACCEL := 100, - IDX_SOC_IFC_ENV_SHA_ACCEL := 100, - IDX_SOC_IFC_ENV_FW_UPD := 10, - IDX_SOC_IFC_ENV_MBOX_UC_REG_ACCESS := 100 + //IDX_SOC_IFC_ENV_MBOX_RAND_FW := 0, + IDX_SOC_IFC_ENV_MBOX_RAND_SMALL := 100, + IDX_SOC_IFC_ENV_MBOX_RAND_MEDIUM := 100, + IDX_SOC_IFC_ENV_MBOX_RAND_LARGE := 10, + IDX_SOC_IFC_ENV_MBOX_MIN := 100, + IDX_SOC_IFC_ENV_MBOX_MAX := 10, + IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_SMALL := 100, + IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_MEDIUM := 100, + IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_LARGE := 10, + IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_SMALL := 100, + IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_MEDIUM := 100, + IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_LARGE := 10, + IDX_SOC_IFC_ENV_MBOX_RAND_MEDIUM_INTERFERENCE := 100, + IDX_SOC_IFC_ENV_MBOX_DLEN_INVALID := 10, + IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_SMALL := 100, + IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_MEDIUM := 100, + IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_LARGE := 10, + IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_SMALL := 100, + IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_MEDIUM := 100, + IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_LARGE := 10, + IDX_SOC_IFC_ENV_MBOX_MULTI_AGENT := 200, + IDX_SOC_IFC_ENV_RST_WARM := 100, + IDX_SOC_IFC_ENV_RST_COLD := 100, + IDX_SOC_IFC_ENV_MBOX_RST_WARM_RAND_MEDIUM := 100, + IDX_SOC_IFC_ENV_MBOX_RST_COLD_RAND_MEDIUM := 100, + IDX_SOC_IFC_ENV_MBOX_SHA_ACCEL := 100, + IDX_SOC_IFC_ENV_SHA_ACCEL := 100, + IDX_SOC_IFC_ENV_FW_UPD := 10, + IDX_SOC_IFC_ENV_MBOX_UC_REG_ACCESS := 100 }; } constraint iter_count_c { @@ -231,12 +251,42 @@ class caliptra_top_rand_sequence extends caliptra_top_bench_sequence_base; end obj = soc_ifc_env_mbox_rand_pauser_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii)); end + IDX_SOC_IFC_ENV_MBOX_RAND_PAUSER_LARGE: begin + if (!pauser_valid_initialized) begin + if(!soc_ifc_env_pauser_init_seq.randomize()) + `uvm_fatal("CALIPTRA_TOP_RAND_TEST", "caliptra_top_rand_sequence::body() - soc_ifc_env_pauser_init_seq randomization failed") + soc_ifc_env_pauser_init_seq.start(top_configuration.soc_ifc_subenv_config.vsqr); + + `uvm_info("CALIPTRA_TOP_RAND_TEST", "SoC completed PAUSER VALID initialization", UVM_LOW) + pauser_valid_initialized = 1'b1; + end + obj = soc_ifc_env_mbox_rand_pauser_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii)); + end IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_SMALL: begin obj = soc_ifc_env_mbox_rand_delay_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii)); end IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_MEDIUM: begin obj = soc_ifc_env_mbox_rand_delay_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii)); end + IDX_SOC_IFC_ENV_MBOX_RAND_DELAY_LARGE: begin + obj = soc_ifc_env_mbox_rand_delay_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii)); + end + IDX_SOC_IFC_ENV_MBOX_RAND_MEDIUM_INTERFERENCE: + obj = soc_ifc_env_mbox_rand_medium_interference_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii)); + IDX_SOC_IFC_ENV_MBOX_DLEN_INVALID: + obj = soc_ifc_env_mbox_dlen_invalid_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii)); + IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_SMALL: + obj = soc_ifc_env_mbox_dlen_overflow_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii)); + IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_MEDIUM: + obj = soc_ifc_env_mbox_dlen_overflow_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii)); + IDX_SOC_IFC_ENV_MBOX_DLEN_OVERFLOW_LARGE: + obj = soc_ifc_env_mbox_dlen_overflow_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii)); + IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_SMALL: + obj = soc_ifc_env_mbox_dlen_underflow_small_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii)); + IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_MEDIUM: + obj = soc_ifc_env_mbox_dlen_underflow_medium_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii)); + IDX_SOC_IFC_ENV_MBOX_DLEN_UNDERFLOW_LARGE: + obj = soc_ifc_env_mbox_dlen_underflow_large_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii)); IDX_SOC_IFC_ENV_MBOX_MULTI_AGENT: // TODO PAUSER init first? obj = soc_ifc_env_mbox_rand_multi_agent_sequence_t::get_type().create_object($sformatf("soc_ifc_env_seq_ii[%0d]",ii)); diff --git a/src/keyvault/uvmf_kv/coverage/uvmf_kv_cm_hier.cfg b/src/keyvault/uvmf_kv/coverage/uvmf_kv_cm_hier.cfg new file mode 100644 index 000000000..f8b1e528f --- /dev/null +++ b/src/keyvault/uvmf_kv/coverage/uvmf_kv_cm_hier.cfg @@ -0,0 +1,4 @@ +begin line+tgl+fsm+cond+branch + +tree hdl_top.dut 0 +end + diff --git a/src/libs/rtl/apb_slv_sif.sv b/src/libs/rtl/apb_slv_sif.sv index e0c0d3f4f..eb791e381 100644 --- a/src/libs/rtl/apb_slv_sif.sv +++ b/src/libs/rtl/apb_slv_sif.sv @@ -77,12 +77,11 @@ end always_comb access_phase = PSEL & PENABLE; //drive ready if no hold from component -always_comb PREADY = (dv & access_phase) ? ~req_hold : '1; +always_comb PREADY = dv ? ~req_hold : '1; //drive read data from component -always_comb PRDATA = (dv & access_phase) ? rdata : '0; +always_comb PRDATA = rdata; //drive error from component for valid access, drive error for invalid access phase -always_comb PSLVERR = (dv & access_phase) ? slverr : - access_phase ? '1 : '0; +always_comb PSLVERR = slverr; diff --git a/src/soc_ifc/.gitignore b/src/soc_ifc/.gitignore index c233f856a..dac06b307 100644 --- a/src/soc_ifc/.gitignore +++ b/src/soc_ifc/.gitignore @@ -6,4 +6,3 @@ docs tb/EXP -# stimulus/testsuites/commit_regress.yml diff --git a/src/soc_ifc/rtl/mbox.sv b/src/soc_ifc/rtl/mbox.sv index f03f55da6..2aece02b6 100644 --- a/src/soc_ifc/rtl/mbox.sv +++ b/src/soc_ifc/rtl/mbox.sv @@ -60,8 +60,9 @@ module mbox ); -localparam DEPTH = (SIZE_KB * 1024 * 8) / DATA_W; -localparam MBOX_SIZE_IN_DW = (SIZE_KB*1024)/4; +localparam MBOX_SIZE_IN_BYTES = SIZE_KB*1024; +localparam MBOX_SIZE_IN_DW = (MBOX_SIZE_IN_BYTES)/4; +localparam DEPTH = (MBOX_SIZE_IN_DW * 32) / DATA_W; //this module is used to instantiate a single mailbox instance //requests within the address space of this mailbox are routed here from the top level @@ -213,7 +214,7 @@ always_comb arc_MBOX_EXECUTE_SOC_MBOX_ERROR = req_dv && req_data.soc_req && //by the client filling the mailbox is used for masking the data //Store the dlen as a ptr to the last entry always_comb latch_dlen_in_dws = arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_UC | arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_SOC | arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_SOC; -always_comb mbox_dlen_in_dws = (hwif_out.mbox_dlen.length.value >= MBOX_SIZE_IN_DW) ? MBOX_SIZE_IN_DW : +always_comb mbox_dlen_in_dws = (hwif_out.mbox_dlen.length.value >= MBOX_SIZE_IN_BYTES) ? MBOX_SIZE_IN_DW : (hwif_out.mbox_dlen.length.value >> 2) + (hwif_out.mbox_dlen.length.value[0] | hwif_out.mbox_dlen.length.value[1]); //latched dlen is the smaller of the programmed dlen or the current wrptr //this avoids a case where a sender writes less than programmed and the receiver can read beyond that diff --git a/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh b/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh index a5f151403..7e67ffbbd 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh +++ b/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh @@ -1489,6 +1489,7 @@ input bit [1-1:0] notif_cmd_avail_en, input bit [1-1:0] notif_mbox_ecc_cor_en, input bit [1-1:0] notif_debug_locked_en, + input bit [1-1:0] notif_scan_mode_en, input bit [1-1:0] notif_soc_req_lock_en, input bit [1-1:0] notif_gen_in_toggle_en ); @@ -1496,6 +1497,7 @@ notif_cmd_avail_en_cp : coverpoint notif_cmd_avail_en; notif_mbox_ecc_cor_en_cp : coverpoint notif_mbox_ecc_cor_en; notif_debug_locked_en_cp : coverpoint notif_debug_locked_en; + notif_scan_mode_en_cp : coverpoint notif_scan_mode_en; notif_soc_req_lock_en_cp : coverpoint notif_soc_req_lock_en; notif_gen_in_toggle_en_cp : coverpoint notif_gen_in_toggle_en; @@ -1575,7 +1577,7 @@ endgroup - /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__NOTIF_INTR_T_NOTIF_CMD_AVAIL_STS_1871606B_NOTIF_DEBUG_LOCKED_STS_5F024102_NOTIF_GEN_IN_TOGGLE_STS_59F84B64_NOTIF_MBOX_ECC_COR_STS_5C3D26BB_NOTIF_SOC_REQ_LOCK_STS_DEDDDE70 COVERGROUPS -----------------------*/ + /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__NOTIF_INTR_T_NOTIF_CMD_AVAIL_STS_1871606B_NOTIF_DEBUG_LOCKED_STS_5F024102_NOTIF_GEN_IN_TOGGLE_STS_59F84B64_NOTIF_MBOX_ECC_COR_STS_5C3D26BB_NOTIF_SCAN_MODE_STS_122F6367_NOTIF_SOC_REQ_LOCK_STS_DEDDDE70 COVERGROUPS -----------------------*/ covergroup soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { @@ -1591,6 +1593,7 @@ input bit [1-1:0] notif_cmd_avail_sts, input bit [1-1:0] notif_mbox_ecc_cor_sts, input bit [1-1:0] notif_debug_locked_sts, + input bit [1-1:0] notif_scan_mode_sts, input bit [1-1:0] notif_soc_req_lock_sts, input bit [1-1:0] notif_gen_in_toggle_sts ); @@ -1598,6 +1601,7 @@ notif_cmd_avail_sts_cp : coverpoint notif_cmd_avail_sts; notif_mbox_ecc_cor_sts_cp : coverpoint notif_mbox_ecc_cor_sts; notif_debug_locked_sts_cp : coverpoint notif_debug_locked_sts; + notif_scan_mode_sts_cp : coverpoint notif_scan_mode_sts; notif_soc_req_lock_sts_cp : coverpoint notif_soc_req_lock_sts; notif_gen_in_toggle_sts_cp : coverpoint notif_gen_in_toggle_sts; @@ -1653,6 +1657,7 @@ input bit [1-1:0] notif_cmd_avail_trig, input bit [1-1:0] notif_mbox_ecc_cor_trig, input bit [1-1:0] notif_debug_locked_trig, + input bit [1-1:0] notif_scan_mode_trig, input bit [1-1:0] notif_soc_req_lock_trig, input bit [1-1:0] notif_gen_in_toggle_trig ); @@ -1660,6 +1665,7 @@ notif_cmd_avail_trig_cp : coverpoint notif_cmd_avail_trig; notif_mbox_ecc_cor_trig_cp : coverpoint notif_mbox_ecc_cor_trig; notif_debug_locked_trig_cp : coverpoint notif_debug_locked_trig; + notif_scan_mode_trig_cp : coverpoint notif_scan_mode_trig; notif_soc_req_lock_trig_cp : coverpoint notif_soc_req_lock_trig; notif_gen_in_toggle_trig_cp : coverpoint notif_gen_in_toggle_trig; @@ -1749,27 +1755,6 @@ endgroup - /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_FBF3C714 COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_fbf3c714_bit_cg with function sample(input bit reg_bit); - option.per_instance = 1; - reg_bit_cp : coverpoint reg_bit { - bins value[2] = {0,1}; - } - reg_bit_edge_cp : coverpoint reg_bit { - bins rise = (0 => 1); - bins fall = (1 => 0); - } - - endgroup - covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_fbf3c714_fld_cg with function sample( - input bit [32-1:0] cnt - ); - option.per_instance = 1; - option.auto_bin_max = 64; - cnt_cp : coverpoint cnt; - - endgroup - /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_25E76B6F COVERGROUPS -----------------------*/ covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_25e76b6f_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; @@ -1917,6 +1902,27 @@ endgroup + /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_FBF3C714 COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_fbf3c714_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_fbf3c714_fld_cg with function sample( + input bit [32-1:0] cnt + ); + option.per_instance = 1; + option.auto_bin_max = 64; + cnt_cp : coverpoint cnt; + + endgroup + /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_B9BDDABE COVERGROUPS -----------------------*/ covergroup soc_ifc_reg__intr_block_t__intr_count_t_cnt_b9bddabe_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; @@ -2179,8 +2185,8 @@ endgroup - /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_246489BD COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_246489bd_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_F5D8AFE0 COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f5d8afe0_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -2191,7 +2197,7 @@ } endgroup - covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_246489bd_fld_cg with function sample( + covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f5d8afe0_fld_cg with function sample( input bit [1-1:0] pulse ); option.per_instance = 1; @@ -2199,8 +2205,8 @@ endgroup - /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_D6ED4D1E COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_d6ed4d1e_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_246489BD COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_246489bd_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -2211,7 +2217,7 @@ } endgroup - covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_d6ed4d1e_fld_cg with function sample( + covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_246489bd_fld_cg with function sample( input bit [1-1:0] pulse ); option.per_instance = 1; @@ -2219,8 +2225,8 @@ endgroup - /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_F5D8AFE0 COVERGROUPS -----------------------*/ - covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f5d8afe0_bit_cg with function sample(input bit reg_bit); + /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_D6ED4D1E COVERGROUPS -----------------------*/ + covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_d6ed4d1e_bit_cg with function sample(input bit reg_bit); option.per_instance = 1; reg_bit_cp : coverpoint reg_bit { bins value[2] = {0,1}; @@ -2231,7 +2237,7 @@ } endgroup - covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f5d8afe0_fld_cg with function sample( + covergroup soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_d6ed4d1e_fld_cg with function sample( input bit [1-1:0] pulse ); option.per_instance = 1; diff --git a/src/soc_ifc/rtl/soc_ifc_reg_sample.svh b/src/soc_ifc/rtl/soc_ifc_reg_sample.svh index e448b38fc..70d5eb1de 100644 --- a/src/soc_ifc/rtl/soc_ifc_reg_sample.svh +++ b/src/soc_ifc/rtl/soc_ifc_reg_sample.svh @@ -1687,11 +1687,12 @@ foreach(notif_cmd_avail_en_bit_cg[bt]) this.notif_cmd_avail_en_bit_cg[bt].sample(data[0 + bt]); foreach(notif_mbox_ecc_cor_en_bit_cg[bt]) this.notif_mbox_ecc_cor_en_bit_cg[bt].sample(data[1 + bt]); foreach(notif_debug_locked_en_bit_cg[bt]) this.notif_debug_locked_en_bit_cg[bt].sample(data[2 + bt]); - foreach(notif_soc_req_lock_en_bit_cg[bt]) this.notif_soc_req_lock_en_bit_cg[bt].sample(data[3 + bt]); - foreach(notif_gen_in_toggle_en_bit_cg[bt]) this.notif_gen_in_toggle_en_bit_cg[bt].sample(data[4 + bt]); + foreach(notif_scan_mode_en_bit_cg[bt]) this.notif_scan_mode_en_bit_cg[bt].sample(data[3 + bt]); + foreach(notif_soc_req_lock_en_bit_cg[bt]) this.notif_soc_req_lock_en_bit_cg[bt].sample(data[4 + bt]); + foreach(notif_gen_in_toggle_en_bit_cg[bt]) this.notif_gen_in_toggle_en_bit_cg[bt].sample(data[5 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[0:0]/*notif_cmd_avail_en*/ , data[1:1]/*notif_mbox_ecc_cor_en*/ , data[2:2]/*notif_debug_locked_en*/ , data[3:3]/*notif_soc_req_lock_en*/ , data[4:4]/*notif_gen_in_toggle_en*/ ); + this.fld_cg.sample( data[0:0]/*notif_cmd_avail_en*/ , data[1:1]/*notif_mbox_ecc_cor_en*/ , data[2:2]/*notif_debug_locked_en*/ , data[3:3]/*notif_scan_mode_en*/ , data[4:4]/*notif_soc_req_lock_en*/ , data[5:5]/*notif_gen_in_toggle_en*/ ); end endfunction @@ -1700,11 +1701,12 @@ foreach(notif_cmd_avail_en_bit_cg[bt]) this.notif_cmd_avail_en_bit_cg[bt].sample(notif_cmd_avail_en.get_mirrored_value() >> bt); foreach(notif_mbox_ecc_cor_en_bit_cg[bt]) this.notif_mbox_ecc_cor_en_bit_cg[bt].sample(notif_mbox_ecc_cor_en.get_mirrored_value() >> bt); foreach(notif_debug_locked_en_bit_cg[bt]) this.notif_debug_locked_en_bit_cg[bt].sample(notif_debug_locked_en.get_mirrored_value() >> bt); + foreach(notif_scan_mode_en_bit_cg[bt]) this.notif_scan_mode_en_bit_cg[bt].sample(notif_scan_mode_en.get_mirrored_value() >> bt); foreach(notif_soc_req_lock_en_bit_cg[bt]) this.notif_soc_req_lock_en_bit_cg[bt].sample(notif_soc_req_lock_en.get_mirrored_value() >> bt); foreach(notif_gen_in_toggle_en_bit_cg[bt]) this.notif_gen_in_toggle_en_bit_cg[bt].sample(notif_gen_in_toggle_en.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( notif_cmd_avail_en.get_mirrored_value() , notif_mbox_ecc_cor_en.get_mirrored_value() , notif_debug_locked_en.get_mirrored_value() , notif_soc_req_lock_en.get_mirrored_value() , notif_gen_in_toggle_en.get_mirrored_value() ); + this.fld_cg.sample( notif_cmd_avail_en.get_mirrored_value() , notif_mbox_ecc_cor_en.get_mirrored_value() , notif_debug_locked_en.get_mirrored_value() , notif_scan_mode_en.get_mirrored_value() , notif_soc_req_lock_en.get_mirrored_value() , notif_gen_in_toggle_en.get_mirrored_value() ); end endfunction @@ -1797,7 +1799,7 @@ end endfunction - /*----------------------- soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70 SAMPLE FUNCTIONS -----------------------*/ + /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__NOTIF_INTR_T_NOTIF_CMD_AVAIL_STS_1871606B_NOTIF_DEBUG_LOCKED_STS_5F024102_NOTIF_GEN_IN_TOGGLE_STS_59F84B64_NOTIF_MBOX_ECC_COR_STS_5C3D26BB_NOTIF_SCAN_MODE_STS_122F6367_NOTIF_SOC_REQ_LOCK_STS_DEDDDE70 SAMPLE FUNCTIONS -----------------------*/ function void soc_ifc_reg__intr_block_t__notif_intr_t_notif_cmd_avail_sts_1871606b_notif_debug_locked_sts_5f024102_notif_gen_in_toggle_sts_59f84b64_notif_mbox_ecc_cor_sts_5c3d26bb_notif_scan_mode_sts_122f6367_notif_soc_req_lock_sts_deddde70::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, @@ -1809,11 +1811,12 @@ foreach(notif_cmd_avail_sts_bit_cg[bt]) this.notif_cmd_avail_sts_bit_cg[bt].sample(data[0 + bt]); foreach(notif_mbox_ecc_cor_sts_bit_cg[bt]) this.notif_mbox_ecc_cor_sts_bit_cg[bt].sample(data[1 + bt]); foreach(notif_debug_locked_sts_bit_cg[bt]) this.notif_debug_locked_sts_bit_cg[bt].sample(data[2 + bt]); - foreach(notif_soc_req_lock_sts_bit_cg[bt]) this.notif_soc_req_lock_sts_bit_cg[bt].sample(data[3 + bt]); - foreach(notif_gen_in_toggle_sts_bit_cg[bt]) this.notif_gen_in_toggle_sts_bit_cg[bt].sample(data[4 + bt]); + foreach(notif_scan_mode_sts_bit_cg[bt]) this.notif_scan_mode_sts_bit_cg[bt].sample(data[3 + bt]); + foreach(notif_soc_req_lock_sts_bit_cg[bt]) this.notif_soc_req_lock_sts_bit_cg[bt].sample(data[4 + bt]); + foreach(notif_gen_in_toggle_sts_bit_cg[bt]) this.notif_gen_in_toggle_sts_bit_cg[bt].sample(data[5 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[0:0]/*notif_cmd_avail_sts*/ , data[1:1]/*notif_mbox_ecc_cor_sts*/ , data[2:2]/*notif_debug_locked_sts*/ , data[3:3]/*notif_soc_req_lock_sts*/ , data[4:4]/*notif_gen_in_toggle_sts*/ ); + this.fld_cg.sample( data[0:0]/*notif_cmd_avail_sts*/ , data[1:1]/*notif_mbox_ecc_cor_sts*/ , data[2:2]/*notif_debug_locked_sts*/ , data[3:3]/*notif_scan_mode_sts*/ , data[4:4]/*notif_soc_req_lock_sts*/ , data[5:5]/*notif_gen_in_toggle_sts*/ ); end endfunction @@ -1822,11 +1825,12 @@ foreach(notif_cmd_avail_sts_bit_cg[bt]) this.notif_cmd_avail_sts_bit_cg[bt].sample(notif_cmd_avail_sts.get_mirrored_value() >> bt); foreach(notif_mbox_ecc_cor_sts_bit_cg[bt]) this.notif_mbox_ecc_cor_sts_bit_cg[bt].sample(notif_mbox_ecc_cor_sts.get_mirrored_value() >> bt); foreach(notif_debug_locked_sts_bit_cg[bt]) this.notif_debug_locked_sts_bit_cg[bt].sample(notif_debug_locked_sts.get_mirrored_value() >> bt); + foreach(notif_scan_mode_sts_bit_cg[bt]) this.notif_scan_mode_sts_bit_cg[bt].sample(notif_scan_mode_sts.get_mirrored_value() >> bt); foreach(notif_soc_req_lock_sts_bit_cg[bt]) this.notif_soc_req_lock_sts_bit_cg[bt].sample(notif_soc_req_lock_sts.get_mirrored_value() >> bt); foreach(notif_gen_in_toggle_sts_bit_cg[bt]) this.notif_gen_in_toggle_sts_bit_cg[bt].sample(notif_gen_in_toggle_sts.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( notif_cmd_avail_sts.get_mirrored_value() , notif_mbox_ecc_cor_sts.get_mirrored_value() , notif_debug_locked_sts.get_mirrored_value() , notif_soc_req_lock_sts.get_mirrored_value() , notif_gen_in_toggle_sts.get_mirrored_value() ); + this.fld_cg.sample( notif_cmd_avail_sts.get_mirrored_value() , notif_mbox_ecc_cor_sts.get_mirrored_value() , notif_debug_locked_sts.get_mirrored_value() , notif_scan_mode_sts.get_mirrored_value() , notif_soc_req_lock_sts.get_mirrored_value() , notif_gen_in_toggle_sts.get_mirrored_value() ); end endfunction @@ -1881,11 +1885,12 @@ foreach(notif_cmd_avail_trig_bit_cg[bt]) this.notif_cmd_avail_trig_bit_cg[bt].sample(data[0 + bt]); foreach(notif_mbox_ecc_cor_trig_bit_cg[bt]) this.notif_mbox_ecc_cor_trig_bit_cg[bt].sample(data[1 + bt]); foreach(notif_debug_locked_trig_bit_cg[bt]) this.notif_debug_locked_trig_bit_cg[bt].sample(data[2 + bt]); - foreach(notif_soc_req_lock_trig_bit_cg[bt]) this.notif_soc_req_lock_trig_bit_cg[bt].sample(data[3 + bt]); - foreach(notif_gen_in_toggle_trig_bit_cg[bt]) this.notif_gen_in_toggle_trig_bit_cg[bt].sample(data[4 + bt]); + foreach(notif_scan_mode_trig_bit_cg[bt]) this.notif_scan_mode_trig_bit_cg[bt].sample(data[3 + bt]); + foreach(notif_soc_req_lock_trig_bit_cg[bt]) this.notif_soc_req_lock_trig_bit_cg[bt].sample(data[4 + bt]); + foreach(notif_gen_in_toggle_trig_bit_cg[bt]) this.notif_gen_in_toggle_trig_bit_cg[bt].sample(data[5 + bt]); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[0:0]/*notif_cmd_avail_trig*/ , data[1:1]/*notif_mbox_ecc_cor_trig*/ , data[2:2]/*notif_debug_locked_trig*/ , data[3:3]/*notif_soc_req_lock_trig*/ , data[4:4]/*notif_gen_in_toggle_trig*/ ); + this.fld_cg.sample( data[0:0]/*notif_cmd_avail_trig*/ , data[1:1]/*notif_mbox_ecc_cor_trig*/ , data[2:2]/*notif_debug_locked_trig*/ , data[3:3]/*notif_scan_mode_trig*/ , data[4:4]/*notif_soc_req_lock_trig*/ , data[5:5]/*notif_gen_in_toggle_trig*/ ); end endfunction @@ -1894,11 +1899,12 @@ foreach(notif_cmd_avail_trig_bit_cg[bt]) this.notif_cmd_avail_trig_bit_cg[bt].sample(notif_cmd_avail_trig.get_mirrored_value() >> bt); foreach(notif_mbox_ecc_cor_trig_bit_cg[bt]) this.notif_mbox_ecc_cor_trig_bit_cg[bt].sample(notif_mbox_ecc_cor_trig.get_mirrored_value() >> bt); foreach(notif_debug_locked_trig_bit_cg[bt]) this.notif_debug_locked_trig_bit_cg[bt].sample(notif_debug_locked_trig.get_mirrored_value() >> bt); + foreach(notif_scan_mode_trig_bit_cg[bt]) this.notif_scan_mode_trig_bit_cg[bt].sample(notif_scan_mode_trig.get_mirrored_value() >> bt); foreach(notif_soc_req_lock_trig_bit_cg[bt]) this.notif_soc_req_lock_trig_bit_cg[bt].sample(notif_soc_req_lock_trig.get_mirrored_value() >> bt); foreach(notif_gen_in_toggle_trig_bit_cg[bt]) this.notif_gen_in_toggle_trig_bit_cg[bt].sample(notif_gen_in_toggle_trig.get_mirrored_value() >> bt); end if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( notif_cmd_avail_trig.get_mirrored_value() , notif_mbox_ecc_cor_trig.get_mirrored_value() , notif_debug_locked_trig.get_mirrored_value() , notif_soc_req_lock_trig.get_mirrored_value() , notif_gen_in_toggle_trig.get_mirrored_value() ); + this.fld_cg.sample( notif_cmd_avail_trig.get_mirrored_value() , notif_mbox_ecc_cor_trig.get_mirrored_value() , notif_debug_locked_trig.get_mirrored_value() , notif_scan_mode_trig.get_mirrored_value() , notif_soc_req_lock_trig.get_mirrored_value() , notif_gen_in_toggle_trig.get_mirrored_value() ); end endfunction @@ -2002,31 +2008,6 @@ end endfunction - /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_fbf3c714 SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_fbf3c714::sample(uvm_reg_data_t data, - uvm_reg_data_t byte_en, - bit is_read, - uvm_reg_map map); - m_current = get(); - m_data = data; - m_is_read = is_read; - if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]); - end - if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( data[31:0]/*cnt*/ ); - end - endfunction - - function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_fbf3c714::sample_values(); - if (get_coverage(UVM_CVR_REG_BITS)) begin - foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt); - end - if (get_coverage(UVM_CVR_FIELD_VALS)) begin - this.fld_cg.sample( cnt.get_mirrored_value() ); - end - endfunction - /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_25E76B6F SAMPLE FUNCTIONS -----------------------*/ function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_25e76b6f::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, @@ -2202,6 +2183,31 @@ end endfunction + /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_FBF3C714 SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_fbf3c714::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[31:0]/*cnt*/ ); + end + endfunction + + function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_fbf3c714::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( cnt.get_mirrored_value() ); + end + endfunction + /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_B9BDDABE SAMPLE FUNCTIONS -----------------------*/ function void soc_ifc_reg__intr_block_t__intr_count_t_cnt_b9bddabe::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, @@ -2527,8 +2533,8 @@ end endfunction - /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_246489BD SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_246489bd::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_F5D8AFE0 SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f5d8afe0::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -2543,7 +2549,7 @@ end endfunction - function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_246489bd::sample_values(); + function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f5d8afe0::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt); end @@ -2552,8 +2558,8 @@ end endfunction - /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_D6ED4D1E SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_d6ed4d1e::sample(uvm_reg_data_t data, + /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_246489BD SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_246489bd::sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); @@ -2568,7 +2574,7 @@ end endfunction - function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_d6ed4d1e::sample_values(); + function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_246489bd::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt); end @@ -2577,11 +2583,11 @@ end endfunction - /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_f5d8afe0 SAMPLE FUNCTIONS -----------------------*/ - function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f5d8afe0::sample(uvm_reg_data_t data, - uvm_reg_data_t byte_en, - bit is_read, - uvm_reg_map map); + /*----------------------- SOC_IFC_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_D6ED4D1E SAMPLE FUNCTIONS -----------------------*/ + function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_d6ed4d1e::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); m_current = get(); m_data = data; m_is_read = is_read; @@ -2592,8 +2598,8 @@ this.fld_cg.sample( data[0:0]/*pulse*/ ); end endfunction - - function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_f5d8afe0::sample_values(); + + function void soc_ifc_reg__intr_block_t__intr_count_incr_t_pulse_d6ed4d1e::sample_values(); if (get_coverage(UVM_CVR_REG_BITS)) begin foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt); end diff --git a/src/soc_ifc/stimulus/tests/directed/fuse_reg_pauser_test.yml b/src/soc_ifc/stimulus/tests/directed/fuse_reg_pauser_test.yml new file mode 100644 index 000000000..9b06b5312 --- /dev/null +++ b/src/soc_ifc/stimulus/tests/directed/fuse_reg_pauser_test.yml @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +plusargs: + - +SOC_IFC_TEST='fuse_reg_pauser_test' + +testname: fuse_reg_pauser_test +seed: ${PLAYBOOK_RANDOM_SEED} diff --git a/src/soc_ifc/stimulus/testsuites/soc_ifc_commit_regress.yml b/src/soc_ifc/stimulus/testsuites/soc_ifc_commit_regress.yml index 7026a595d..292d387ba 100644 --- a/src/soc_ifc/stimulus/testsuites/soc_ifc_commit_regress.yml +++ b/src/soc_ifc/stimulus/testsuites/soc_ifc_commit_regress.yml @@ -6,6 +6,7 @@ contents: tags: ["L0", "directed", "SOC_IFC"] paths: - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_ifc_test.yml + - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_pauser_test.yml - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_prod_test.yml - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_perm_test.yml - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_lifecycle_test.yml @@ -14,6 +15,6 @@ contents: - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_pwron_test.yml - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_wrmrst_test.yml - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_invalid_test.yml - - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_ifc_intrblk_test.yml + - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_intrblk_test.yml - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/sha_acc_intrblk_test.yml - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/rvtime_reg_test.yml diff --git a/src/soc_ifc/stimulus/testsuites/soc_ifc_nightly_directed_regression.yml b/src/soc_ifc/stimulus/testsuites/soc_ifc_nightly_directed_regression.yml index 3adb0248d..2821f9aa5 100644 --- a/src/soc_ifc/stimulus/testsuites/soc_ifc_nightly_directed_regression.yml +++ b/src/soc_ifc/stimulus/testsuites/soc_ifc_nightly_directed_regression.yml @@ -5,15 +5,16 @@ contents: - generator: tags: ["L0", "directed", "nightly", "SOC_IFC"] path: "" - weight: 99 - generations: 96 + weight: 100 + generations: 100 formats: generate: "reseed {template}.yml -seed {seed}" path: "{template_basename}__{seed}.yml" templates: ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_ifc_test : {weight 12} + ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_pauser_test : {weight 3} ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_prod_test : {weight 12} - ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_perm_test: {weight 14} + ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_perm_test: {weight 12} ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/fuse_reg_lifecycle_test: {weight 6} ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_test: {weight 16} ${CALIPTRA_ROOT}/src/soc_ifc/stimulus/tests/directed/soc_reg_pwron_test: {weight 12} diff --git a/src/soc_ifc/tb/fuse_reg_pauser_test.svh b/src/soc_ifc/tb/fuse_reg_pauser_test.svh new file mode 100644 index 000000000..216017d99 --- /dev/null +++ b/src/soc_ifc/tb/fuse_reg_pauser_test.svh @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== + + +`define FORLOOP_COMB(x) always_comb for (int j = 0; j < x; j++) +`define REG_HIER_PFX dut.i_soc_ifc_reg.field_storage +`define STR_RMPFX(astr, bstr) astr.substr(bstr.len(), astr.len() - 1).atoi() + + +// Declarations for internal signal probing +logic [31:0] fuse_uds_seed [0:11]; +logic [31:0] fuse_field_entropy [0:7]; +logic [31:0] fuse_key_manifest_pk_hash [0:11]; +logic [3:0] fuse_key_manifest_pk_hash_mask; +logic [31:0] fuse_owner_pk_hash [0:11]; +logic [31:0] fuse_fmc_key_manifest_svn; +logic [31:0] fuse_runtime_svn [0:3]; +logic fuse_anti_rollback_disable; +logic [31:0] fuse_idevid_cert_attr [0:23]; +logic [31:0] fuse_idevid_manuf_hsm_id [0:3]; +logic [1:0] fuse_life_cycle ; +logic fuse_lms_verify ; +logic [31:0] fuse_lms_revocation; + + +`FORLOOP_COMB( 12 ) fuse_uds_seed[j] = `REG_HIER_PFX.fuse_uds_seed[j].seed.value; +`FORLOOP_COMB( 8 ) fuse_field_entropy[j] = `REG_HIER_PFX.fuse_field_entropy[j].seed.value; +`FORLOOP_COMB( 12 ) fuse_key_manifest_pk_hash[j] = `REG_HIER_PFX.fuse_key_manifest_pk_hash[j].hash.value; + always_comb fuse_key_manifest_pk_hash_mask = `REG_HIER_PFX.fuse_key_manifest_pk_hash_mask.mask.value; +`FORLOOP_COMB( 12 ) fuse_owner_pk_hash[j] = `REG_HIER_PFX.fuse_owner_pk_hash[j].hash.value; + always_comb fuse_fmc_key_manifest_svn = `REG_HIER_PFX.fuse_fmc_key_manifest_svn.svn.value; +`FORLOOP_COMB( 4 ) fuse_runtime_svn[j] = `REG_HIER_PFX.fuse_runtime_svn[j].svn.value; + always_comb fuse_anti_rollback_disable = `REG_HIER_PFX.fuse_anti_rollback_disable.dis.value; +`FORLOOP_COMB( 24 ) fuse_idevid_cert_attr[j] = `REG_HIER_PFX.fuse_idevid_cert_attr[j].cert.value; +`FORLOOP_COMB( 4 ) fuse_idevid_manuf_hsm_id[j] = `REG_HIER_PFX.fuse_idevid_manuf_hsm_id[j].hsm_id.value; + always_comb fuse_life_cycle = `REG_HIER_PFX.fuse_life_cycle.life_cycle.value; + always_comb fuse_lms_verify = `REG_HIER_PFX.fuse_lms_verify.lms_verify.value; + always_comb fuse_lms_revocation = `REG_HIER_PFX.fuse_lms_revocation.lms_revocation.value; + + +//---------------------------------------------------------------- +// fuse_reg_pauser_test() +// +// Checks fuse permission tests depending on PAUSER bit status +//---------------------------------------------------------------- +task fuse_reg_pauser_test; + // Fuse Register PA-USER Test + + automatic word_addr_t addr; + automatic int tid = 0; // optional to increment UNLESS multiple writes to same address + automatic strq_t fuse_regnames; // ordered list of fuse register names + automatic dwordq_t fuse_regdata; // corresponding data to fuse register names + automatic dword_t valid_pauser; + automatic logic lock_status; + automatic WordTransaction wrtrans, rdtrans; + automatic string rname; + automatic dword_t fuse_regval_actual; + + begin + $display("Executing task fuse_reg_pauser_test"); + $display("-----------------------------------\n"); + + $display("Current security state = 0b%03b", security_state); + tc_ctr = tc_ctr + 1; + + wrtrans = new(); + rdtrans = new(); + + fuse_regnames = get_fuse_regnames(); + + init_sim(); + reset_dut(); + + //------------------------------------------------------------------------------------------- + print_banner("1a. Default pauser and unlocked. APB write to registers, check values"); + tphase = "1a"; + + write_regs(SET_APB, fuse_regnames, tid, 3); // effect changes & expec same values on read + repeat (5) @(posedge clk_tb); + read_regs(GET_APB, fuse_regnames, tid, 3); + + //------------------------------------------------------------------------------------------- + print_banner("1b. With unlocked non-default pauser, repeat 1a"); + tphase = "1b"; + + // Set pauser valid to non-default + wrtrans.update_byname("CPTRA_FUSE_VALID_PAUSER", 0, tid); + wrtrans.randomize(); + valid_pauser = wrtrans.data; + write_reg_trans(SET_APB, wrtrans); + repeat (3) @(posedge clk_tb); + rdtrans.update_byname("CPTRA_FUSE_VALID_PAUSER", 0, tid); + read_reg_trans(GET_APB, rdtrans); + $display ("Pauser value programmed = 0x%08x", rdtrans.data); + assert (rdtrans.data == valid_pauser) else begin + $display("TB ERROR. fuse_pauser_valid modfication failed"); + error_ctr += 1; + end + + write_regs(SET_APB, fuse_regnames, tid, 3); // effect changes + repeat (5) @(posedge clk_tb); + read_regs(GET_APB, fuse_regnames, tid, 3); + + //------------------------------------------------------------------------------------------- + print_banner("1c. Lock pauser with non-default value. repeat 1a but read with and w/o valid pauser"); + tphase = "1c"; + + set_fuse_pauser_lock(1'b1, tid, lock_status); + if (lock_status == 1'b0) begin + $display("TB ERROR. Setting fuse_pauser_lock failed!"); + error_ctr += 1; + end + + $display ("TB INFO. Storing last modified fuse register values with valid pauser writes"); + foreach (fuse_regnames[i]) begin // store last-modified values + rname = fuse_regnames[i]; + fuse_regval_actual = get_fuse_regval(rname); + fuse_regdata.push_back(fuse_regval_actual); + $display ("TB INFO. For %-30s storing last modified value 0x%08x", rname, fuse_regval_actual); + end + + write_regs(SET_APB, fuse_regnames, tid, 3); // should be ineffectual + repeat (5) @(posedge clk_tb); + + // Read twice, with and without valid pauser + foreach (fuse_regnames[i]) begin + rname = fuse_regnames[i]; + rdtrans.update_byname(rname, 0, tid); + fuse_regval_actual = get_fuse_regval(rname); + read_reg_chk_inrange(GET_APB, rname, tid, '0, '0); // get 0's on default pauser + repeat (3) @(posedge clk_tb); + read_reg_trans(GET_APB, rdtrans, valid_pauser); + repeat (3) @(posedge clk_tb); + + if (str_startswith(rname, "FUSE_UDS_SEED") || str_startswith(rname, "FUSE_FIELD_ENTROPY")) + assert (rdtrans.data == '0) else error_ctr += 1; + continue; + + if (rdtrans.data != fuse_regval_actual) begin + $display("TB ERROR. Mismatch on APB read w/valid pauser for reg %-30s (0x%08x). Read value = 0x%08x | expected probed = 0x%08x", + rname, rdtrans.addr, rdtrans.data, fuse_regval_actual) ; + error_ctr += 1; + end + @(posedge clk_tb); + end + + + //------------------------------------------------------------------------------------------- + print_banner("1d. With matching locked non-default pauser, repeat 1a"); + tphase = "1d"; + + sb.del_all(); // Fresh scoreboard start (except for errors) + + foreach (fuse_regnames[i]) begin + rname = fuse_regnames[i]; + wrtrans.update_byname(rname, 0, tid); + wrtrans.randomize(); + rdtrans.update_byname(rname, 0, tid); + + write_reg_trans(SET_APB, wrtrans, valid_pauser); + @(posedge clk_tb); + read_reg_trans(GET_APB, rdtrans, valid_pauser); + repeat (3) @(posedge clk_tb); + + if (str_startswith(rname, "FUSE_UDS_SEED") || str_startswith(rname, "FUSE_FIELD_ENTROPY")) + continue; + + if (rdtrans.data != (get_mask(rname) & wrtrans.data)) begin + $display("TB ERROR. Mismatch on APB write and read w/valid pauser for reg %-30s (0x%08x). Masked Write value = 0x%08x | expected Read value = 0x%08x", + rname, rdtrans.addr, get_mask(rname) & wrtrans.data, rdtrans.data); + error_ctr += 1; + end + + repeat (3) @(posedge clk_tb); + end + + + //------------------------------------------------------------------------------------------- + print_banner("2a. for completeness try to unlock pauser by writing"); + tphase = "2a"; + + set_fuse_pauser_lock(1'b0, tid, lock_status); + assert (lock_status == 1'b1) else begin + $display("TB ERROR. Resetting of fuse_pauser_lock via APB was allowed!"); + error_ctr += 1; + end + + + //------------------------------------------------------------------------------------------- + print_banner("2b. then attempt to unlock pauser by warm reseting"); + tphase = "2b"; + + warm_reset_dut(); + reset_exp_data(); + sb.del_all(); + + read_reg_chk_inrange(GET_APB, "CPTRA_FUSE_PAUSER_LOCK", tid, '0, '0); + @(posedge clk_tb); + + + //------------------------------------------------------------------------------------------- + print_banner("2c. finally unlock pauser by cold reseting"); + tphase = "2c"; + + reset_dut(); // expect to be clearing CPTRA_FUSE_WR_DONE effect + reset_exp_data(); + // simulate_caliptra_boot(); + sb.del_all(); + + read_reg_chk_inrange(GET_APB, "CPTRA_FUSE_PAUSER_LOCK", tid, '0, '0); + @(posedge clk_tb); + + + error_ctr += sb.err_count; + + end + +endtask // fuse_reg_pauser_test + + + +//---------------------------------------------------------------- +// function get_fuse_regval() +// +// Probes to get the intenral fuse register value inside dut +//---------------------------------------------------------------- +function dword_t get_fuse_regval(string rname); + + automatic dword_t regval; + string pfx = "unknown"; + automatic int j; + + strq_t prefixes = {"FUSE_UDS_SEED", "FUSE_FIELD_ENTROPY", "FUSE_KEY_MANIFEST_PK_HASH", + "FUSE_OWNER_PK_HASH", "FUSE_RUNTIME_SVN", "FUSE_IDEVID_CERT_ATTR", "FUSE_IDEVID_MANUF_HSM_ID"}; + + begin + case (rname) + "FUSE_KEY_MANIFEST_PK_HASH_MASK" : regval = fuse_key_manifest_pk_hash_mask; + "FUSE_FMC_KEY_MANIFEST_SVN" : regval = fuse_fmc_key_manifest_svn; + "FUSE_ANTI_ROLLBACK_DISABLE" : regval = fuse_anti_rollback_disable; + "FUSE_LIFE_CYCLE" : regval = fuse_life_cycle ; + "FUSE_LMS_VERIFY" : regval = fuse_lms_verify ; + "FUSE_LMS_REVOCATION" : regval = fuse_lms_revocation; + + default: begin + foreach (prefixes[i]) begin + if (str_startswith(rname, prefixes[i])) begin + pfx = prefixes[i]; + break; + end + end + + if (pfx == "unknown") begin + $display ("TB ERROR. Unknown prefix in fuse register name %s", rname); + error_ctr += 1; + end else begin + j = `STR_RMPFX(rname, pfx); + // $display ("prefix = %s, j = %d", pfx, j); + regval = (pfx == "FUSE_UDS_SEED" ) ? fuse_uds_seed[j]: + (pfx == "FUSE_FIELD_ENTROPY" ) ? fuse_field_entropy[j] : + (pfx == "FUSE_KEY_MANIFEST_PK_HASH") ? fuse_key_manifest_pk_hash[j] : + (pfx == "FUSE_OWNER_PK_HASH" ) ? fuse_owner_pk_hash[j] : + (pfx == "FUSE_RUNTIME_SVN" ) ? fuse_runtime_svn[j] : + (pfx == "FUSE_IDEVID_CERT_ATTR" ) ? fuse_idevid_cert_attr[j] : + (pfx == "FUSE_IDEVID_MANUF_HSM_ID" ) ? fuse_idevid_manuf_hsm_id[j] : 'x; + end + end + + endcase + + return regval; + end + +endfunction // get_fuse_regval + + +//---------------------------------------------------------------- +// task set_fuse_pauser_lock() +// +// Sets fuse pauser lock register & checks value +//---------------------------------------------------------------- +task set_fuse_pauser_lock(input logic lock_value, input int tid, output logic lock_status); + + automatic WordTransaction wrtrans, rdtrans; + begin + wrtrans = new(); + rdtrans = new(); + + wrtrans.update_byname("CPTRA_FUSE_PAUSER_LOCK", lock_value, tid); + write_reg_trans(SET_APB, wrtrans); + repeat (3) @(posedge clk_tb); + rdtrans.update_byname("CPTRA_FUSE_PAUSER_LOCK", 0, tid); + read_reg_trans(GET_APB, rdtrans); // FIXME. + $display ("Pauser lock status = 0x%08x", rdtrans.data); + + lock_status = rdtrans.data[0]; + end +endtask // set_fuse_pauser_lock + diff --git a/src/soc_ifc/tb/fuse_reg_perm_test.svh b/src/soc_ifc/tb/fuse_reg_perm_test.svh index 6a0728c43..fff476837 100644 --- a/src/soc_ifc/tb/fuse_reg_perm_test.svh +++ b/src/soc_ifc/tb/fuse_reg_perm_test.svh @@ -17,6 +17,8 @@ //---------------------------------------------------------------- // fuse_reg_perm_test() +// +// Checks fuse permission tests depending on lock status from FUSE_WR_DONE //---------------------------------------------------------------- task fuse_reg_perm_test; // Fuse Register Test diff --git a/src/soc_ifc/tb/sha_acc_intrblk_test.svh b/src/soc_ifc/tb/sha_acc_intrblk_test.svh index c8f3dbe30..cc6cfd4fb 100644 --- a/src/soc_ifc/tb/sha_acc_intrblk_test.svh +++ b/src/soc_ifc/tb/sha_acc_intrblk_test.svh @@ -29,7 +29,7 @@ automatic strq_t sha_acc_intrblk_regnames; automatic strq_t nonmatching_regnames; automatic dword_t rddata; - automatic dword_q nonmatching_rddata; + automatic dwordq_t nonmatching_rddata; automatic string rname; automatic dword_t ahb_wrdata, exp_regval; automatic dword_t apb_wrdata, apb_rddata; diff --git a/src/soc_ifc/tb/soc_ifc_tb.sv b/src/soc_ifc/tb/soc_ifc_tb.sv index e1c9595d8..99a6b1370 100644 --- a/src/soc_ifc/tb/soc_ifc_tb.sv +++ b/src/soc_ifc/tb/soc_ifc_tb.sv @@ -22,14 +22,6 @@ // Probably should be deprecated and utilize UVMF environment only //====================================================================== -/* -`define PRINT_TESTNAME(_SOC_IFC_TESTNAME) \ - string tmpstr = `"_SOC_IFC_TESTNAME`"; - $display(`"Executing test: _SOC_IFC_TESTNAME`"); - $display({{tmpstr.len(){`"-`"}}); -//---------------------------------------------------------------- -*/ - import "DPI-C" function string getenv(input string env_name); @@ -41,12 +33,14 @@ module soc_ifc_tb enum logic {DEBUG_UNLOCKED = 1'b0, DEBUG_LOCKED = 1'b1} debug_state_e; - // Strings for plusargs + // plusargs and other test related string soc_ifc_testname; string socreg_method_name = ""; string security_state_testname; int socreg_wrcount = 1; + string tphase; + //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- @@ -73,17 +67,20 @@ module soc_ifc_tb parameter MBOX_FE_ADDR = 32'h3003_0230; parameter MBOX_FUSE_DONE_ADDR = 32'h3003_00ac; - parameter AHB_ADDR_WIDTH = 18; - parameter AHB_DATA_WIDTH = 32; - parameter APB_ADDR_WIDTH = 18; - parameter APB_DATA_WIDTH = 32; - parameter APB_USER_WIDTH = 32; + parameter AHB_ADDR_WIDTH = 18; // `CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC); // 18 + parameter AHB_DATA_WIDTH = 32; // `CALIPTRA_AHB_HDATA_SIZE; // 32 + parameter APB_ADDR_WIDTH = 18; // `CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC); // 18 + parameter APB_DATA_WIDTH = 32; // `CALIPTRA_APB_DATA_WIDTH; // 32 + parameter APB_USER_WIDTH = 32; // `CALIPTRA_APB_USER_WIDTH; // 32 + parameter AHB_HTRANS_IDLE = 0; parameter AHB_HTRANS_BUSY = 1; parameter AHB_HTRANS_NONSEQ = 2; parameter AHB_HTRANS_SEQ = 3; + localparam PAUSER_DEFAULT = 32'hffff_ffff; + //---------------------------------------------------------------- // Register and Wire declarations. //---------------------------------------------------------------- @@ -166,36 +163,8 @@ module soc_ifc_tb - always @(posedge clk_tb or negedge cptra_pwrgood_tb) begin - if (!cptra_pwrgood_tb) - cycle_ctr_since_pwrgood <= '0; - else - cycle_ctr_since_pwrgood <= cycle_ctr_since_pwrgood + 1'b1; - end - - always @(posedge clk_tb or negedge cptra_rst_b_tb) begin - if (!cptra_rst_b_tb) - cycle_ctr_since_rst <= '0; - else - cycle_ctr_since_rst <= cycle_ctr_since_pwrgood + 1'b1; - end - - always @(posedge clk_tb or negedge cptra_rst_b_tb) begin - if (!cptra_rst_b_tb) begin - // gen_input_wire_toggle <= 1'b1; - generic_input_wires0_q <= 32'b0; - generic_input_wires0_q <= 32'b0; - end else begin - // gen_input_wire_toggle <= 1'b1; - generic_input_wires0_q <= generic_input_wires0; - generic_input_wires1_q <= generic_input_wires1; - end - end - - assign gen_input_wire_toggle = (generic_input_wires0 != generic_input_wires0_q) | - (generic_input_wires1 != generic_input_wires1_q); - - + + always_comb begin mbox_sram_cs = mbox_sram_req.cs; mbox_sram_we = mbox_sram_req.we; @@ -213,11 +182,11 @@ module soc_ifc_tb // Device Under Test. //---------------------------------------------------------------- soc_ifc_top #( - .AHB_DATA_WIDTH(32), - .AHB_ADDR_WIDTH(18), - .APB_USER_WIDTH(32), - .APB_ADDR_WIDTH(18), - .APB_DATA_WIDTH(32) + .AHB_DATA_WIDTH(AHB_DATA_WIDTH), // .AHB_DATA_WIDTH(32), + .AHB_ADDR_WIDTH(AHB_ADDR_WIDTH), // .AHB_ADDR_WIDTH(18), + .APB_USER_WIDTH(APB_USER_WIDTH), // .APB_USER_WIDTH(32), + .APB_ADDR_WIDTH(APB_ADDR_WIDTH), // .APB_ADDR_WIDTH(18), + .APB_DATA_WIDTH(APB_DATA_WIDTH) // .APB_DATA_WIDTH(32) ) dut ( .clk(clk_tb), @@ -372,11 +341,45 @@ module soc_ifc_tb //---------------------------------------------------------------- - // tick_timer + // tick_timer // - // Counts number of clock ticks since reset + // Counts number of clock ticks since power good and reset //---------------------------------------------------------------- - + always @(posedge clk_tb or negedge cptra_pwrgood_tb) begin : tick_timer_pwrgood + if (!cptra_pwrgood_tb) + cycle_ctr_since_pwrgood <= '0; + else + cycle_ctr_since_pwrgood <= cycle_ctr_since_pwrgood + 1'b1; + end + + always @(posedge clk_tb or negedge cptra_rst_b_tb) begin : tick_timer_outofrst + if (!cptra_rst_b_tb) + cycle_ctr_since_rst <= '0; + else + cycle_ctr_since_rst <= cycle_ctr_since_pwrgood + 1'b1; + end + + + //---------------------------------------------------------------- + // generic_input_detetor + // + // pulses high when generic input wires change + //---------------------------------------------------------------- + always @(posedge clk_tb or negedge cptra_rst_b_tb) begin : generic_input_detector + if (!cptra_rst_b_tb) begin + // gen_input_wire_toggle <= 1'b1; + generic_input_wires0_q <= 32'b0; + generic_input_wires0_q <= 32'b0; + end else begin + // gen_input_wire_toggle <= 1'b1; + generic_input_wires0_q <= generic_input_wires0; + generic_input_wires1_q <= generic_input_wires1; + end + end + + assign gen_input_wire_toggle = (generic_input_wires0 != generic_input_wires0_q) | + (generic_input_wires1 != generic_input_wires1_q); + //---------------------------------------------------------------- // pulse_trig_handler @@ -612,6 +615,33 @@ module soc_ifc_tb endtask // write_single_word_apb + //---------------------------------------------------------------- + // write_single_word_apb_wpauser() + // + // Write the given word to the DUT using the APB interface setting pauser. + //---------------------------------------------------------------- + task write_single_word_apb_wpauser(input [31 : 0] address, + input [31 : 0] word, + input [31 : 0] pauser); + begin + paddr_i_tb <= address; + psel_i_tb <= 1; + penable_i_tb <= 0; + pwrite_i_tb <= 1; + pwdata_i_tb <= word; + pauser_i_tb <= pauser; + wait(pready_o_tb == 1'b1); + + @(posedge clk_tb); + penable_i_tb <= 1; + wait(pready_o_tb == 1'b1); + + @(posedge clk_tb); + psel_i_tb <= 0; + penable_i_tb <= 0; + end + endtask // write_single_word_apb_wpauser + //---------------------------------------------------------------- // write_block_ahb() @@ -687,7 +717,34 @@ module soc_ifc_tb psel_i_tb <= 0; penable_i_tb <= 0; end - endtask // read_single_word_ahb + endtask // read_single_word_apb + + //---------------------------------------------------------------- + // read_single_word_apb_wpauser() + // + // Read the given word to the DUT using the APB interface setting pauser. + //---------------------------------------------------------------- + task read_single_word_apb_wpauser(input [31 : 0] address, + input [31 : 0] word, + input [31 : 0] pauser); + begin + paddr_i_tb <= address; + psel_i_tb <= 1; + penable_i_tb <= 0; + pwrite_i_tb <= 0; + pwdata_i_tb <= 0; + pauser_i_tb <= pauser; + wait(pready_o_tb == 1'b1); + + @(posedge clk_tb); + penable_i_tb <= 1; + wait(pready_o_tb == 1'b1); + + @(posedge clk_tb); + psel_i_tb <= 0; + penable_i_tb <= 0; + end + endtask // read_single_word_apb_wpauser //---------------------------------------------------------------- // read_result_ahb() @@ -780,9 +837,22 @@ module soc_ifc_tb set_initval("INTR_BRF_NOTIF_INTERNAL_INTR_R", intr_notif_val); update_exp_regval("INTR_BRF_NOTIF_INTERNAL_INTR_R", intr_notif_val, SET_DIRECT); end - endtask + endtask // set_security_state + //---------------------------------------------------------------- + // set_security_state_random() + // + // convenience function to set the security state to random + //---------------------------------------------------------------- + task set_security_state_random; + + automatic int ss_code = $urandom_range(0, 7); + ss_code = $urandom_range(0, 7); + set_security_state(security_state_t'(ss_code)); + + endtask // set_security_state_random + //---------------------------------------------------------------- // reset_generic_input_wires() @@ -1083,11 +1153,11 @@ module soc_ifc_tb if (modifier == GET_AHB) begin read_single_word_ahb(addr); - $display("Read over AHB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, hrdata_o_tb); + $display(" Read over AHB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, hrdata_o_tb); rdtrans.update(addr, hrdata_o_tb, tid); end else if (modifier == GET_APB) begin read_single_word_apb(addr); - $display("Read over APB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, prdata_o_tb); + $display(" Read over APB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, prdata_o_tb); rdtrans.update_byname(rname, prdata_o_tb, tid); end else $error("TB ERROR. Unsupported access modifier %s", modifier.name()); @@ -1099,13 +1169,13 @@ module soc_ifc_tb endtask // read_reg_chk_inrange - //---------------------------------------------------------------- + //---------------------------------------------------------------- // write_reg_trans() // // Utility for tracking/writing transaction to a register over APB/AHB // NOTE. Wait times must be added explcitly outside routine //---------------------------------------------------------------- - task write_reg_trans(input access_t modifier, WordTransaction wrtrans); + task write_reg_trans(access_t modifier, WordTransaction wrtrans, logic [31:0] pauser=PAUSER_DEFAULT); string rname; word_addr_t addr; @@ -1117,24 +1187,32 @@ module soc_ifc_tb write_single_word_ahb(addr, wrtrans.data); $display("Write over AHB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, wrtrans.data); end else if (modifier == SET_APB) begin - write_single_word_apb(addr, wrtrans.data); - $display("Write over APB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, wrtrans.data); + if (pauser != PAUSER_DEFAULT) begin + write_single_word_apb_wpauser(addr, wrtrans.data, pauser); + $display("Write over APB with non-default pauser: addr = %-40s (0x%08x), data = 0x%08x", + rname, addr, wrtrans.data); + end else begin + write_single_word_apb(addr, wrtrans.data); + $display("Write over APB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, wrtrans.data); + end end else $error("TB ERROR. Unsupported access modifier %s", modifier.name()); sb.record_entry(wrtrans, modifier); - end - endtask // write_reg_trans + end + endtask // write_reg_trans //---------------------------------------------------------------- // read_reg_trans() // // Utility for reading transaction to a register over APB/AHB - // NOTES. 1. No scoreboard tracking + // NOTES. 1. No scoreboard checking // 2. Wait times must be added explcitly outside routine //---------------------------------------------------------------- - task read_reg_trans(input access_t modifier, inout WordTransaction rdtrans); + task read_reg_trans(input access_t modifier, + inout WordTransaction rdtrans, + input logic [31:0] pauser=PAUSER_DEFAULT); string rname; word_addr_t addr; @@ -1145,11 +1223,18 @@ module soc_ifc_tb if (modifier == GET_AHB) begin read_single_word_ahb(addr); rdtrans.data = hrdata_o_tb; - $display("Read over AHB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, rdtrans.data); + $display(" Read over AHB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, rdtrans.data); end else if (modifier == GET_APB) begin - read_single_word_apb(addr); - rdtrans.data = prdata_o_tb; - $display("Read over APB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, rdtrans.data); + if (pauser != PAUSER_DEFAULT) begin + read_single_word_apb_wpauser(addr, rdtrans.data, pauser); + rdtrans.data = prdata_o_tb; + $display(" Read over APB with explicit pauser: addr = %-40s (0x%08x), data = 0x%08x", + rname, addr, rdtrans.data); + end else begin + read_single_word_apb(addr); + rdtrans.data = prdata_o_tb; + $display(" Read over APB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, rdtrans.data); + end end else $error("TB ERROR. Unsupported access modifier %s", modifier.name()); @@ -1158,7 +1243,6 @@ module soc_ifc_tb endtask // read_reg_trans - //---------------------------------------------------------------- // read_regs() // @@ -1189,11 +1273,11 @@ module soc_ifc_tb if (modifier == GET_AHB) begin read_single_word_ahb(addr); - $display("Read over AHB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, hrdata_o_tb); + $display(" Read over AHB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, hrdata_o_tb); rdtrans.update(addr, hrdata_o_tb, tid); end else if (modifier == GET_APB) begin read_single_word_apb(addr); - $display("Read over APB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, prdata_o_tb); + $display(" Read over APB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, prdata_o_tb); rdtrans.update(addr, prdata_o_tb, tid); end else $error("TB ERROR. Unsupported access modifier %s", modifier.name()); @@ -1272,11 +1356,11 @@ module soc_ifc_tb // read phase if (rd_modifier == GET_AHB) begin read_single_word_ahb(addr); - $display("Read over AHB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, hrdata_o_tb); + $display(" Read over AHB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, hrdata_o_tb); rdtrans.update(addr, hrdata_o_tb, tid); end else if (rd_modifier == GET_APB) begin read_single_word_apb(addr); - $display("Read over APB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, prdata_o_tb); + $display(" Read over APB: addr = %-40s (0x%08x), data = 0x%08x", rname, addr, prdata_o_tb); rdtrans.update(addr, prdata_o_tb, tid); end else $error("TB ERROR. Unsupported access rd_modifier %s", rd_modifier.name()); @@ -1302,6 +1386,7 @@ module soc_ifc_tb //---------------------------------------------------------------- `include "fuse_reg_lifecycle_test.svh" `include "fuse_reg_perm_test.svh" + `include "fuse_reg_pauser_test.svh" `include "fuse_reg_test.svh" `include "single_soc_reg_test.svh" `include "soc_reg_reset_test.svh" @@ -1361,7 +1446,7 @@ module soc_ifc_tb if ($value$plusargs("SECURITY_STATE=%s", security_state_testname)) fuse_reg_lifecycle_test(security_state_testname); else - fuse_reg_lifecycle_test("RANDOM"); // 'ALL' is the other option that isn't working fully + fuse_reg_lifecycle_test("RANDOM"); end else if (soc_ifc_testname == "soc_reg_test") begin set_security_state('{device_lifecycle: DEVICE_PRODUCTION, debug_locked: DEBUG_LOCKED}); @@ -1403,6 +1488,11 @@ module soc_ifc_tb sim_dut_init(); fuse_reg_perm_test(); + end else if (soc_ifc_testname == "fuse_reg_pauser_test") begin + set_security_state_random; + sim_dut_init(); + fuse_reg_pauser_test(); + end @(posedge clk_tb); diff --git a/src/soc_ifc/tb/soc_ifc_tb_pkg.sv b/src/soc_ifc/tb/soc_ifc_tb_pkg.sv index a3aa27a26..8e6d7fa99 100644 --- a/src/soc_ifc/tb/soc_ifc_tb_pkg.sv +++ b/src/soc_ifc/tb/soc_ifc_tb_pkg.sv @@ -56,7 +56,7 @@ package soc_ifc_tb_pkg; typedef transaction_t transq_t [$]; typedef string strq_t [$]; - typedef dword_t dword_q [$]; + typedef dword_t dwordq_t [$]; typedef enum { COLD_RESET, WARM_RESET, @@ -207,9 +207,10 @@ package soc_ifc_tb_pkg; "INTR_BRF_NOTIF_CMD_AVAIL_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_CMD_AVAIL_INTR_COUNT_R, // 0x980 "INTR_BRF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_MBOX_ECC_COR_INTR_COUNT_R, // 0x984 "INTR_BRF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_DEBUG_LOCKED_INTR_COUNT_R, // 0x988 - "INTR_BRF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R, // 0x98c - "INTR_BRF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R, // 0x990 - // 0x994..0x9fc + "INTR_BRF_NOTIF_SCAN_MODE_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R, // 0x98c + "INTR_BRF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_SOC_REQ_LOCK_INTR_COUNT_R, // 0x990 + "INTR_BRF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_GEN_IN_TOGGLE_INTR_COUNT_R, // 0x994 + // 0x998..0x9fc "INTR_BRF_ERROR_INTERNAL_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R, // 0xa00 "INTR_BRF_ERROR_INV_DEV_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INV_DEV_INTR_COUNT_INCR_R, // 0xa04 "INTR_BRF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R" : SOCIFC_BASE + `SOC_IFC_REG_INTR_BLOCK_RF_ERROR_CMD_FAIL_INTR_COUNT_INCR_R, // 0xa08 @@ -256,7 +257,7 @@ package soc_ifc_tb_pkg; '{addr_min: SOCIFC_BASE + 16'h0650, addr_max: SOCIFC_BASE + 16'h07fc}, '{addr_min: SOCIFC_BASE + 16'h0824, addr_max: SOCIFC_BASE + 16'h08fc}, '{addr_min: SOCIFC_BASE + 16'h0920, addr_max: SOCIFC_BASE + 16'h097c}, - '{addr_min: SOCIFC_BASE + 16'h0994, addr_max: SOCIFC_BASE + 16'h09fc} + '{addr_min: SOCIFC_BASE + 16'h0998, addr_max: SOCIFC_BASE + 16'h09fc} }; @@ -1064,6 +1065,15 @@ package soc_ifc_tb_pkg; endfunction // count_trailing_zeros + function automatic void print_banner(string txtstr, string s = "-"); + + int L = txtstr.len(); + $display({L{s}}); + $display(txtstr); + $display({L{s}}); + + endfunction // print_banner + // ================================================================================ // Class definitions // ================================================================================ diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain.svh index a9dada78b..eee2faf34 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/registers/soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain.svh @@ -55,7 +55,8 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain extends soc_ifc_reg_cbs_mbox_c `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called through map [%s] results in data entry push to mbox_data_q", map.get_name()), UVM_FULL) // A potential issue because uC should have set dlen prior to pushing data if (rm.mbox_data_q.size() >= dlen_cap_dw) begin - `uvm_warning("SOC_IFC_REG_CBS", "Push to datain observed when mbox_data_q already contains the same number of entries as indicated in mbox_dlen or the mailbox maximum capacity!") +// `uvm_warning("SOC_IFC_REG_CBS", "Push to datain observed when mbox_data_q already contains the same number of entries as indicated in mbox_dlen or the mailbox maximum capacity!") + `uvm_info("SOC_IFC_REG_CBS", $sformatf("Push to datain observed when mbox_data_q already contains the same number of entries [%d] as indicated in mbox_dlen [%d bytes] or the mailbox maximum capacity!", rm.mbox_data_q.size(), mbox_dlen_mirrored(rm)), UVM_LOW) end rm.mbox_data_q.push_back(value); if (rm.mbox_data_q.size() == 1) begin @@ -99,7 +100,7 @@ class soc_ifc_reg_cbs_mbox_csr_mbox_datain_datain extends soc_ifc_reg_cbs_mbox_c if (rm.mbox_fn_state_sigs.soc_data_stage) begin `uvm_info("SOC_IFC_REG_CBS", $sformatf("post_predict called through map [%s] results in data entry push to mbox_data_q", map.get_name()), UVM_FULL) if (rm.mbox_data_q.size() >= dlen_cap_dw) begin - `uvm_info("SOC_IFC_REG_CBS", "Push to datain observed when mbox_data_q already contains the same number of entries as indicated in mbox_dlen or the mailbox maximum capacity!", UVM_LOW) + `uvm_info("SOC_IFC_REG_CBS", $sformatf("Push to datain observed when mbox_data_q already contains the same number of entries [%d] as indicated in mbox_dlen [%d bytes] or the mailbox maximum capacity!", rm.mbox_data_q.size(), mbox_dlen_mirrored(rm)), UVM_LOW) end rm.mbox_data_q.push_back(value); if (rm.mbox_data_q.size() == 1) begin diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_dlen_underread_handler_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_dlen_underread_handler_sequence.svh index 0068d5cdd..2a12920a0 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_dlen_underread_handler_sequence.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/cptra/soc_ifc_env_cptra_mbox_dlen_underread_handler_sequence.svh @@ -43,15 +43,25 @@ endclass task soc_ifc_env_cptra_mbox_dlen_underread_handler_sequence::mbox_pop_dataout(); int ii; int unsigned underrun_bytes; + int unsigned bytes_to_read; uvm_reg_data_t data; // minimum 5 bytes so we can grab the resp dlen - if (!std::randomize(underrun_bytes) with {underrun_bytes < op.dlen - 4;}) + if (!std::randomize(underrun_bytes) with {if (op.dlen > 4) underrun_bytes < op.dlen - 4; + else underrun_bytes == 0;}) `uvm_error("CPTRA_MBOX_HANDLER", "Failed to randomize overrun bytes") else `uvm_info("CPTRA_MBOX_HANDLER", $sformatf("Randomized underrun bytes to %d", underrun_bytes), UVM_MEDIUM) - for (ii=0; ii < op.dlen-underrun_bytes; ii+=4) begin + bytes_to_read = op.dlen-underrun_bytes; + if (bytes_to_read > 32'h8000_0000) begin + `uvm_warning("MBOX_SEQ", $sformatf("Bytes to read is calculated as a huge number - was this intentional? bytes_to_read: %d (0x%x)", bytes_to_read, bytes_to_read)) + end + else begin + `uvm_info("MBOX_SEQ", $sformatf("Bytes to read is calculated as %d (0x%x)", bytes_to_read, bytes_to_read), UVM_HIGH) + end + + for (ii=0; ii < bytes_to_read; ii+=4) begin reg_model.mbox_csr_rm.mbox_dataout.read(reg_sts, data, UVM_FRONTDOOR, reg_model.soc_ifc_AHB_map, this); if (reg_sts != UVM_IS_OK) `uvm_error("MBOX_SEQ", "Register access failed (mbox_dataout)") diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh index 1bc60b158..0f8d79660 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_predictor.svh @@ -1295,6 +1295,7 @@ class soc_ifc_predictor #( "notif_cmd_avail_intr_count_r", "notif_mbox_ecc_cor_intr_count_r", "notif_debug_locked_intr_count_r", + "notif_scan_mode_intr_count_r", "notif_soc_req_lock_intr_count_r", "notif_gen_in_toggle_intr_count_r": begin if (ahb_txn.RnW == AHB_WRITE) begin @@ -1304,14 +1305,6 @@ class soc_ifc_predictor #( `uvm_info("PRED_AHB", {"Access to register ", axs_reg.get_name(), " will have no effect on system"}, UVM_HIGH) end end - "notif_scan_mode_intr_count_r": begin - if (ahb_txn.RnW == AHB_WRITE) begin - `uvm_info("PRED_AHB", {"Write to ", axs_reg.get_name(), " modifies interrupt statistics count"}, UVM_HIGH) - end - else begin - `uvm_info("PRED_AHB", {"Access to register ", axs_reg.get_name(), " will have no effect on system"}, UVM_HIGH) - end - end "error_internal_intr_count_incr_r", "error_inv_dev_intr_count_incr_r", "error_cmd_fail_intr_count_incr_r", @@ -1323,6 +1316,7 @@ class soc_ifc_predictor #( "notif_cmd_avail_intr_count_incr_r", "notif_mbox_ecc_cor_intr_count_incr_r", "notif_debug_locked_intr_count_incr_r", + "notif_scan_mode_intr_count_incr_r", "notif_soc_req_lock_intr_count_incr_r", "notif_gen_in_toggle_intr_count_incr_r": begin `uvm_info("PRED_AHB", {"Access to register ", axs_reg.get_name(), " will have no effect on system"}, UVM_HIGH) @@ -2002,18 +1996,28 @@ class soc_ifc_predictor #( "error_bad_fuse_intr_count_r", "error_iccm_blocked_intr_count_r", "error_mbox_ecc_unc_intr_count_r", + "error_wdt_timer1_timeout_intr_count_r", + "error_wdt_timer2_timeout_intr_count_r", "notif_cmd_avail_intr_count_r", "notif_mbox_ecc_cor_intr_count_r", "notif_debug_locked_intr_count_r", + "notif_scan_mode_intr_count_r", + "notif_soc_req_lock_intr_count_r", + "notif_gen_in_toggle_intr_count_r", "error_internal_intr_count_incr_r", "error_inv_dev_intr_count_incr_r", "error_cmd_fail_intr_count_incr_r", "error_bad_fuse_intr_count_incr_r", "error_iccm_blocked_intr_count_incr_r", "error_mbox_ecc_unc_intr_count_incr_r", + "error_wdt_timer1_timeout_intr_count_incr_r", + "error_wdt_timer2_timeout_intr_count_incr_r", "notif_cmd_avail_intr_count_incr_r", "notif_mbox_ecc_cor_intr_count_incr_r", "notif_debug_locked_intr_count_incr_r", + "notif_scan_mode_intr_count_incr_r", + "notif_soc_req_lock_intr_count_incr_r", + "notif_gen_in_toggle_intr_count_incr_r", "error0_intr_count_r", "error1_intr_count_r", "error2_intr_count_r", @@ -2122,7 +2126,7 @@ function void soc_ifc_predictor::send_delayed_expected_transactions(); // Force unlock will also reset mailbox_data_avail, if set, but // will not reset any pending interrupts to uC because those // are sticky - else if (mailbox_data_avail && (p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.mbox_idle || !p_soc_ifc_rm.mbox_csr_rm.mbox_execute.execute.get_mirrored_value())) begin + else if (mailbox_data_avail && !p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_receive_stage && !p_soc_ifc_rm.mbox_csr_rm.mbox_fn_state_sigs.soc_done_stage) begin `uvm_info("PRED_DLY", $sformatf("Resetting mailbox_data_avail"), UVM_HIGH) send_soc_ifc_sts_txn = 1'b1; mailbox_data_avail = 1'b0; diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_scoreboard.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_scoreboard.svh index bc8e9b383..ba58abb99 100644 --- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_scoreboard.svh +++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/src/soc_ifc_scoreboard.svh @@ -143,9 +143,10 @@ class soc_ifc_scoreboard #( bit [1:0] soc_ifc_status_monitor_toggle_count [$bits(soc_ifc_status_monitor_s)-1:0] = '{default: 0}; // Variables used to report transaction matches and mismatches - int match_count; // FIXME report this - int mismatch_count; // FIXME report this - int nothing_to_compare_against_count; // FIXME check this and report + int match_count = 0; + int mismatch_count = 0; + int nothing_to_compare_against_count = 0; + int multiple_missed_txn_count = 0; bit testcase_passed = 1'b0; // Variables used for report_phase summary output formatting using report_message() @@ -154,7 +155,7 @@ class soc_ifc_scoreboard #( // Variable used to enable end of test scoreboard empty check bit end_of_test_empty_check=1; // FIXME - int transaction_count; // FIXME check this + int transaction_count = 0; // Variable used to delay run phase completion until scoreboard empty bit wait_for_scoreboard_empty; // FIXME @@ -223,8 +224,10 @@ class soc_ifc_scoreboard #( soc_ifc_status_monitor_struct_rpt[sts_bit] = 1'b1; end end - if (multiple_missed_txn_error) + if (multiple_missed_txn_error) begin + multiple_missed_txn_count++; `uvm_error("SCBD_SOC_IFC_STS",$sformatf("Received multiple expected transactions without corresponding actual transaction. Problem fields: %p", soc_ifc_status_monitor_struct_rpt)) + end transaction_count++; -> entry_received; @@ -526,7 +529,7 @@ class soc_ifc_scoreboard #( virtual function void extract_phase(uvm_phase phase); // pragma uvmf custom extract_phase begin super.extract_phase(phase); - report_variables = {transaction_count, match_count, mismatch_count, nothing_to_compare_against_count}; + report_variables = {transaction_count, match_count, mismatch_count, nothing_to_compare_against_count, multiple_missed_txn_count}; // pragma uvmf custom extract_phase end endfunction @@ -535,7 +538,7 @@ class soc_ifc_scoreboard #( // pragma uvmf custom check_phase begin super.check_phase(phase); if (transaction_count == 0) `uvm_error("SCBD","No Transactions Scoreboarded") - if ((match_count > 0) && (mismatch_count == 0) && (nothing_to_compare_against_count == 0)) + if ((match_count > 0) && (mismatch_count == 0) && (nothing_to_compare_against_count == 0) && (multiple_missed_txn_count == 0)) testcase_passed = 1'b1; // pragma uvmf custom check_phase end endfunction @@ -544,7 +547,7 @@ class soc_ifc_scoreboard #( // Builds the report_phase message printed for scoreboards derived from this base // Provides for customization of output formatting virtual function string report_message(string header, int variables [] ); - return {$sformatf("%s PREDICTED_TRANSACTIONS=%0d MATCHES=%0d MISMATCHES=%0d NO_COMPARISON_TXN=%0d", header, variables[0], variables[1], variables[2], variables[3])}; + return {$sformatf("%s PREDICTED_TRANSACTIONS=%0d MATCHES=%0d MISMATCHES=%0d NO_COMPARISON_TXN=%0d MULTIPLE_MISSED_TXN=%0d", header, variables[0], variables[1], variables[2], variables[3], variables[4])}; endfunction // FUNCTION: report_phase