From 8d9c9297a665883d3da4a085bd1c5a48c63dcf16 Mon Sep 17 00:00:00 2001 From: Tanner Gooding Date: Tue, 1 Nov 2022 14:21:04 -0700 Subject: [PATCH] Assert GT_RSH for simd isn't TYP_LONG on xarch --- src/coreclr/jit/gentree.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp index 0e489ff23a5ee..5aba871c22a90 100644 --- a/src/coreclr/jit/gentree.cpp +++ b/src/coreclr/jit/gentree.cpp @@ -19334,9 +19334,6 @@ GenTree* Compiler::gtNewSimdBinOpNode(genTreeOps op, case GT_RSH: case GT_RSZ: { - assert(!varTypeIsByte(simdBaseType)); - assert((op != GT_RSH) || !varTypeIsUnsigned(simdBaseType)); - // float and double don't have actual instructions for shifting // so we'll just use the equivalent integer instruction instead. @@ -19351,6 +19348,9 @@ GenTree* Compiler::gtNewSimdBinOpNode(genTreeOps op, simdBaseType = TYP_LONG; } + assert(!varTypeIsByte(simdBaseType)); + assert((op != GT_RSH) || (!varTypeIsUnsigned(simdBaseType) && !varTypeIsLong(simdBaseType))); + // "over shifting" is platform specific behavior. We will match the C# behavior // this requires we mask with (sizeof(T) * 8) - 1 which ensures the shift cannot // exceed the number of bits available in `T`. This is roughly equivalent to