From 17d5c2a4d5aba39042f8c7f32b33143b62d054b4 Mon Sep 17 00:00:00 2001 From: Michael Schaffner Date: Tue, 30 Jan 2024 18:51:36 -0800 Subject: [PATCH] [otp_ctrl] Remove entropy_src chicken switches This carries over a change from integrated_dev that removes unnecessary chicken switches for the entropy complex. Note however that this time we do not remove EN_CSRNG_SW_APP_READ since that may still be useful. Signed-off-by: Michael Schaffner --- hw/dv/sv/mem_bkdr_util/mem_bkdr_util__otp.sv | 10 +- hw/ip/csrng/data/csrng.hjson | 1 + hw/ip/entropy_src/data/entropy_src.hjson | 2 + hw/ip/otp_ctrl/data/BUILD | 6 - .../data/earlgrey_a0_skus/prodc/BUILD | 6 - .../data/earlgrey_a0_skus/sival/BUILD | 6 - .../data/earlgrey_a0_skus/sival_bringup/BUILD | 6 - hw/ip/otp_ctrl/data/otp_ctrl.hjson | 26 --- hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl | 2 - .../otp_ctrl/data/otp_ctrl_img_hw_cfg0.hjson | 12 - hw/ip/otp_ctrl/data/otp_ctrl_mmap.hjson | 16 -- hw/ip/otp_ctrl/doc/otp_ctrl_mmap.md | 2 - hw/ip/otp_ctrl/doc/otp_ctrl_partitions.md | 4 - hw/ip/otp_ctrl/rtl/otp_ctrl_part_pkg.sv | 12 +- hw/ip/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv | 4 - .../data/autogen/top_earlgrey.gen.hjson | 38 +--- .../data/ip/chip_entropy_src_testplan.hjson | 26 --- hw/top_earlgrey/data/top_earlgrey.hjson | 2 - hw/top_earlgrey/dv/chip_sim_cfg.hjson | 7 - .../chip_sw_csrng_lc_hw_debug_en_vseq.sv | 4 +- .../seq_lib/chip_sw_entropy_src_fuse_vseq.sv | 8 +- .../chip_sw_flash_rma_unlocked_vseq.sv | 4 +- .../chip_sw_sram_ctrl_execution_main_vseq.sv | 7 +- hw/top_earlgrey/rtl/autogen/top_earlgrey.sv | 10 +- sw/device/lib/dif/dif_otp_ctrl.h | 4 - .../manuf/data/manuf_testplan.hjson | 2 - sw/device/tests/sim_dv/BUILD | 18 -- .../sim_dv/entropy_src_fuse_en_fw_read_test.c | 208 ------------------ sw/host/opentitanlib/src/dif/otp_ctrl.rs | 14 -- .../src/otp/testdata/otp_ctrl_mmap.hjson | 20 +- util/topgen/templates/toplevel.sv.tpl | 4 - 31 files changed, 26 insertions(+), 465 deletions(-) delete mode 100644 sw/device/tests/sim_dv/entropy_src_fuse_en_fw_read_test.c diff --git a/hw/dv/sv/mem_bkdr_util/mem_bkdr_util__otp.sv b/hw/dv/sv/mem_bkdr_util/mem_bkdr_util__otp.sv index e060cb688b9db..3e9b56a2566af 100644 --- a/hw/dv/sv/mem_bkdr_util/mem_bkdr_util__otp.sv +++ b/hw/dv/sv/mem_bkdr_util/mem_bkdr_util__otp.sv @@ -125,10 +125,8 @@ endfunction virtual function void otp_write_hw_cfg0_partition( bit [DeviceIdSize*8-1:0] device_id, bit [ManufStateSize*8-1:0] manuf_state, - bit [EnSramIfetchSize*8-1:0] en_sram_ifetch, bit [EnCsrngSwAppReadSize*8-1:0] en_csrng_sw_app_read, - bit [EnEntropySrcFwReadSize*8-1:0] en_entropy_src_fw_read, - bit [EnEntropySrcFwOverSize*8-1:0] en_entropy_src_fw_over); + bit [EnSramIfetchSize*8-1:0] en_sram_ifetch); bit [HwCfg0DigestSize*8-1:0] digest; bit [bus_params_pkg::BUS_DW-1:0] hw_cfg0_data[$]; @@ -139,11 +137,9 @@ virtual function void otp_write_hw_cfg0_partition( for (int i = 0; i < ManufStateSize; i += 4) begin write32(i + ManufStateOffset, manuf_state[i*8+:32]); end - write32(EnSramIfetchOffset, - {en_entropy_src_fw_over, en_entropy_src_fw_read, en_csrng_sw_app_read, en_sram_ifetch}); + write32(EnSramIfetchOffset, {en_csrng_sw_app_read, en_sram_ifetch}); - hw_cfg0_data = {<<32 {32'h0, en_entropy_src_fw_over, en_entropy_src_fw_read, - en_csrng_sw_app_read, en_sram_ifetch, manuf_state, device_id}}; + hw_cfg0_data = {<<32 {32'h0, en_csrng_sw_app_read, en_sram_ifetch, manuf_state, device_id}}; digest = cal_digest(HwCfg0Idx, hw_cfg0_data); write64(HwCfg0DigestOffset, digest); diff --git a/hw/ip/csrng/data/csrng.hjson b/hw/ip/csrng/data/csrng.hjson index 34b8f622b1676..ee23aca6c3bfe 100644 --- a/hw/ip/csrng/data/csrng.hjson +++ b/hw/ip/csrng/data/csrng.hjson @@ -103,6 +103,7 @@ name: "otp_en_csrng_sw_app_read" act: "rcv" package: "prim_mubi_pkg" + default: "prim_mubi_pkg::MuBi8True" } { struct: "lc_tx" type: "uni" diff --git a/hw/ip/entropy_src/data/entropy_src.hjson b/hw/ip/entropy_src/data/entropy_src.hjson index 41b9cbbb4b416..933c1d1ea203b 100644 --- a/hw/ip/entropy_src/data/entropy_src.hjson +++ b/hw/ip/entropy_src/data/entropy_src.hjson @@ -78,12 +78,14 @@ name: "otp_en_entropy_src_fw_read" act: "rcv" package: "prim_mubi_pkg" + default: "prim_mubi_pkg::MuBi8True" } { struct: "mubi8" type: "uni" name: "otp_en_entropy_src_fw_over" act: "rcv" package: "prim_mubi_pkg" + default: "prim_mubi_pkg::MuBi8True" } { struct: "logic" type: "uni" diff --git a/hw/ip/otp_ctrl/data/BUILD b/hw/ip/otp_ctrl/data/BUILD index b4f139349d377..610b46d32019f 100644 --- a/hw/ip/otp_ctrl/data/BUILD +++ b/hw/ip/otp_ctrl/data/BUILD @@ -252,12 +252,6 @@ otp_json( # Cryptolib and chip-level tests require access to the CSRNG # software interfaces. "EN_CSRNG_SW_APP_READ": True, - # Cryptolib and chip-level tests require access to the - # entropy_src FW data interface. - "EN_ENTROPY_SRC_FW_READ": True, - # Cryptolib and chip-level tests require access to the - # entropy_src FW override interface. - "EN_ENTROPY_SRC_FW_OVER": True, }, lock = True, ), diff --git a/hw/ip/otp_ctrl/data/earlgrey_a0_skus/prodc/BUILD b/hw/ip/otp_ctrl/data/earlgrey_a0_skus/prodc/BUILD index 46044f846bceb..3f591847a79aa 100644 --- a/hw/ip/otp_ctrl/data/earlgrey_a0_skus/prodc/BUILD +++ b/hw/ip/otp_ctrl/data/earlgrey_a0_skus/prodc/BUILD @@ -225,12 +225,6 @@ otp_json( # Cryptolib and chip-level tests require access to the CSRNG # software interfaces. "EN_CSRNG_SW_APP_READ": True, - # Cryptolib and chip-level tests require access to the - # entropy_src FW data interface. - "EN_ENTROPY_SRC_FW_READ": True, - # Cryptolib and chip-level tests require access to the - # entropy_src FW override interface. - "EN_ENTROPY_SRC_FW_OVER": True, }, lock = True, ), diff --git a/hw/ip/otp_ctrl/data/earlgrey_a0_skus/sival/BUILD b/hw/ip/otp_ctrl/data/earlgrey_a0_skus/sival/BUILD index 9ac39866a9807..97370deecb1bf 100644 --- a/hw/ip/otp_ctrl/data/earlgrey_a0_skus/sival/BUILD +++ b/hw/ip/otp_ctrl/data/earlgrey_a0_skus/sival/BUILD @@ -225,12 +225,6 @@ otp_json( # Cryptolib and chip-level tests require access to the CSRNG # software interfaces. "EN_CSRNG_SW_APP_READ": True, - # Cryptolib and chip-level tests require access to the - # entropy_src FW data interface. - "EN_ENTROPY_SRC_FW_READ": True, - # Cryptolib and chip-level tests require access to the - # entropy_src FW override interface. - "EN_ENTROPY_SRC_FW_OVER": True, }, lock = True, ), diff --git a/hw/ip/otp_ctrl/data/earlgrey_a0_skus/sival_bringup/BUILD b/hw/ip/otp_ctrl/data/earlgrey_a0_skus/sival_bringup/BUILD index 61b3251c87cb1..08a315e297ff7 100644 --- a/hw/ip/otp_ctrl/data/earlgrey_a0_skus/sival_bringup/BUILD +++ b/hw/ip/otp_ctrl/data/earlgrey_a0_skus/sival_bringup/BUILD @@ -225,12 +225,6 @@ otp_json( # Cryptolib and chip-level tests require access to the CSRNG # software interfaces. "EN_CSRNG_SW_APP_READ": True, - # Cryptolib and chip-level tests require access to the - # entropy_src FW data interface. - "EN_ENTROPY_SRC_FW_READ": True, - # Cryptolib and chip-level tests require access to the - # entropy_src FW override interface. - "EN_ENTROPY_SRC_FW_OVER": True, }, lock = True, ), diff --git a/hw/ip/otp_ctrl/data/otp_ctrl.hjson b/hw/ip/otp_ctrl/data/otp_ctrl.hjson index 3b402909cb81f..d5c9adf719d69 100644 --- a/hw/ip/otp_ctrl/data/otp_ctrl.hjson +++ b/hw/ip/otp_ctrl/data/otp_ctrl.hjson @@ -943,30 +943,6 @@ default: "1", local: "true" }, - { name: "EnEntropySrcFwReadOffset", - desc: "Offset of EN_ENTROPY_SRC_FW_READ", - type: "int", - default: "1730", - local: "true" - }, - { name: "EnEntropySrcFwReadSize", - desc: "Size of EN_ENTROPY_SRC_FW_READ", - type: "int", - default: "1", - local: "true" - }, - { name: "EnEntropySrcFwOverOffset", - desc: "Offset of EN_ENTROPY_SRC_FW_OVER", - type: "int", - default: "1731", - local: "true" - }, - { name: "EnEntropySrcFwOverSize", - desc: "Size of EN_ENTROPY_SRC_FW_OVER", - type: "int", - default: "1", - local: "true" - }, { name: "HwCfg0DigestOffset", desc: "Offset of HW_CFG0_DIGEST", type: "int", @@ -1562,8 +1538,6 @@ name: "OTP_CTRL.ENTROPY_READ" desc: '''Firmware can read entropy from ENTROPY_SRC block by configuring following field of HW_CFG* partition. - EN_CSRNG_SW_APP_READ - - EN_ENTROPY_SRC_FW_READ - - EN_ENTROPY_SRC_FW_OVER ''' } { diff --git a/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl b/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl index 989f4a6b80d62..a5903dc18315c 100644 --- a/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl +++ b/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl @@ -612,8 +612,6 @@ otp_size_as_uint32 = otp_size_as_bytes // 4 name: "OTP_CTRL.ENTROPY_READ" desc: '''Firmware can read entropy from ENTROPY_SRC block by configuring following field of HW_CFG* partition. - EN_CSRNG_SW_APP_READ - - EN_ENTROPY_SRC_FW_READ - - EN_ENTROPY_SRC_FW_OVER ''' } { diff --git a/hw/ip/otp_ctrl/data/otp_ctrl_img_hw_cfg0.hjson b/hw/ip/otp_ctrl/data/otp_ctrl_img_hw_cfg0.hjson index 609b9d1d981d2..e20f9a5efbf60 100644 --- a/hw/ip/otp_ctrl/data/otp_ctrl_img_hw_cfg0.hjson +++ b/hw/ip/otp_ctrl/data/otp_ctrl_img_hw_cfg0.hjson @@ -25,18 +25,6 @@ name: "EN_CSRNG_SW_APP_READ", value: true, }, - { - // Cryptolib and chip-level tests require access to the - // entropy_src FW data interface. - name: "EN_ENTROPY_SRC_FW_READ", - value: true, - }, - { - // Cryptolib and chip-level tests require access to the - // entropy_src FW override interface. - name: "EN_ENTROPY_SRC_FW_OVER", - value: true, - } ], } ] diff --git a/hw/ip/otp_ctrl/data/otp_ctrl_mmap.hjson b/hw/ip/otp_ctrl/data/otp_ctrl_mmap.hjson index 856f6c6ff0d06..7a4a80ffdb67f 100644 --- a/hw/ip/otp_ctrl/data/otp_ctrl_mmap.hjson +++ b/hw/ip/otp_ctrl/data/otp_ctrl_mmap.hjson @@ -381,18 +381,6 @@ ismubi: true, inv_default: false }, - { - name: "EN_ENTROPY_SRC_FW_READ", - size: "1", - ismubi: true, - inv_default: false - }, - { - name: "EN_ENTROPY_SRC_FW_OVER", - size: "1", - ismubi: true, - inv_default: false - }, ], desc: '''Hardware configuration 0 partition. This contains @@ -401,10 +389,6 @@ - EN_SRAM_IFETCH: Enable / disable execute from SRAM CSR switch. - EN_CSRNG_SW_APP_READ: This input efuse is used to enable access to the NIST internal state per instance. - - EN_ENTROPY_SRC_FW_READ: This input efuse is used to enable access - to the ENTROPY_DATA register directly. - - EN_ENTROPY_SRC_FW_OVER: This input efuse is used to enable access - to the firmware override FIFO and other related functions. ''' } { diff --git a/hw/ip/otp_ctrl/doc/otp_ctrl_mmap.md b/hw/ip/otp_ctrl/doc/otp_ctrl_mmap.md index 53f39bdd51f0f..dc043a8e4155c 100644 --- a/hw/ip/otp_ctrl/doc/otp_ctrl_mmap.md +++ b/hw/ip/otp_ctrl/doc/otp_ctrl_mmap.md @@ -64,8 +64,6 @@ It has been generated with ./util/design/gen-otp-mmap.py | | | | 32bit | MANUF_STATE | 0x6A0 | 32 | | | | | 32bit | EN_SRAM_IFETCH | 0x6C0 | 1 | | | | | 32bit | EN_CSRNG_SW_APP_READ | 0x6C1 | 1 | -| | | | 32bit | EN_ENTROPY_SRC_FW_READ | 0x6C2 | 1 | -| | | | 32bit | EN_ENTROPY_SRC_FW_OVER | 0x6C3 | 1 | | | | | 64bit | [HW_CFG0_DIGEST](#Reg_hw_cfg0_digest_0) | 0x6C8 | 8 | | 4 | SECRET0 | 40 | 64bit | TEST_UNLOCK_TOKEN | 0x6D0 | 16 | | | | | 64bit | TEST_EXIT_TOKEN | 0x6E0 | 16 | diff --git a/hw/ip/otp_ctrl/doc/otp_ctrl_partitions.md b/hw/ip/otp_ctrl/doc/otp_ctrl_partitions.md index 485a8a52dfb86..859b173816e49 100644 --- a/hw/ip/otp_ctrl/doc/otp_ctrl_partitions.md +++ b/hw/ip/otp_ctrl/doc/otp_ctrl_partitions.md @@ -25,10 +25,6 @@ It has been generated with ./util/design/gen-otp-mmap.py | | | | | | | - EN_SRAM_IFETCH: Enable / disable execute from SRAM CSR switch. | | | | | | | | - EN_CSRNG_SW_APP_READ: This input efuse is used to enable access | | | | | | | | to the NIST internal state per instance. | -| | | | | | | - EN_ENTROPY_SRC_FW_READ: This input efuse is used to enable access | -| | | | | | | to the ENTROPY_DATA register directly. | -| | | | | | | - EN_ENTROPY_SRC_FW_OVER: This input efuse is used to enable access | -| | | | | | | to the firmware override FIFO and other related functions. | | SECRET0 | yes | yes | yes | yes (Digest) | yes (Digest) | Secret partition 0. | | | | | | | | This contains TEST lifecycle unlock tokens. | | SECRET1 | yes | yes | yes | yes (Digest) | yes (Digest) | Secret partition 1. | diff --git a/hw/ip/otp_ctrl/rtl/otp_ctrl_part_pkg.sv b/hw/ip/otp_ctrl/rtl/otp_ctrl_part_pkg.sv index 21d898e188c89..bc33ccc54e8fd 100644 --- a/hw/ip/otp_ctrl/rtl/otp_ctrl_part_pkg.sv +++ b/hw/ip/otp_ctrl/rtl/otp_ctrl_part_pkg.sv @@ -256,9 +256,7 @@ package otp_ctrl_part_pkg; // Breakout types for easier access of individual items. typedef struct packed { logic [63:0] hw_cfg0_digest; - logic [31:0] unallocated; - prim_mubi_pkg::mubi8_t en_entropy_src_fw_over; - prim_mubi_pkg::mubi8_t en_entropy_src_fw_read; + logic [47:0] unallocated; prim_mubi_pkg::mubi8_t en_csrng_sw_app_read; prim_mubi_pkg::mubi8_t en_sram_ifetch; logic [255:0] manuf_state; @@ -268,9 +266,7 @@ package otp_ctrl_part_pkg; // default value used for intermodule parameter otp_hw_cfg0_data_t OTP_HW_CFG0_DATA_DEFAULT = '{ hw_cfg0_digest: 64'h15F164D7930C9D19, - unallocated: 32'h0, - en_entropy_src_fw_over: prim_mubi_pkg::mubi8_t'(8'h69), - en_entropy_src_fw_read: prim_mubi_pkg::mubi8_t'(8'h69), + unallocated: 48'h0, en_csrng_sw_app_read: prim_mubi_pkg::mubi8_t'(8'h69), en_sram_ifetch: prim_mubi_pkg::mubi8_t'(8'h69), manuf_state: 256'hDF3888886BD10DC67ABB319BDA0529AE40119A3C6E63CDF358840E458E4029A6, @@ -314,9 +310,7 @@ package otp_ctrl_part_pkg; }), 640'({ 64'h15F164D7930C9D19, - 32'h0, // unallocated space - 8'h69, - 8'h69, + 48'h0, // unallocated space 8'h69, 8'h69, 256'hDF3888886BD10DC67ABB319BDA0529AE40119A3C6E63CDF358840E458E4029A6, diff --git a/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv b/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv index 73ddbcbf15b79..c27cab29d5323 100644 --- a/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv +++ b/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv @@ -142,10 +142,6 @@ package otp_ctrl_reg_pkg; parameter int EnSramIfetchSize = 1; parameter int EnCsrngSwAppReadOffset = 1729; parameter int EnCsrngSwAppReadSize = 1; - parameter int EnEntropySrcFwReadOffset = 1730; - parameter int EnEntropySrcFwReadSize = 1; - parameter int EnEntropySrcFwOverOffset = 1731; - parameter int EnEntropySrcFwOverSize = 1; parameter int HwCfg0DigestOffset = 1736; parameter int HwCfg0DigestSize = 8; parameter int Secret0Offset = 1744; diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 4c2d508263375..2e0ece6f86ae8 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -6651,8 +6651,8 @@ type: uni act: rcv width: 1 + default: prim_mubi_pkg::MuBi8True inst_name: csrng - default: "" top_signame: csrng_otp_en_csrng_sw_app_read index: -1 } @@ -6800,9 +6800,8 @@ type: uni act: rcv width: 1 + default: prim_mubi_pkg::MuBi8True inst_name: entropy_src - default: "" - top_signame: entropy_src_otp_en_entropy_src_fw_read index: -1 } { @@ -6812,9 +6811,8 @@ type: uni act: rcv width: 1 + default: prim_mubi_pkg::MuBi8True inst_name: entropy_src - default: "" - top_signame: entropy_src_otp_en_entropy_src_fw_over index: -1 } { @@ -8650,8 +8648,6 @@ pinmux_aon.dft_jtag otp_ctrl.otp_broadcast csrng.otp_en_csrng_sw_app_read - entropy_src.otp_en_entropy_src_fw_read - entropy_src.otp_en_entropy_src_fw_over lc_ctrl.otp_device_id lc_ctrl.otp_manuf_state keymgr.otp_device_id @@ -18975,8 +18971,8 @@ type: uni act: rcv width: 1 + default: prim_mubi_pkg::MuBi8True inst_name: csrng - default: "" top_signame: csrng_otp_en_csrng_sw_app_read index: -1 } @@ -19071,9 +19067,8 @@ type: uni act: rcv width: 1 + default: prim_mubi_pkg::MuBi8True inst_name: entropy_src - default: "" - top_signame: entropy_src_otp_en_entropy_src_fw_read index: -1 } { @@ -19083,9 +19078,8 @@ type: uni act: rcv width: 1 + default: prim_mubi_pkg::MuBi8True inst_name: entropy_src - default: "" - top_signame: entropy_src_otp_en_entropy_src_fw_over index: -1 } { @@ -23378,25 +23372,7 @@ width: 1 type: uni end_idx: -1 - default: "" - } - { - package: prim_mubi_pkg - struct: mubi8 - signame: entropy_src_otp_en_entropy_src_fw_read - width: 1 - type: uni - end_idx: -1 - default: "" - } - { - package: prim_mubi_pkg - struct: mubi8 - signame: entropy_src_otp_en_entropy_src_fw_over - width: 1 - type: uni - end_idx: -1 - default: "" + default: prim_mubi_pkg::MuBi8True } { package: otp_ctrl_pkg diff --git a/hw/top_earlgrey/data/ip/chip_entropy_src_testplan.hjson b/hw/top_earlgrey/data/ip/chip_entropy_src_testplan.hjson index d3398bf944852..ef2eb6f4dbbd2 100644 --- a/hw/top_earlgrey/data/ip/chip_entropy_src_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_entropy_src_testplan.hjson @@ -51,32 +51,6 @@ tests: ["chip_sw_entropy_src_csrng"] bazel: [] }, - { - name: chip_sw_entropy_src_fuse_en_fw_read - desc: '''Verify the fuse input entropy_src. - - - Initialize the OTP with the fuse that controls whether the SW can read the entropy src - enabled. - - Read the OTP and verify that the fuse is enabled. - - Read the entropy_data_fifo via SW and verify that it reads valid values. - - Reset the chip, but this time, initialize the OTP with the fuse disabled. - - Read the OTP and verify that fuse is disabled. - - Read the internal state via SW and verify that the entropy valid bit is zero. - - Notes for silicon targets: - - The current understanding is that the en_entropy_src_fw_read OTP switch controlling the ENTROPY_SRC.ROUTE_TO_FIRMWARE feature will need to be enabled also in the PROD life-cycle state for validation and known-answer testing. - Thus, burning the en_entropy_src_fw_read OTP fuses is not advisable for silicon validation. - This particular test may be skipped in favor of chip_sw_entropy_src_known_answer_tests which also tests the ENTROPY_SRC.ROUTE_TO_FIRMWARE feature. - ''' - features: [ - "ENTROPY_SRC.ROUTE_TO_FIRMWARE", - ] - stage: V2 - si_stage: None - lc_states: ["TEST_UNLOCKED", "PROD"] - tests: ["chip_sw_entropy_src_fuse_en_fw_read_test"] - bazel: [] - }, { name: chip_sw_entropy_src_known_answer_tests desc: '''Verify our ability to run known-answer tests in SW. diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index 0634448ff8ba8..bf6f6d8a0e62c 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson @@ -1087,8 +1087,6 @@ // be performed by hand in the toplevel template. 'otp_ctrl.otp_broadcast', 'csrng.otp_en_csrng_sw_app_read', - 'entropy_src.otp_en_entropy_src_fw_read', - 'entropy_src.otp_en_entropy_src_fw_over', 'lc_ctrl.otp_device_id', 'lc_ctrl.otp_manuf_state', 'keymgr.otp_device_id', diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson index b2cf8ca0fa574..90efd0aa995ff 100644 --- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson +++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson @@ -1331,13 +1331,6 @@ en_run_modes: ["sw_test_mode_test_rom"] run_opts: ["+sw_test_timeout_ns=15_000_000"] } - { - name: chip_sw_entropy_src_fuse_en_fw_read_test - uvm_test_seq: chip_sw_entropy_src_fuse_vseq - sw_images: ["//sw/device/tests/sim_dv:entropy_src_fuse_en_fw_read_test:1:new_rules"] - en_run_modes: ["sw_test_mode_test_rom"] - run_opts: ["+sw_test_timeout_ns=18000000"] - } { name: chip_sw_entropy_src_kat_test uvm_test_seq: chip_sw_base_vseq diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_csrng_lc_hw_debug_en_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_csrng_lc_hw_debug_en_vseq.sv index e0e935fec2c21..12468377c360b 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_csrng_lc_hw_debug_en_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_csrng_lc_hw_debug_en_vseq.sv @@ -46,9 +46,7 @@ class chip_sw_csrng_lc_hw_debug_en_vseq extends chip_sw_base_vseq; // lc states across resets. cfg.mem_bkdr_util_h[Otp].otp_write_hw_cfg0_partition( .device_id(DEVICE_ID), .manuf_state(MANUF_STATE), - .en_sram_ifetch(MUBI8FALSE), .en_csrng_sw_app_read(MUBI8TRUE), - .en_entropy_src_fw_read(MUBI8TRUE), - .en_entropy_src_fw_over(MUBI8TRUE)); + .en_sram_ifetch(MUBI8FALSE), .en_csrng_sw_app_read(MUBI8TRUE)); endtask virtual task body(); diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_entropy_src_fuse_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_entropy_src_fuse_vseq.sv index 443c98bec443a..1ebf9de4e051f 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_entropy_src_fuse_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_entropy_src_fuse_vseq.sv @@ -22,9 +22,7 @@ class chip_sw_entropy_src_fuse_vseq extends chip_sw_base_vseq; cfg.mem_bkdr_util_h[Otp].otp_write_hw_cfg0_partition( .device_id(DEVICE_ID), .manuf_state(MANUF_STATE), - .en_sram_ifetch(MUBI8FALSE), .en_csrng_sw_app_read(MUBI8TRUE), - .en_entropy_src_fw_read(MUBI8TRUE), - .en_entropy_src_fw_over(MUBI8TRUE)); + .en_sram_ifetch(MUBI8FALSE), .en_csrng_sw_app_read(MUBI8TRUE)); endtask virtual task body(); @@ -38,9 +36,7 @@ class chip_sw_entropy_src_fuse_vseq extends chip_sw_base_vseq; if (cfg.sw_logger_vif.printed_log == "Software resetting!") begin cfg.mem_bkdr_util_h[Otp].otp_write_hw_cfg0_partition( .device_id(DEVICE_ID), .manuf_state(MANUF_STATE), - .en_sram_ifetch(MUBI8FALSE), .en_csrng_sw_app_read(MUBI8FALSE), - .en_entropy_src_fw_read(MUBI8FALSE), - .en_entropy_src_fw_over(MUBI8TRUE)); + .en_sram_ifetch(MUBI8FALSE), .en_csrng_sw_app_read(MUBI8FALSE)); break; end end diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_rma_unlocked_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_rma_unlocked_vseq.sv index c58ff9b451299..c585209346eb5 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_rma_unlocked_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_flash_rma_unlocked_vseq.sv @@ -72,9 +72,7 @@ class chip_sw_flash_rma_unlocked_vseq extends chip_sw_base_vseq; .manuf_state(manuf_state), // Use same default config as in otp_ctrl_img_hw_cfg.hjson .en_sram_ifetch(prim_mubi_pkg::MuBi8False), - .en_csrng_sw_app_read(prim_mubi_pkg::MuBi8True), - .en_entropy_src_fw_read(prim_mubi_pkg::MuBi8True), - .en_entropy_src_fw_over(prim_mubi_pkg::MuBi8True)); + .en_csrng_sw_app_read(prim_mubi_pkg::MuBi8True)); // Read current chip revision and generation parameter values. retval = uvm_hdl_read(SILICON_CREATOR_ID_PATH, silicon_creator_id); diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_sram_ctrl_execution_main_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_sram_ctrl_execution_main_vseq.sv index f77beaf8f6b64..9110cc9211168 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_sram_ctrl_execution_main_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_sram_ctrl_execution_main_vseq.sv @@ -14,9 +14,6 @@ class chip_sw_sram_ctrl_execution_main_vseq extends chip_sw_base_vseq; localparam logic [7:0] MUBI8TRUE = prim_mubi_pkg::MuBi8True; localparam logic [7:0] MUBI8FALSE = prim_mubi_pkg::MuBi8False; localparam logic [7:0] EN_CSRNG_SW_APP_READ = MUBI8FALSE; - localparam logic [7:0] EN_ENTROPY_SRC_FW_READ = MUBI8FALSE; - localparam logic [7:0] EN_ENTROPY_SRC_FW_OVER = MUBI8FALSE; - virtual task do_test(logic [7:0] en_sram_ifetch, bit set_prod_lc); @@ -27,9 +24,7 @@ class chip_sw_sram_ctrl_execution_main_vseq extends chip_sw_base_vseq; end cfg.mem_bkdr_util_h[Otp].otp_write_hw_cfg0_partition( .device_id(DEVICE_ID), .manuf_state(MANUF_STATE), .en_sram_ifetch(en_sram_ifetch), - .en_csrng_sw_app_read(EN_CSRNG_SW_APP_READ), - .en_entropy_src_fw_read(EN_ENTROPY_SRC_FW_READ), - .en_entropy_src_fw_over(EN_ENTROPY_SRC_FW_OVER)); + .en_csrng_sw_app_read(EN_CSRNG_SW_APP_READ)); `DV_WAIT(cfg.sw_test_status_vif.sw_test_status == SwTestStatusInTest) `DV_WAIT(cfg.sw_test_status_vif.sw_test_status == SwTestStatusInWfi) diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index f11afb4cb96cf..68da72a49eba4 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -736,8 +736,6 @@ module top_earlgrey #( jtag_pkg::jtag_rsp_t pinmux_aon_dft_jtag_rsp; otp_ctrl_part_pkg::otp_broadcast_t otp_ctrl_otp_broadcast; prim_mubi_pkg::mubi8_t csrng_otp_en_csrng_sw_app_read; - prim_mubi_pkg::mubi8_t entropy_src_otp_en_entropy_src_fw_read; - prim_mubi_pkg::mubi8_t entropy_src_otp_en_entropy_src_fw_over; otp_ctrl_pkg::otp_device_id_t lc_ctrl_otp_device_id; otp_ctrl_pkg::otp_manuf_state_t lc_ctrl_otp_manuf_state; otp_ctrl_pkg::otp_device_id_t keymgr_otp_device_id; @@ -787,10 +785,6 @@ module top_earlgrey #( // be performed by hand. assign csrng_otp_en_csrng_sw_app_read = otp_ctrl_otp_broadcast.hw_cfg0_data.en_csrng_sw_app_read; - assign entropy_src_otp_en_entropy_src_fw_read = - otp_ctrl_otp_broadcast.hw_cfg0_data.en_entropy_src_fw_read; - assign entropy_src_otp_en_entropy_src_fw_over = - otp_ctrl_otp_broadcast.hw_cfg0_data.en_entropy_src_fw_over; assign sram_ctrl_main_otp_en_sram_ifetch = otp_ctrl_otp_broadcast.hw_cfg0_data.en_sram_ifetch; assign lc_ctrl_otp_device_id = @@ -2434,8 +2428,8 @@ module top_earlgrey #( .entropy_src_rng_i(es_rng_rsp_i), .entropy_src_xht_o(), .entropy_src_xht_i(entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT), - .otp_en_entropy_src_fw_read_i(entropy_src_otp_en_entropy_src_fw_read), - .otp_en_entropy_src_fw_over_i(entropy_src_otp_en_entropy_src_fw_over), + .otp_en_entropy_src_fw_read_i(prim_mubi_pkg::MuBi8True), + .otp_en_entropy_src_fw_over_i(prim_mubi_pkg::MuBi8True), .rng_fips_o(es_rng_fips_o), .tl_i(entropy_src_tl_req), .tl_o(entropy_src_tl_rsp), diff --git a/sw/device/lib/dif/dif_otp_ctrl.h b/sw/device/lib/dif/dif_otp_ctrl.h index 703cdf8dddfdc..a1a71ba5c3f55 100644 --- a/sw/device/lib/dif/dif_otp_ctrl.h +++ b/sw/device/lib/dif/dif_otp_ctrl.h @@ -64,10 +64,6 @@ typedef enum dif_otp_ctrl_partition { * - EN_SRAM_IFETCH: Enable / disable execute from SRAM CSR switch. * - EN_CSRNG_SW_APP_READ: This input efuse is used to enable access * to the NIST internal state per instance. - * - EN_ENTROPY_SRC_FW_READ: This input efuse is used to enable access - * to the ENTROPY_DATA register directly. - * - EN_ENTROPY_SRC_FW_OVER: This input efuse is used to enable access - * to the firmware override FIFO and other related functions. */ kDifOtpCtrlPartitionHwCfg0, /** diff --git a/sw/device/silicon_creator/manuf/data/manuf_testplan.hjson b/sw/device/silicon_creator/manuf/data/manuf_testplan.hjson index 47bef4eb5ac6b..e1a8d3fef36e1 100644 --- a/sw/device/silicon_creator/manuf/data/manuf_testplan.hjson +++ b/sw/device/silicon_creator/manuf/data/manuf_testplan.hjson @@ -271,8 +271,6 @@ - Check device lc_state. Return error to the host if device in invalid state. - Configure the following OTP fuses to enable access to entropy: - EN_CSRNG_SW_APP_READ - - EN_ENTROPY_SRC_FW_READ - - EN_ENTROPY_SRC_FW_OVER - Configure remaining HW_CFG0 OTP fields: - DEVICE_ID - MANUF_STATE diff --git a/sw/device/tests/sim_dv/BUILD b/sw/device/tests/sim_dv/BUILD index d635e3449eafd..bc1c451d0cfc2 100644 --- a/sw/device/tests/sim_dv/BUILD +++ b/sw/device/tests/sim_dv/BUILD @@ -950,24 +950,6 @@ opentitan_test( ], ) -opentitan_test( - name = "entropy_src_fuse_en_fw_read_test", - srcs = ["entropy_src_fuse_en_fw_read_test.c"], - exec_env = {"//hw/top_earlgrey:sim_dv": None}, - deps = [ - "//hw/top_earlgrey/sw/autogen:top_earlgrey", - "//sw/device/lib/base:memory", - "//sw/device/lib/base:mmio", - "//sw/device/lib/dif:base", - "//sw/device/lib/dif:entropy_src", - "//sw/device/lib/dif:rstmgr", - "//sw/device/lib/runtime:log", - "//sw/device/lib/testing:otp_ctrl_testutils", - "//sw/device/lib/testing:rstmgr_testutils", - "//sw/device/lib/testing/test_framework:ottf_main", - ], -) - opentitan_test( name = "ast_usb_clk_calib", srcs = ["ast_usb_clk_calib.c"], diff --git a/sw/device/tests/sim_dv/entropy_src_fuse_en_fw_read_test.c b/sw/device/tests/sim_dv/entropy_src_fuse_en_fw_read_test.c deleted file mode 100644 index 3fad542269b5f..0000000000000 --- a/sw/device/tests/sim_dv/entropy_src_fuse_en_fw_read_test.c +++ /dev/null @@ -1,208 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#include "sw/device/lib/base/memory.h" -#include "sw/device/lib/base/mmio.h" -#include "sw/device/lib/dif/dif_base.h" -#include "sw/device/lib/dif/dif_entropy_src.h" -#include "sw/device/lib/dif/dif_rstmgr.h" -#include "sw/device/lib/runtime/log.h" -#include "sw/device/lib/testing/otp_ctrl_testutils.h" -#include "sw/device/lib/testing/rstmgr_testutils.h" -#include "sw/device/lib/testing/test_framework/check.h" -#include "sw/device/lib/testing/test_framework/ottf_main.h" - -#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" // Generated. -#include "otp_ctrl_regs.h" // Generated - -OTTF_DEFINE_TEST_CONFIG(); - -/** - * OTP HW partition relative IFETCH offset in bytes. - * - * x = OTP_CTRL_PARAM_EN_SRAM_IFETCH_OFFSET (1728) - * y = OTP_CTRL_PARAM_HW_CFG0_OFFSET (1664) - * IFETCH_OFFSET = (x - y) = 64 - */ -static const uint32_t kOtpIfetchHwRelativeOffset = - OTP_CTRL_PARAM_EN_SRAM_IFETCH_OFFSET - OTP_CTRL_PARAM_HW_CFG0_OFFSET; - -static const uint32_t kOtpEntropySrcFwReadOffset = - (OTP_CTRL_PARAM_EN_ENTROPY_SRC_FW_READ_OFFSET - - OTP_CTRL_PARAM_EN_SRAM_IFETCH_OFFSET) * - 8; - -enum { - /** - * The size of the buffer used in firmware to process the entropy bits in - * firmware override mode. - */ - kEntropyFifoBufferSize = 12, -}; - -/** - * Configures the entropy source module in firmware override mode. - * - * Output is routed to firmware, and the fw_override mode is enabled to get data - * post-health tests and before the pre conditioner block. - * - * @param entropy An entropy source instance. - */ -static void entropy_with_fw_override_enable(dif_entropy_src_t *entropy_src) { - const dif_entropy_src_fw_override_config_t fw_override_config = { - .entropy_insert_enable = true, - .buffer_threshold = kEntropyFifoBufferSize, - }; - CHECK_DIF_OK(dif_entropy_src_fw_override_configure( - entropy_src, fw_override_config, kDifToggleEnabled)); - - const dif_entropy_src_config_t config = { - .fips_enable = true, - .route_to_firmware = true, - .single_bit_mode = kDifEntropySrcSingleBitModeDisabled, - .health_test_threshold_scope = false, - .health_test_window_size = 0x0200, - .alert_threshold = 2, - }; - CHECK_DIF_OK( - dif_entropy_src_configure(entropy_src, config, kDifToggleEnabled)); -} - -/** - * Rounds known answer test for the entropy_src SHA-3 conditioner. - * - * This test uses the following SHA3 CAVP test vector: - * - * Msg=a90d2aa5b241e1ca9dab5b6dc05c3e2c93fc5a2210a6315d60f9b791b36b560d70e135ef8e7dba9441b74e53dab0606b - * MD=4a16881ce156f45fdfdb45088e3f23be1b4c5a7a6a35315d36c51c75f275733319aca185d4ab33130ffe45f751f1bbc5 - * - * See: - * https://csrc.nist.gov/projects/cryptographic-algorithm-validation-program/secure-hashing - */ -static void test_fuse_init(dif_entropy_src_t *entropy) { - CHECK_DIF_OK(dif_entropy_src_set_enabled(entropy, kDifToggleDisabled)); - entropy_with_fw_override_enable(entropy); - CHECK_DIF_OK(dif_entropy_src_conditioner_start(entropy)); - - const uint32_t kInputMsg[kEntropyFifoBufferSize] = { - 0xa52a0da9, 0xcae141b2, 0x6d5bab9d, 0x2c3e5cc0, 0x225afc93, 0x5d31a610, - 0x91b7f960, 0x0d566bb3, 0xef35e170, 0x94ba7d8e, 0x534eb741, 0x6b60b0da, - }; - CHECK_DIF_OK(dif_entropy_src_observe_fifo_write(entropy, kInputMsg, - ARRAYSIZE(kInputMsg), NULL)); - - CHECK_DIF_OK(dif_entropy_src_conditioner_stop(entropy)); -} - -void test_fuse_enable(dif_entropy_src_t *entropy) { - test_fuse_init(entropy); - - uint32_t got[kEntropyFifoBufferSize]; - for (size_t i = 0; i < ARRAYSIZE(got); ++i) { - CHECK_DIF_OK(dif_entropy_src_non_blocking_read(entropy, &got[i])); - } - - const uint32_t kExpectedDigest[kEntropyFifoBufferSize] = { - 0x1c88164a, 0x5ff456e1, 0x0845dbdf, 0xbe233f8e, 0x7a5a4c1b, 0x5d31356a, - 0x751cc536, 0x337375f2, 0x85a1ac19, 0x1333abd4, 0xf745fe0f, 0xc5bbf151, - }; - CHECK_ARRAYS_EQ(got, kExpectedDigest, kEntropyFifoBufferSize, - "Unexpected digest value."); -} - -static void test_fuse_disable(dif_entropy_src_t *entropy) { - enum { - kAttemptsAmount = 4, - kAttemptIntervalMicros = 500, - }; - - uint32_t got; - test_fuse_init(entropy); - for (uint32_t tries = 0; tries < kAttemptsAmount; --tries) { - CHECK(dif_entropy_src_non_blocking_read(entropy, &got) == kDifUnavailable); - busy_spin_micros(kAttemptIntervalMicros); - } -} - -/** - * Read the otp at `HW_CFG.EN_ENTROPY_SRC_FW_READ` address and check whether is - * configured by the `uvm_test_seq` as expected. - * - * @param expected Define the expected value for the - * HW_CFG.EN_ENTROPY_SRC_FW_READ flag. - */ -static void check_entropy_src_fw_read_enable(bool expected) { - dif_otp_ctrl_t otp; - CHECK_DIF_OK(dif_otp_ctrl_init( - mmio_region_from_addr(TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR), &otp)); - - dif_otp_ctrl_config_t config = { - .check_timeout = 100000, - .integrity_period_mask = 0x3ffff, - .consistency_period_mask = 0x3ffffff, - }; - CHECK_DIF_OK(dif_otp_ctrl_configure(&otp, config)); - CHECK_STATUS_OK(otp_ctrl_testutils_wait_for_dai(&otp)); - - uint32_t value; - // Read the current value of the partition. - CHECK_DIF_OK(dif_otp_ctrl_dai_read_start(&otp, kDifOtpCtrlPartitionHwCfg0, - kOtpIfetchHwRelativeOffset)); - CHECK_STATUS_OK(otp_ctrl_testutils_wait_for_dai(&otp)); - CHECK_DIF_OK(dif_otp_ctrl_dai_read32_end(&otp, &value)); - multi_bit_bool_t enable = bitfield_field32_read( - value, - (bitfield_field32_t){.mask = 0xff, .index = kOtpEntropySrcFwReadOffset}); - CHECK((enable == kMultiBitBool8True) == expected, - "`fw_enable` not expected (%x)", enable); -} - -/** - * This test: - * - * - Initialize the OTP with the `HW_CFG.EN_ENTROPY_SRC_FW_READ` fuse bit set to - * enabled in the `uvm_test_seq`. - * - Read and verify the OTP `HW_CFG.EN_ENTROPY_SRC_FW_READ` against the - * previous step expectation. - * - Read the entropy_data_fifo via SW; verify that it reads valid values. - * - Reset the chip, but this time, initialize the OTP with the - * `HW_CFG.EN_ENTROPY_SRC_FW_READ` fuse bit set to disable. - * - Read and verify the OTP `HW_CFG.EN_ENTROPY_SRC_FW_READ` against the - * previous step expectation. - * - Read the internal state via SW; verify that the entropy valid bit is zero. - */ -bool test_main(void) { - dif_entropy_src_t entropy_src; - CHECK_DIF_OK(dif_entropy_src_init( - mmio_region_from_addr(TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR), &entropy_src)); - - dif_rstmgr_t rstmgr; - dif_rstmgr_reset_info_bitfield_t info; - CHECK_DIF_OK(dif_rstmgr_init( - mmio_region_from_addr(TOP_EARLGREY_RSTMGR_AON_BASE_ADDR), &rstmgr)); - info = rstmgr_testutils_reason_get(); - - if (info == kDifRstmgrResetInfoPor) { - LOG_INFO("Powered up for the first time"); - check_entropy_src_fw_read_enable(true); - test_fuse_enable(&entropy_src); - // Reboot device. - rstmgr_testutils_reason_clear(); - CHECK_DIF_OK(dif_rstmgr_software_device_reset(&rstmgr)); - - // This log message is extremely important for the test, as the - // `uvm_test_seq` uses it to change the otp values. - LOG_INFO("Software resetting!"); - - // Wait here until device reset. - wait_for_interrupt(); - } else if (info == kDifRstmgrResetInfoSw) { - LOG_INFO("Powered up for the second time"); - - check_entropy_src_fw_read_enable(false); - test_fuse_disable(&entropy_src); - return true; - } - return false; -} diff --git a/sw/host/opentitanlib/src/dif/otp_ctrl.rs b/sw/host/opentitanlib/src/dif/otp_ctrl.rs index 24d8dfa17c667..f617842cf8385 100644 --- a/sw/host/opentitanlib/src/dif/otp_ctrl.rs +++ b/sw/host/opentitanlib/src/dif/otp_ctrl.rs @@ -225,8 +225,6 @@ pub enum DaiParam { ManufState, EnSramIfetch, EnCsrngSwAppRead, - EnEntropySrcFwRead, - EnEntropySrcFwOver, // SECRET0 TestUnlockToken, TestExitToken, @@ -266,14 +264,6 @@ impl DaiParam { byte_addr: dif::OTP_CTRL_PARAM_EN_CSRNG_SW_APP_READ_OFFSET, size: dif::OTP_CTRL_PARAM_EN_CSRNG_SW_APP_READ_SIZE, }; - pub const EN_ENTROPY_SRC_FW_READ: OtpParamMmap = OtpParamMmap { - byte_addr: dif::OTP_CTRL_PARAM_EN_ENTROPY_SRC_FW_READ_OFFSET, - size: dif::OTP_CTRL_PARAM_EN_ENTROPY_SRC_FW_READ_SIZE, - }; - pub const EN_ENTROPY_SRC_FW_OVER: OtpParamMmap = OtpParamMmap { - byte_addr: dif::OTP_CTRL_PARAM_EN_ENTROPY_SRC_FW_OVER_OFFSET, - size: dif::OTP_CTRL_PARAM_EN_ENTROPY_SRC_FW_OVER_SIZE, - }; pub const TEST_UNLOCK_TOKEN: OtpParamMmap = OtpParamMmap { byte_addr: dif::OTP_CTRL_PARAM_TEST_UNLOCK_TOKEN_OFFSET, size: dif::OTP_CTRL_PARAM_TEST_UNLOCK_TOKEN_SIZE, @@ -316,8 +306,6 @@ impl DaiParam { Self::ManufState => Self::MANUF_STATE, Self::EnSramIfetch => Self::EN_SRAM_IFETCH, Self::EnCsrngSwAppRead => Self::EN_CSRNG_SW_APP_READ, - Self::EnEntropySrcFwRead => Self::EN_ENTROPY_SRC_FW_READ, - Self::EnEntropySrcFwOver => Self::EN_ENTROPY_SRC_FW_OVER, Self::TestUnlockToken => Self::TEST_UNLOCK_TOKEN, Self::TestExitToken => Self::TEST_EXIT_TOKEN, Self::FlashAddrKeySeed => Self::FLASH_ADDR_KEY_SEED, @@ -338,8 +326,6 @@ impl DaiParam { Self::ManufState => Partition::HW_CFG0, Self::EnSramIfetch => Partition::HW_CFG0, Self::EnCsrngSwAppRead => Partition::HW_CFG0, - Self::EnEntropySrcFwRead => Partition::HW_CFG0, - Self::EnEntropySrcFwOver => Partition::HW_CFG0, Self::TestUnlockToken => Partition::SECRET0, Self::TestExitToken => Partition::SECRET0, Self::FlashAddrKeySeed => Partition::SECRET1, diff --git a/sw/host/opentitanlib/src/otp/testdata/otp_ctrl_mmap.hjson b/sw/host/opentitanlib/src/otp/testdata/otp_ctrl_mmap.hjson index 870bcb706b442..9b0e6ef43077d 100644 --- a/sw/host/opentitanlib/src/otp/testdata/otp_ctrl_mmap.hjson +++ b/sw/host/opentitanlib/src/otp/testdata/otp_ctrl_mmap.hjson @@ -219,7 +219,7 @@ write_lock: "Digest", read_lock: "None", key_sel: "NoKey", - ecc_fatal: true, + integrity: true, bkout_type: true, items: [ { @@ -247,27 +247,13 @@ ismubi: true, inv_default: false }, - { - name: "EN_ENTROPY_SRC_FW_READ", - size: "1", - ismubi: true, - inv_default: false - }, - { - name: "EN_ENTROPY_SRC_FW_OVER", - size: "1", - ismubi: true, - inv_default: false - }, ], desc: ''' + DEVICE_ID: Unique device identifier. + MANUF_STATE: Vector for capturing the manufacturing status. EN_SRAM_IFETCH: Enable / disable execute from SRAM CSR switch. EN_CSRNG_SW_APP_READ: This input efuse is used to enable access to the NIST internal state per instance. - EN_ENTROPY_SRC_FW_READ: This input efuse is used to enable access - to the ENTROPY_DATA register directly. - EN_ENTROPY_SRC_FW_OVER: This input efuse is used to enable access - to the firmware override FIFO and other related functions. ''' } { diff --git a/util/topgen/templates/toplevel.sv.tpl b/util/topgen/templates/toplevel.sv.tpl index 8b903839effba..46a6e73f66207 100644 --- a/util/topgen/templates/toplevel.sv.tpl +++ b/util/topgen/templates/toplevel.sv.tpl @@ -234,10 +234,6 @@ module top_${top["name"]} #( // be performed by hand. assign csrng_otp_en_csrng_sw_app_read = otp_ctrl_otp_broadcast.hw_cfg0_data.en_csrng_sw_app_read; - assign entropy_src_otp_en_entropy_src_fw_read = - otp_ctrl_otp_broadcast.hw_cfg0_data.en_entropy_src_fw_read; - assign entropy_src_otp_en_entropy_src_fw_over = - otp_ctrl_otp_broadcast.hw_cfg0_data.en_entropy_src_fw_over; assign sram_ctrl_main_otp_en_sram_ifetch = otp_ctrl_otp_broadcast.hw_cfg0_data.en_sram_ifetch; assign lc_ctrl_otp_device_id =