From 74ecc7910fc79ccde7819a9be898c668d9a0b8e0 Mon Sep 17 00:00:00 2001 From: Miguel Osorio Date: Tue, 23 Apr 2024 14:33:49 -0700 Subject: [PATCH] [entropy_src] Keep applying fw_ov_rd_fifo_overflow Keep applying fw_ov_rd_fifo_overflow instead of pulsing. This commit is a manual port of the following Opentitan commit: b454878f2528b49318ff2b604cb8d59a6e59b0ea Which is associated with https://github.com/lowRISC/opentitan/pull/21640. Original commit description: This commit applies the fw_ov_rd_fifo_overflow signal in case of an overflow. It used to only send a pulse through the register but now the signal is applied until the FIFO has been emptied once and is receiving contiguous data again. This commit also aligns the documentation for the FW_OV_RD_FIFO_OVERFLOW register. The register is now not clearable by software. It instead is cleared by hardware. Signed-off-by: Miguel Osorio --- .github/workflow_metadata/pr_hash | 2 +- .github/workflow_metadata/pr_timestamp | 2 +- src/entropy_src/data/entropy_src.hjson | 4 ++-- src/entropy_src/data/entropy_src.json | 6 +++--- src/entropy_src/data/entropy_src.rdl | 5 ++--- src/entropy_src/rtl/entropy_src_core.sv | 10 +++++----- src/entropy_src/rtl/entropy_src_reg_top.sv | 10 ++++------ 7 files changed, 18 insertions(+), 21 deletions(-) diff --git a/.github/workflow_metadata/pr_hash b/.github/workflow_metadata/pr_hash index 2890cf28b..090656ffd 100644 --- a/.github/workflow_metadata/pr_hash +++ b/.github/workflow_metadata/pr_hash @@ -1 +1 @@ -d80fa2173c00ce84dc0c744ca9d1ee6a99eb54891d7eb6c172e6a38905699c12fd517b389bcff0698dfb7d352f7cda6c \ No newline at end of file +4207d937698d49ca879659d561a60bcbfc427e004f3af67e1f8e31648eb770d625aa4916abba5503d5a8ef9788b159a1 \ No newline at end of file diff --git a/.github/workflow_metadata/pr_timestamp b/.github/workflow_metadata/pr_timestamp index cff033a9f..d4cf11d74 100644 --- a/.github/workflow_metadata/pr_timestamp +++ b/.github/workflow_metadata/pr_timestamp @@ -1 +1 @@ -1712949801 \ No newline at end of file +1713993516 \ No newline at end of file diff --git a/src/entropy_src/data/entropy_src.hjson b/src/entropy_src/data/entropy_src.hjson index 65202bab5..9549fc77f 100644 --- a/src/entropy_src/data/entropy_src.hjson +++ b/src/entropy_src/data/entropy_src.hjson @@ -1176,7 +1176,7 @@ }, { name: "FW_OV_RD_FIFO_OVERFLOW", desc: "Firmware override Observe FIFO overflow status", - swaccess: "rw0c", + swaccess: "ro", hwaccess: "hwo", hwext: "false", fields: [ @@ -1187,7 +1187,7 @@ in the Observe FIFO. The RNG data rate is slow enough that firmware should always be able to keep up. This register meanwhile provides an additional check to confirm that bytes read from the !!FW_OV_RD_DATA register represent contiguous RNG samples. - If an overflow event occurs, this bit must be cleared by software. + If an overflow event occurs, this bit is cleared by hardware as soon as the FIFO is emptied. ''' } ] diff --git a/src/entropy_src/data/entropy_src.json b/src/entropy_src/data/entropy_src.json index 522b3403e..df7fd3a2c 100644 --- a/src/entropy_src/data/entropy_src.json +++ b/src/entropy_src/data/entropy_src.json @@ -1072,14 +1072,14 @@ { "name": "FW_OV_RD_FIFO_OVERFLOW", "desc": "Firmware override Observe FIFO overflow status", - "swaccess": "rw0c", + "swaccess": "ro", "hwaccess": "hwo", "hwext": "false", "fields": [ { "bits": "0", "name": "FW_OV_RD_FIFO_OVERFLOW", - "desc": "This bit is set by hardware whenever RNG data is lost due to an overflow condition\nin the Observe FIFO. The RNG data rate is slow enough that firmware should always\nbe able to keep up. This register meanwhile provides an additional check to confirm\nthat bytes read from the !!FW_OV_RD_DATA register represent contiguous RNG samples.\nIf an overflow event occurs, this bit must be cleared by software." + "desc": "This bit is set by hardware whenever RNG data is lost due to an overflow condition\nin the Observe FIFO. The RNG data rate is slow enough that firmware should always\nbe able to keep up. This register meanwhile provides an additional check to confirm\nthat bytes read from the !!FW_OV_RD_DATA register represent contiguous RNG samples.\nIf an overflow event occurs, this bit is cleared by hardware as soon as the FIFO is emptied." } ] }, @@ -1366,4 +1366,4 @@ ] } ] -} +} \ No newline at end of file diff --git a/src/entropy_src/data/entropy_src.rdl b/src/entropy_src/data/entropy_src.rdl index 764740366..200bf5dcd 100644 --- a/src/entropy_src/data/entropy_src.rdl +++ b/src/entropy_src/data/entropy_src.rdl @@ -688,9 +688,8 @@ addrmap entropy_src { in the Observe FIFO. The RNG data rate is slow enough that firmware should always be able to keep up. This register meanwhile provides an additional check to confirm that bytes read from the !!FW_OV_RD_DATA register represent contiguous RNG samples. - If an overflow event occurs, this bit must be cleared by software."; - sw = rw; - onwrite = woclr; + If an overflow event occurs, this bit is cleared by hardware as soon as the FIFO is emptied."; + sw = r; } FW_OV_RD_FIFO_OVERFLOW[0:0]; } FW_OV_RD_FIFO_OVERFLOW @ 0xBC; reg { diff --git a/src/entropy_src/rtl/entropy_src_core.sv b/src/entropy_src/rtl/entropy_src_core.sv index be691a1f6..a76b96fc3 100644 --- a/src/entropy_src/rtl/entropy_src_core.sv +++ b/src/entropy_src/rtl/entropy_src_core.sv @@ -5,8 +5,8 @@ // Description: entropy_src core module // -module entropy_src_core - import entropy_src_pkg::*; +module entropy_src_core + import entropy_src_pkg::*; import lc_ctrl_state_pkg::*; import lc_ctrl_reg_pkg::*; import lc_ctrl_pkg::*; @@ -2336,8 +2336,8 @@ module entropy_src_core // contiguous as possible. logic sfifo_observe_gate_d, sfifo_observe_gate_q; - assign sfifo_observe_gate_d = (sfifo_observe_push && sfifo_observe_full) ? 1'b0 : - !sfifo_observe_not_empty ? 1'b1 : + assign sfifo_observe_gate_d = (pfifo_postht_pop && sfifo_observe_full) ? 1'b0 : + !sfifo_observe_not_empty ? 1'b1 : sfifo_observe_gate_q; always_ff @(posedge clk_i or negedge rst_ni) begin @@ -2348,7 +2348,7 @@ module entropy_src_core end end - assign hw2reg.fw_ov_rd_fifo_overflow.d = (pfifo_postht_pop && sfifo_observe_full); + assign hw2reg.fw_ov_rd_fifo_overflow.d = !sfifo_observe_gate_d; assign hw2reg.fw_ov_rd_fifo_overflow.de = 1'b1; assign observe_fifo_thresh_met = fw_ov_mode && (observe_fifo_thresh != '0) && diff --git a/src/entropy_src/rtl/entropy_src_reg_top.sv b/src/entropy_src/rtl/entropy_src_reg_top.sv index de571706a..bfeb93373 100644 --- a/src/entropy_src/rtl/entropy_src_reg_top.sv +++ b/src/entropy_src/rtl/entropy_src_reg_top.sv @@ -2222,15 +2222,15 @@ module entropy_src_reg_top #( // R[fw_ov_rd_fifo_overflow]: V(False) caliptra_prim_subreg #( .DW (1), - .SwAccess(caliptra_prim_subreg_pkg::SwAccessW0C), + .SwAccess(caliptra_prim_subreg_pkg::SwAccessRO), .RESVAL (1'h0) ) u_fw_ov_rd_fifo_overflow ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface - .we (fw_ov_rd_fifo_overflow_we), - .wd (fw_ov_rd_fifo_overflow_wd), + .we (1'b0), + .wd ('0), // from internal hardware .de (hw2reg.fw_ov_rd_fifo_overflow.de), @@ -3476,9 +3476,7 @@ module entropy_src_reg_top #( assign fw_ov_sha3_start_wd = reg_wdata[3:0]; assign fw_ov_wr_fifo_full_re = addr_hit[46] & reg_re & !reg_error; - assign fw_ov_rd_fifo_overflow_we = addr_hit[47] & reg_we & !reg_error; - assign fw_ov_rd_fifo_overflow_wd = reg_wdata[0]; assign fw_ov_rd_data_re = addr_hit[48] & reg_re & !reg_error; assign fw_ov_wr_data_we = addr_hit[49] & reg_we & !reg_error; @@ -3573,7 +3571,7 @@ module entropy_src_reg_top #( reg_we_check[44] = fw_ov_control_gated_we; reg_we_check[45] = fw_ov_sha3_start_we; reg_we_check[46] = 1'b0; - reg_we_check[47] = fw_ov_rd_fifo_overflow_we; + reg_we_check[47] = 1'b0; reg_we_check[48] = 1'b0; reg_we_check[49] = fw_ov_wr_data_we; reg_we_check[50] = observe_fifo_thresh_gated_we;