From 6becaf8f817d077f885a82d8ef48087f2dcca583 Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Mon, 28 May 2018 13:48:16 +0200 Subject: [PATCH] arch: arm: Set Zero Latency IRQ to priority level zero: Set Zero Latency IRQ to priority level zero and SVCs to priority level one when Zero Latency IRQ is enabled. This makes Zero Zatency truly zero latency when the kernel has been configured with userspace enabled, or when IRQ offloading is used. Exceptions can still delay Zero Latency IRQ, but this is considered ok since exceptions indicate a serious error, and the system needs to recover. Fixes: #7869 Signed-off-by: Joakim Andersson --- arch/arm/core/cortex_m/Kconfig | 20 +++++++++++--------- include/arch/arm/cortex_m/exc.h | 5 +++-- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/arch/arm/core/cortex_m/Kconfig b/arch/arm/core/cortex_m/Kconfig index e5eec3611cce7b..ba7ba9efd88230 100644 --- a/arch/arm/core/cortex_m/Kconfig +++ b/arch/arm/core/cortex_m/Kconfig @@ -317,15 +317,17 @@ config ZERO_LATENCY_IRQS default n depends on CPU_CORTEX_M_HAS_BASEPRI help - Interrupt locking is done by setting exception masking to priority - one, thus allowing exception of priority zero to still come in. By - default, the kernel verifies, via __ASSERT() statements, that the - interrupt priority is not set to zero when either connecting them or - setting their priority. Enabling this option disables the check, - thus allowing setting the priority of interrupts to zero. - - Note that this is a somewhat dangerous option: ISRs of priority zero - interrupts cannot use any kernel functionality. + The kernel may reserve some of the highest interrupts priorities in + the system for its own use. These interrupts will not be masked + by interrupt locking. + When connecting interrupts the kernel will offset all interrupts + to lower priority than those reserved by the kernel. + Zero-latency interrupt can be used to set up an interrupt at the + highest interrupt priority which will not be blocked by interrupt + locking. + Since Zero-latency ISRs will run in the same priority or possibly at + higher priority than the rest of the kernel they cannot use any + kernel functionality. config SW_VECTOR_RELAY bool diff --git a/include/arch/arm/cortex_m/exc.h b/include/arch/arm/cortex_m/exc.h index 4b130a08b8ab1a..36700f161a5653 100644 --- a/include/arch/arm/cortex_m/exc.h +++ b/include/arch/arm/cortex_m/exc.h @@ -27,12 +27,13 @@ extern "C" { #define _EXCEPTION_RESERVED_PRIO 0 #endif -#define _EXC_SVC_PRIO 0 #define _EXC_FAULT_PRIO 0 #ifdef CONFIG_ZERO_LATENCY_IRQS -#define _EXC_ZERO_LATENCY_IRQS_PRIO 1 +#define _EXC_ZERO_LATENCY_IRQS_PRIO 0 +#define _EXC_SVC_PRIO 1 #define _IRQ_PRIO_OFFSET (_EXCEPTION_RESERVED_PRIO + 1) #else +#define _EXC_SVC_PRIO 0 #define _IRQ_PRIO_OFFSET (_EXCEPTION_RESERVED_PRIO) #endif