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  1. ivl_uvm ivl_uvm Public

    Adding UVM support to Icarus Verilog (and Verilator in near future) by taking a step-by-step, bottom-up approach.

    SystemVerilog 23 39

  2. pyslint pyslint Public

    SystemVerilog Linter based on pyslang

    SystemVerilog 20 22

  3. MathLib MathLib Public

    MathLib DAC 2023 version

    SystemVerilog 11 6

  4. apb_uvc_verilator apb_uvc_verilator Public

    APB UVC ported to Verilator

    SystemVerilog 11 3

  5. benchbot benchbot Public

    A Python based VHDL app to improve productivity of VHDL designs

    VHDL 6 7

  6. af_sva_apb af_sva_apb Public

    AsFigo's opensource SVA IP for APB protocol + SVUnit tests on Verilator

    Verilog 2 3

Repositories

Showing 9 of 9 repositories
  • FVLint Public

    Custom linter for Formal Verification using SVA

    AsFigo/FVLint’s past year of commit activity
    0 0 8 0 Updated Oct 20, 2024
  • SVALint Public

    Linter for SystemVerilog Assertions (SVA). Following the philosophy of BYOL - Build Your Own Linter, SVALint is an example of ho users can roll out their own linters!

    AsFigo/SVALint’s past year of commit activity
    1 0 12 0 Updated Oct 14, 2024
  • benchbot Public

    A Python based VHDL app to improve productivity of VHDL designs

    AsFigo/benchbot’s past year of commit activity
    VHDL 6 7 1 0 Updated Jun 14, 2024
  • pyslint Public

    SystemVerilog Linter based on pyslang

    AsFigo/pyslint’s past year of commit activity
    SystemVerilog 20 MIT 22 55 6 Updated Mar 18, 2024
  • af_sva_apb Public

    AsFigo's opensource SVA IP for APB protocol + SVUnit tests on Verilator

    AsFigo/af_sva_apb’s past year of commit activity
    Verilog 2 MIT 3 0 1 Updated Nov 30, 2023
  • apb_uvc_verilator Public

    APB UVC ported to Verilator

    AsFigo/apb_uvc_verilator’s past year of commit activity
    SystemVerilog 11 GPL-3.0 3 0 0 Updated Nov 19, 2023
  • MathLib Public

    MathLib DAC 2023 version

    AsFigo/MathLib’s past year of commit activity
    SystemVerilog 11 6 1 4 Updated Sep 11, 2023
  • VHLD_parse Public Forked from svenka3/VHLD_parse

    A collection of Python scripts to make working with VHDL easier

    AsFigo/VHLD_parse’s past year of commit activity
    Python 0 MIT 2 0 0 Updated Jun 20, 2023
  • ivl_uvm Public

    Adding UVM support to Icarus Verilog (and Verilator in near future) by taking a step-by-step, bottom-up approach.

    AsFigo/ivl_uvm’s past year of commit activity
    SystemVerilog 23 39 4 (1 issue needs help) 1 Updated Dec 27, 2022

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