01
m03, 50 iio6 => iio6(2)
m11.6, 17.6, 35.6, 41.6 V7(64) => V7
m12, 13, 14.6, 17, 18, 19, 21, 35, 36, 37, 38.6, 41, 42, 43 I64 => I
m14.3, 38.3 I6 => V(6)
m15.4, 39.4 V =>
m24.4, 26, 30.4, 32 V43(62) => V43(+6+2)
m25, m26.6, 31,32.6 V43(6) => V43(+6)\
02
m01 Db.I => .Db.I
m01.3, 02.3 IV(2) => IV(9)
m03.2 I(42) => I(94)
m03.3 I(27) => I(97)
m06.3 V64(2) => V43(9)
m08.4 bVI+ => .bVI+
m08.4 Fr6 => It6
m09.2 V7(2)\\ => V7(9)\\
m10-12 analog
m13.4 Ger6 => .Ger6
m14.4 V7 => V7(6)
m15.2 I(2) => I(9)\
03
m01 Db.V43/V => .Db.V43/V
m01.2 Ger6 => .Ger6
m02.2 iii%65-V(6#4) => V[V(6#4)
m03.3 viio43 => #viio43/ii
m09 V => V\\
m09.2, 10.2, 11.2 vi7 => vi43
m12.2, 21.2 viio7/vi => #viio7/vi
m14.2, 23.2 I => I\\
m27.2 .bVI.V => #V.V
m29.2 .bIII.V => #II.V
m33-34 {.bII VII VII I}.V2(4) => I.IV(+9)/{#I VII VI V}
rest analog