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Nic30 edited this page Dec 4, 2018 · 1 revision

ABC: System for Sequential Logic Synthesis and Formal Verification

ABC has many internal representation AIG, BDD, ... they usually corresponds to formal models. There is also a Verilog parser in abc/src/base/ver/.

  • License: custom
  • GIT: https:/berkeley-abc/abc
  • Internal representation: netlist, formal models
  • Optimization alg. paradigm: many

Internal representation

Abc_Ntk_t

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