AArch32: addrmode3 incorrectly had load in address pointer export #6607
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ryanmkurtz
added
Feature: Processor/ARM
Status: Triage
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With this patch applied I get a lot of build errors at least for Ghidra Staging: |
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You're right @jobermayr, you have to give it a size. Since everything else is exporting a varnode based on |
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…ot a memory address
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As part of a research project testing the accuracy of the SLEIGH specifications compared to real hardware, we observed unexpected behaviours in a few instructions that used
addrmode3constructor for AArch32 (ARM:LE:32:v8).According to the manual, the instruction in the example stores two words from two registers to memory. However, we noticed the output was incorrect.
e.g, for AArch32 with,
Instruction:
0xf000cfb1 or 0xf0004fb1, strdlt r0,r1,[0x10000008]initial_registers:
{ "r0": 0xaabc1448, "r1": 0x1923c5ef, "NG": 0x1 }initial_memory:
{ "0x10000008": [ 0xfd, 0xd6, 0xf0, 0x8f ] }We get:
Hardware:
{ 0x10000008: 0x48, 0x10000009: 0x14, 0x1000000A: 0xbc, 0x1000000B: 0xaa, 0x1000000C: 0xef, 0x1000000D: 0xc5, 0x1000000E: 0x23, 0x1000000F: 0x19 }Patched Spec:
{ 0x10000008: 0x48, 0x10000009: 0x14, 0x1000000A: 0xbc, 0x1000000B: 0xaa, 0x1000000C: 0xef, 0x1000000D: 0xc5, 0x1000000E: 0x23, 0x1000000F: 0x19 }Existing Spec:
{ 0x8FF0D6FD: 0x48, 0x8FF0D6FE: 0x14, 0x8FF0D6FF: 0xbc, 0x8FF0D700: 0xaa, 0x8FF0D701: 0xef, 0x8FF0D702: 0xc5, 0x8FF0D703: 0x23, 0x8FF0D704: 0x19 }Note: The patched spec does not introduce any disassembly changes to the best of our knowledge.