The CR2 register was only written to if the settings differ from the
reset value. This wasn't actually a bug, since it was cleared in
`spi_release()` to the reset value again. Still, it looks like a bug,
may cause a pipeline flush due to the branch, and increased `.text`
size. So let's get rid of this.

This doesn't change the firmware, since for all STM32 MCUs with an
SPI driver the register setting in the mode did match the SPI mode
number by chance. But for some STM32 MCUs with no SPI driver yet
the register layout is indeed different. This will help to provide an
SPI driver for them as well.

Previously, the /CS signal was performed by enabling / disabling the
SPI peripheral. This had the disadvantage that clock polarity settings
where not applied starting with `spi_acquire()`, as assumed by e.g.
the SPI SD card driver, but only just before transmitting data.

Now the SPI peripheral is enabled on `spi_acquire()` and only disabled
when calling `spi_release()`, and the `SPI_CR2_SSOE` bit in the `CR2`
register is used for hardware /CS handling (as supposed to).

With only 8 possible prescalers, we can just loop over the values
and shift the clock. In addition to being much easier to read, using
shifts over divisions can be a lot faster on CPUs without hardware
division.

In addition an `assert()` is added that checks if the API contract
regarding the SPI frequency is honored. If the requested clock is too
low to be generated, we should rather have a blown assertion than
hard to trace communication errors.

Finally, the term prescaler is used instead of divider, as divider may
imply that the frequency is divided by the given value n, but
in fact is divided by 2^(n+1).