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[sonic_ax_impl]: Update the code to use common library API for bridge…
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…/port mapping (sonic-net#39)

* Update the code to use common library API for bridge/port mapping
* Safety check to continue instead of raising exception
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prsunny authored and Shuotian Cheng committed Sep 28, 2017
1 parent 8dfcbd2 commit 6996123
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Showing 2 changed files with 9 additions and 53 deletions.
42 changes: 5 additions & 37 deletions src/sonic_ax_impl/mibs/__init__.py
Original file line number Diff line number Diff line change
Expand Up @@ -2,14 +2,13 @@
import re

from swsssdk import SonicV2Connector

from swsssdk import port_util
from swsssdk.port_util import get_index
from sonic_ax_impl import logger, _if_alias_map

COUNTERS_PORT_NAME_MAP = b'COUNTERS_PORT_NAME_MAP'
LAG_TABLE = b'LAG_TABLE'
LAG_MEMBER_TABLE = b'LAG_MEMBER_TABLE'
SONIC_ETHERNET_RE_PATTERN = "^Ethernet(\d+)$"
SONIC_PORTCHANNEL_RE_PATTERN = "^PortChannel(\d+)$"
APPL_DB = 'APPL_DB'
ASIC_DB = 'ASIC_DB'
COUNTERS_DB = 'COUNTERS_DB'
Expand Down Expand Up @@ -48,32 +47,6 @@ def lag_entry_table(lag_name):
return b'LAG_TABLE:' + lag_name


def get_index(if_name):
"""
OIDs are 1-based, interfaces are 0-based, return the 1-based index
Ethernet N = N + 1
PortChannel N = N + 1000
"""
return get_index_from_str(if_name.decode())


def get_index_from_str(if_name):
"""
OIDs are 1-based, interfaces are 0-based, return the 1-based index
Ethernet N = N + 1
PortChannel N = N + 1000
"""
patterns = {
SONIC_ETHERNET_RE_PATTERN: 1,
SONIC_PORTCHANNEL_RE_PATTERN: 1000
}

for pattern, baseidx in patterns.items():
match = re.match(pattern, if_name)
if match:
return int(match.group(1)) + baseidx


def config(**kwargs):
global redis_kwargs
redis_kwargs = {k:v for (k,v) in kwargs.items() if k in ['unix_socket_path', 'host', 'port']}
Expand Down Expand Up @@ -101,13 +74,8 @@ def init_sync_d_interface_tables(db_conn):

# { if_name (SONiC) -> sai_id }
# ex: { "Ethernet76" : "1000000000023" }
if_name_map = db_conn.get_all(COUNTERS_DB, COUNTERS_PORT_NAME_MAP, blocking=True)
if_name_map, if_id_map = port_util.get_interface_oid_map(db_conn)
logger.debug("Port name map:\n" + pprint.pformat(if_name_map, indent=2))

# { sai_id -> if_name (SONiC) }
if_id_map = {sai_id: if_name for if_name, sai_id in if_name_map.items()
# only map the interface if it's a style understood to be a SONiC interface.
if get_index(if_name) is not None}
logger.debug("Interface name map:\n" + pprint.pformat(if_id_map, indent=2))

# { OID -> sai_id }
Expand All @@ -128,13 +96,13 @@ def init_sync_d_interface_tables(db_conn):
# In the event no interface exists that follows the SONiC pattern, no OIDs are able to be registered.
# A RuntimeError here will prevent the 'main' module from loading. (This is desirable.)
message = "No interfaces found matching pattern '{}'. SyncD database is incoherent." \
.format(SONIC_ETHERNET_RE_PATTERN)
.format(port_util.SONIC_ETHERNET_RE_PATTERN)
logger.error(message)
raise RuntimeError(message)
elif len(if_id_map) < len(if_name_map) or len(oid_sai_map) < len(if_name_map):
# a length mismatch indicates a bad interface name
logger.warning("SyncD database contains incoherent interface names. Interfaces must match pattern '{}'"
.format(SONIC_ETHERNET_RE_PATTERN))
.format(port_util.SONIC_ETHERNET_RE_PATTERN))
logger.warning("Port name map:\n" + pprint.pformat(if_name_map, indent=2))

# { SONiC name -> optional rename }
Expand Down
20 changes: 4 additions & 16 deletions src/sonic_ax_impl/mibs/ietf/rfc4363.py
Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,7 @@
from enum import unique, Enum

from sonic_ax_impl import mibs
from swsssdk import port_util
from ax_interface import MIBMeta, ValueType, MIBUpdater, ContextualMIBEntry, SubtreeMIBEntry
from ax_interface.util import mac_decimals
from bisect import bisect_right
Expand Down Expand Up @@ -34,23 +35,8 @@ def reinit_data(self):
self.prev_if_id_map = self.if_id_map
self.invalid_port_oids = set()

## Note: get the bridge port ID to port ID mapping
## In FDB entry, the bridge port ID is available which is one-to-one mapping with port ID
## TODO: LAG in VLAN is to be supported
self.if_bpid_map = {}
self.db_conn.connect(mibs.ASIC_DB)
bridge_port_strings = self.db_conn.keys(mibs.ASIC_DB, "ASIC_STATE:SAI_OBJECT_TYPE_BRIDGE_PORT:*")

if not bridge_port_strings:
return
self.if_bpid_map = port_util.get_bridge_port_map(self.db_conn)

for s in bridge_port_strings:
# Example output: ASIC_STATE:SAI_OBJECT_TYPE_BRIDGE_PORT:oid:0x3a000000000616
bridge_port_id = s[45:]
ent = self.db_conn.get_all(mibs.ASIC_DB, s, blocking=True)
if b"SAI_BRIDGE_PORT_ATTR_PORT_ID" in ent:
port_id = ent[b"SAI_BRIDGE_PORT_ATTR_PORT_ID"][6:]
self.if_bpid_map[bridge_port_id] = port_id

def update_data(self):
"""
Expand All @@ -76,6 +62,8 @@ def update_data(self):
ent = self.db_conn.get_all(mibs.ASIC_DB, s, blocking=True)
# Example output: oid:0x3a000000000608
bridge_port_id = ent[b"SAI_FDB_ENTRY_ATTR_BRIDGE_PORT_ID"][6:]
if bridge_port_id not in self.if_bpid_map:
continue
port_id = self.if_bpid_map[bridge_port_id]

vlanmac = fdb_vlanmac(fdb)
Expand Down

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