Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

ATSAME51J20A chip #78

Merged
merged 5 commits into from
Sep 23, 2022
Merged

ATSAME51J20A chip #78

merged 5 commits into from
Sep 23, 2022

Conversation

r4gus
Copy link
Contributor

@r4gus r4gus commented Sep 10, 2022

  • MAIN_CLK
    • 48MHz on startup via DFLL48M -> GCLK0 -> GCLK_MAIN
  • GPIO
    • PA{0..31}
    • PB{0..31}
  • UART
    • Via SERCOM5 (PB16 (TX) and PB17 (RX))
    • Clocked by GCLK2 at 48MHz

@mattnite
Copy link
Contributor

I've run this locally and it builds so merging.

@mattnite mattnite merged commit e280cca into ZigEmbeddedGroup:main Sep 23, 2022
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers
No reviews
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
2 participants
@r4gus @mattnite