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Initial partial SPI support #97

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merged 57 commits into from
Feb 1, 2023

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@marnix marnix commented Dec 31, 2022

Here is an initial SPI support PR; still draft for now, see below.

It adds an API much like in Discord #microzig message https://discord.com/channels/824493524413710336/824629907089784832/947090519484411945.

And an implementation for that API for the STM32F303.

Here is some code that I've got working on my STM32F3DISCOVERY revision E.02 board, which has an I3G4250D gyroscope connected to the STM32's SPI1 with CS on pin PE3:

        const spi1 = try microzig.Spi(1).init(.{});
        var gyro = spi1.device(microzig.chip.parsePin("PE3"), .{});

        var gyro_id: u8 = undefined;
        {
            var transfer = try gyro.beginTransfer();
            defer transfer.end();
            // read no-autoincrement WHO_AM_I = 0x0F
            try transfer.writer().writeByte(0x80 + 0x0F);
            gyro_id = try transfer.reader().readByte(); // returns 0xD3
        }

What really must go in here before merging:

  • Do a clean split between bus configuration (like setting SPIx_CR SPE to enable an STM32 SPI bus) and device configuration (like clock polarity+phase).
  • Actually use the PE3 pin parameter, it is currently hardcoded in the STM32F303 implementation.
  • Code clean-up, and more/better doc comments.

What should be in here before merging:

  • spi.zig support for 'registers' like the I2C implementation has.
  • spi.zig support for transceive...() functions.

Update Dec 31, 2022, 15:03 UTC: All of the above was completed, I consider this PR ready for review, removing draft status.

What I would like to leave for later:

  • Make clock speed configurable (instead of choosing slowest available).
  • Support more SPI buses.
  • Allow support for SPI devices with different clock phase and/or polarity.
  • Read various status bits and return new ReadError or WriteError values as appropriate.
  • A replacement for the hack to wait long enough for the SPI device to detect 'end of transfer'.
  • Support data frame sizes other than 8 bits, and related MSB/LSB configuration.
  • Support DMA-based reads/writes.
  • Support interrupt-based operation.
  • Support SPI slave mode.

marnix and others added 30 commits February 9, 2022 19:14
All code assumes default chip clock configuration.
Code assumes STM32F303xB / STM32F3030xC.
Code supports only 8 data bits, 1 stop bit.
This is done by implementing `debugWrite()` for the board,
which only initializes UART1 if that was not yet done,
and flushes afterwards to make sure the host receives all.
This is done by implementing `rx()` and `canRead()`.
This includes correctly masking the parity bit
on reads.
Support uart stm32f3discovery: Make UART1 support complete
Allows only writing and reading single bytes.
Now using controller/device terminology, instead of master/slave.

Now using 'transfer objects' to make STOPs and re-STARTs explicit,
and allow using Writer and Reader APIs.

Added 'register' abstraction.

STM32F303 I2C now supports this new API, and multi-byte transfers.

Now waiting for I2C_ISR.BUSY == 0, after setting I2C_CR2.STOP == 1.
Without this, the sequence write-stop-write caused an additional STOP
to be sent immediately the START and address of the second write.
marnix and others added 24 commits March 16, 2022 17:45
It needs to be a non-`comptime` `var` for `@export` to work properly.

The only 'documentation' for this behavior currently seems GitHub comment
ziglang/zig#5157 (comment) .

This issue was introduced in 1c17304 for PR ZigEmbeddedGroup#27,
which broke at least ARM-based STM32F303.
Specifically,
top-level `Spi` is now `SpiBus`;
and the internal API has an additional `switchToDevice()`,
and receives `DeviceConfig` in more places.
@marnix marnix marked this pull request as ready for review December 31, 2022 15:02
@ikskuh ikskuh merged commit e1c1466 into ZigEmbeddedGroup:main Feb 1, 2023
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3 participants