Doc markdown fixes.

doc/components/adder.md

@@ -108,11 +108,11 @@ Here is an example of instantiating a `SignMagnitudeAdder`:
 
 A compound carry adder is a digital circuit used for binary addition. It produces sum and sum+1 outputs.
 A trivial compound adder component [`TrivialCompoundAdder`]<https://intel.github.io/rohd-hcl/rohd_hcl/TrivialCompoundAdder-class.html> doesnt use any RTL code optimization.
-Carry-select adder-based compound adder [`CarrySelectCompoundAdder`](https://intel.github.io/rohd-hcl/rohd_hcl/CarrySelectCompoundAdder-class.html) uses carry-select adder as a basis. Like a carry-select adder it consists of a multiple blocks of two ripple-carry adders (https://en.wikipedia.org/wiki/Carry-select_adder). But the first block has two ripple-carry adders and two separate carry-propagate chains are used to select sum and sum+1 output bits. sum selecting chain starts from carry input 'zero' driven block and sum+1 selecting chain starts from carry input 'one' driven block.
-The delay of the adder is defined by combination ripple-carry adder and accumulated carry-select chain delay. 
+Carry-select adder-based compound adder [`CarrySelectCompoundAdder`]<https://intel.github.io/rohd-hcl/rohd_hcl/CarrySelectCompoundAdder-class.html> uses carry-select adder as a basis. Like a carry-select adder it consists of a multiple blocks of two ripple-carry adders <https://en.wikipedia.org/wiki/Carry-select_adder>. But the first block has two ripple-carry adders and two separate carry-propagate chains are used to select sum and sum+1 output bits. sum selecting chain starts from carry input 'zero' driven block and sum+1 selecting chain starts from carry input 'one' driven block.
+The delay of the adder is defined by combination ripple-carry adder and accumulated carry-select chain delay.
 
-The [`CarrySelectCompoundAdder`](https://intel.github.io/rohd-hcl/rohd_hcl/CarrySelectCompoundAdder-class.html) module in ROHD-HCL accept input `Logic`s a and b as the input pin and the name of the module `name`. Note that the width of the inputs must be the same or a `RohdHclException` will be thrown.
-Compound adder generator provides two alogithms for splitting adder into ripple-carry blocks. [CarrySelectCompoundAdder.splitSelectAdderAlgorithm4Bit] algoritm splits adder into blocks of 4-bit ripple-carry adders with the first one width adjusted down. [CarrySelectCompoundAdder.splitSelectAdderAlgorithmSingleBlock] algorithm generates only one block of full bitwidth of the adder. Input List<int> Function(int adderFullWidth) [widthGen] should be used to specify custom adder splitting algorithm that return a list of sub-adders width. The default one is [CarrySelectCompoundAdder.splitSelectAdderAlgorithmSingleBlock].
+The [`CarrySelectCompoundAdder`]<https://intel.github.io/rohd-hcl/rohd_hcl/CarrySelectCompoundAdder-class.html> module in ROHD-HCL accept input `Logic`s a and b as the input pin and the name of the module `name`. Note that the width of the inputs must be the same or a `RohdHclException` will be thrown.
+Compound adder generator provides two alogithms for splitting adder into ripple-carry blocks. [CarrySelectCompoundAdder.splitSelectAdderAlgorithm4Bit] algoritm splits adder into blocks of 4-bit ripple-carry adders with the first one width adjusted down. [CarrySelectCompoundAdder.splitSelectAdderAlgorithmSingleBlock] algorithm generates only one block of full bitwidth of the adder. Input List\<int\> Function(int adderFullWidth) [widthGen] should be used to specify custom adder splitting algorithm that return a list of sub-adders width. The default one is [CarrySelectCompoundAdder.splitSelectAdderAlgorithmSingleBlock].
 
 An example is shown below to add two inputs of signals that have 8-bits of width.