cope with I$ miss on teensy #405
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if the instruction cache is completely flushed *even before* the counter is read, under specific situations (presumably when relevant parts of show() are on different cache lines), the first bit would not be sent (but discarded), often leading to a change in colour. prevent compiler optimisation across counter reads, order the delays so that they are easier to reason about.
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if the instruction cache is completely flushed even before the counter is read, under specific situations (presumably when relevant parts of show() are on different cache lines), the first bit would not be sent (but discarded), often leading to a change in colour.
prevent compiler optimisation across counter reads, order the delays so that they are easier to reason about.
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this is supposed to fix instruction cache invalidation breaks timing on teensy4 #404
the patch was tested against version 1.1.7 (blame platformio...), but the relevant part of the teensy code seems to not have changed since then. will test with master in a bit.