test.vcd

$date
	Thu May 01 02:30:33 2014
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module test $end
$var reg 1 ! clk $end
$scope module arm $end
$var event 1 " _s20 $end
$var wire 1 # alu_is_writeback $end
$var wire 4 $ alu_nzcv [3:0] $end
$var wire 32 % alu_result [31:0] $end
$var wire 1 & c_to_alu $end
$var wire 1 ' clk $end
$var wire 32 ( cspr [31:0] $end
$var wire 32 ) instr [31:0] $end
$var wire 32 * memory_out_data [31:0] $end
$var wire 32 + mult_result [31:0] $end
$var wire 32 , out_data_1 [31:0] $end
$var wire 32 - out_data_2 [31:0] $end
$var wire 32 . out_data_3 [31:0] $end
$var wire 32 / out_data_4 [31:0] $end
$var wire 32 0 pc [31:0] $end
$var wire 32 1 shifter_result [31:0] $end
$var wire 4 2 type [3:0] $end
$var wire 1 3 will_this_be_executed $end
$var reg 1 4 ALU_MEM_alu_is_writeback $end
$var reg 4 5 ALU_MEM_alu_nzcv [3:0] $end
$var reg 32 6 ALU_MEM_alu_result [31:0] $end
$var reg 1 7 ALU_MEM_flush $end
$var reg 32 8 ALU_MEM_instr [31:0] $end
$var reg 32 9 ALU_MEM_mult_result [31:0] $end
$var reg 32 : ALU_MEM_out_data_1 [31:0] $end
$var reg 32 ; ALU_MEM_out_data_2 [31:0] $end
$var reg 32 < ALU_MEM_out_data_3 [31:0] $end
$var reg 32 = ALU_MEM_out_data_4 [31:0] $end
$var reg 4 > ALU_MEM_type [3:0] $end
$var reg 1 ? ALU_MEM_will_this_be_executed $end
$var reg 1 @ F_R_flush $end
$var reg 32 A F_R_instr [31:0] $end
$var reg 4 B F_R_type [3:0] $end
$var reg 1 C MEM_W_alu_is_writeback $end
$var reg 4 D MEM_W_alu_nzcv [3:0] $end
$var reg 32 E MEM_W_alu_result [31:0] $end
$var reg 1 F MEM_W_flush $end
$var reg 32 G MEM_W_instr [31:0] $end
$var reg 32 H MEM_W_memory_out_data [31:0] $end
$var reg 32 I MEM_W_mult_result [31:0] $end
$var reg 32 J MEM_W_out_data_1 [31:0] $end
$var reg 32 K MEM_W_out_data_2 [31:0] $end
$var reg 32 L MEM_W_out_data_3 [31:0] $end
$var reg 32 M MEM_W_out_data_4 [31:0] $end
$var reg 4 N MEM_W_type [3:0] $end
$var reg 1 O MEM_W_will_this_be_executed $end
$var reg 32 P MUL_ALU_data_1_fwd [31:0] $end
$var reg 1 Q MUL_ALU_data_1_use_fwd $end
$var reg 32 R MUL_ALU_data_2_fwd [31:0] $end
$var reg 1 S MUL_ALU_data_2_use_fwd $end
$var reg 32 T MUL_ALU_data_3_fwd [31:0] $end
$var reg 1 U MUL_ALU_data_3_use_fwd $end
$var reg 32 V MUL_ALU_data_4_fwd [31:0] $end
$var reg 1 W MUL_ALU_data_4_use_fwd $end
$var reg 1 X MUL_ALU_flush $end
$var reg 32 Y MUL_ALU_instr [31:0] $end
$var reg 32 Z MUL_ALU_mult_result [31:0] $end
$var reg 32 [ MUL_ALU_out_data_1 [31:0] $end
$var reg 32 \ MUL_ALU_out_data_2 [31:0] $end
$var reg 32 ] MUL_ALU_out_data_3 [31:0] $end
$var reg 32 ^ MUL_ALU_out_data_4 [31:0] $end
$var reg 4 _ MUL_ALU_type [3:0] $end
$var reg 1 ` MUL_ALU_will_this_be_executed $end
$var reg 1 a R_MUL_flush $end
$var reg 32 b R_MUL_instr [31:0] $end
$var reg 32 c R_MUL_out_data_1 [31:0] $end
$var reg 32 d R_MUL_out_data_2 [31:0] $end
$var reg 32 e R_MUL_out_data_3 [31:0] $end
$var reg 32 f R_MUL_out_data_4 [31:0] $end
$var reg 4 g R_MUL_type [3:0] $end
$var reg 4 h alu_opcode [3:0] $end
$var reg 32 i alu_operand_1 [31:0] $end
$var reg 32 j alu_operand_2 [31:0] $end
$var reg 32 k cspr_update [31:0] $end
$var reg 1 l cspr_write $end
$var reg 32 m current_pc [31:0] $end
$var reg 1 n fetch_instr $end
$var reg 1 o isByte $end
$var reg 32 p memory_data_address [31:0] $end
$var reg 32 q memory_in_data [31:0] $end
$var reg 1 r memory_read_enable $end
$var reg 1 s memory_write_enable $end
$var reg 1 t number_stalls $end
$var reg 4 u nzcv_forward [3:0] $end
$var reg 32 v out_data_1_fwd [31:0] $end
$var reg 1 w out_data_1_use_fwd $end
$var reg 32 x out_data_2_fwd [31:0] $end
$var reg 1 y out_data_2_use_fwd $end
$var reg 32 z out_data_3_fwd [31:0] $end
$var reg 1 { out_data_3_use_fwd $end
$var reg 32 | out_data_4_fwd [31:0] $end
$var reg 1 } out_data_4_use_fwd $end
$var reg 32 ~ pc_update [31:0] $end
$var reg 1 !" pc_write $end
$var reg 1 "" use_shifter $end
$var reg 1 #" want_to_flush $end
$var reg 4 $" write_address [3:0] $end
$var reg 4 %" write_address_2 [3:0] $end
$var reg 32 &" write_data [31:0] $end
$var reg 32 '" write_data_2 [31:0] $end
$var reg 1 (" write_enable $end
$var reg 1 )" write_enable_2 $end
$scope module InstructionCache $end
$var wire 32 *" PC [31:0] $end
$var wire 1 ' clk $end
$var wire 1 +" read_enable $end
$var reg 32 ," instr [31:0] $end
$upscope $end
$scope module InstructionDecoder $end
$var wire 32 -" ir [31:0] $end
$var reg 4 ." type [3:0] $end
$upscope $end
$scope module RegisterFile $end
$var wire 1 ' clk $end
$var wire 32 /" cspr_update [31:0] $end
$var wire 1 0" cspr_write $end
$var wire 4 1" in_address1 [3:0] $end
$var wire 4 2" in_address2 [3:0] $end
$var wire 4 3" in_address3 [3:0] $end
$var wire 4 4" in_address4 [3:0] $end
$var wire 32 5" pc_update [31:0] $end
$var wire 1 6" pc_write $end
$var wire 4 7" write_address [3:0] $end
$var wire 4 8" write_address2 [3:0] $end
$var wire 32 9" write_data [31:0] $end
$var wire 32 :" write_data2 [31:0] $end
$var wire 1 ;" write_enable $end
$var wire 1 <" write_enable2 $end
$var reg 32 =" cspr [31:0] $end
$var reg 32 >" out_data1 [31:0] $end
$var reg 32 ?" out_data2 [31:0] $end
$var reg 32 @" out_data3 [31:0] $end
$var reg 32 A" out_data4 [31:0] $end
$var reg 32 B" pc [31:0] $end
$upscope $end
$scope module Multiplier $end
$var wire 32 C" Rm [31:0] $end
$var wire 32 D" Rs [31:0] $end
$var wire 32 E" result [31:0] $end
$upscope $end
$scope module BarrelShifter $end
$var wire 32 F" Rm [31:0] $end
$var wire 32 G" Rs [31:0] $end
$var wire 1 H" cin $end
$var wire 32 I" direct_data [31:0] $end
$var wire 12 J" imm_value [11:0] $end
$var wire 1 K" instr_bit_25 $end
$var wire 32 L" operand2 [31:0] $end
$var wire 1 M" use_shifter $end
$var reg 1 N" c_to_alu $end
$var reg 32 O" in [31:0] $end
$var reg 32 P" junk [31:0] $end
$var reg 32 Q" out [31:0] $end
$var reg 8 R" shiftby [7:0] $end
$upscope $end
$scope module ALU $end
$var wire 1 & c_from_shifter $end
$var wire 4 S" nzcv_old [3:0] $end
$var wire 4 T" opcode [3:0] $end
$var wire 32 U" operand_1 [31:0] $end
$var wire 32 V" operand_2 [31:0] $end
$var reg 1 W" cin $end
$var reg 1 X" cout $end
$var reg 1 Y" isWriteback $end
$var reg 32 Z" neg [31:0] $end
$var reg 4 [" nzcv [3:0] $end
$var reg 32 \" result [31:0] $end
$upscope $end
$scope module conditionFieldChecker $end
$var wire 4 ]" condition_code [3:0] $end
$var wire 4 ^" nzcv [3:0] $end
$var reg 1 _" will_this_be_executed $end
$upscope $end
$scope module DataCache $end
$var wire 1 ' clk $end
$var wire 32 `" data_address [31:0] $end
$var wire 32 a" in_data [31:0] $end
$var wire 1 b" isByte $end
$var wire 1 c" read_enable $end
$var wire 1 d" write_enable $end
$var reg 32 e" out_data [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
bx e"
0d"
0c"
xb"
bx a"
bx `"
x_"
bx ^"
bx ]"
bx \"
bx ["
bx Z"
1Y"
xX"
xW"
bx V"
bx U"
b100 T"
bx S"
bx R"
bx Q"
bx P"
bx O"
xN"
1M"
bx L"
xK"
bx J"
bx I"
xH"
bx G"
bx F"
bx E"
bx D"
bx C"
b0 B"
bx A"
bx @"
bx ?"
bx >"
b0 ="
x<"
0;"
bx :"
bx 9"
bx 8"
bx 7"
16"
b1000 5"
bx 4"
bx 3"
bx 2"
bx 1"
00"
b0 /"
b1001 ."
bx -"
bx ,"
1+"
b100 *"
x)"
0("
bx '"
bx &"
bx %"
bx $"
0#"
1""
1!"
b1000 ~
0}
bx |
0{
bx z
0y
bx x
0w
bx v
bx u
0t
0s
0r
bx q
bx p
xo
1n
b100 m
0l
b0 k
bx j
bx i
b100 h
b1001 g
bx f
bx e
bx d
bx c
bx b
xa
x`
b1001 _
bx ^
bx ]
bx \
bx [
bx Z
bx Y
xX
0W
bx V
0U
bx T
0S
bx R
0Q
bx P
xO
b1001 N
bx M
bx L
bx K
bx J
bx I
bx H
bx G
xF
bx E
bx D
xC
b1001 B
bx A
0@
x?
b1001 >
bx =
bx <
bx ;
bx :
bx 9
bx 8
x7
bx 6
bx 5
14
x3
b1001 2
bx 1
b0 0
bx /
bx .
bx -
bx ,
bx +
bx *
bx )
b0 (
1'
x&
bx %
bx $
1#
1"
1!
$end
#1
b111 ."
b111 2
b11100011101000000000000000000000 ,"
b11100011101000000000000000000000 )
b11100011101000000000000000000000 -"
0!
0'
#2
b0 1"
b0 2"
b0 3"
b0 4"
b1100 ~
b1100 5"
b111 B
b11100011101000000000000000000000 A
0a
1C
b1000 m
b1000 *"
1!
1'
#3
b0 A"
b0 /
b0 @"
b0 .
b0 ?"
b0 -
b0 >"
b0 ,
b11100011101000000001000000000001 ,"
b11100011101000000001000000000001 )
b11100011101000000001000000000001 -"
0!
0'
#4
1_"
13
b1 2"
b1 4"
b1110 ]"
b10000 ~
b10000 5"
b11100011101000000001000000000001 A
b0 f
b0 C"
b0 +
b0 E"
b0 e
b0 D"
b0 d
b0 c
b11100011101000000000000000000000 b
b111 g
0X
b1100 m
b1100 *"
1!
1'
#5
b11100000100100010011000000000010 ,"
b11100000100100010011000000000010 )
b11100000100100010011000000000010 -"
0!
0'
#6
b0 T
b0 P
b0 z
b1xx $
b1xx ^"
b0 \"
b0 %
b0 1
b0 L"
b0 V"
b1xx ["
b1 1"
b11 2"
b10 4"
b0 P"
b0 Q"
b0 R"
b0 O"
1K"
b0 J"
1U
1Q
1{
b1101 h
b1101 T"
b0 i
b0 U"
b10100 ~
b10100 5"
b11100000100100010011000000000010 A
b11100011101000000001000000000001 b
b0 Z
b0 ^
b0 F"
b0 ]
b0 G"
b0 \
b0 [
b11100011101000000000000000000000 Y
b111 _
1`
07
b10000 m
b10000 *"
1!
1'
#7
b11100001101000000001000000000010 ,"
b11100001101000000001000000000010 )
b11100001101000000001000000000010 -"
0!
0'
#8
b1 P
b0xx $
b0xx ^"
b1 \"
b1 %
b1 1
b1 L"
b1 V"
b1 P"
b1 Q"
b0 R"
b1 O"
b0 1"
b1 2"
b1 J"
b0xx ["
1y
b1 x
1w
b0 v
0U
1Q
1{
b11000 ~
b11000 5"
b11100001101000000001000000000010 A
b11100000100100010011000000000010 b
b11100011101000000001000000000001 Y
b1xx u
b1xx S"
b1xx 5
b0 6
b0 9
b0 =
b0 <
b0 ;
b0 :
b11100011101000000000000000000000 8
b111 >
1?
0F
b10100 m
b10100 *"
1!
1'
#9
b11100001101000000010000000000011 ,"
b11100001101000000010000000000011 )
b11100001101000000010000000000011 -"
0!
0'
#10
b0 1
b0 L"
b0 V"
b0 Q"
b0 O"
b10 2"
b11 4"
0K"
b10 J"
b0 ["
b0 $
b0 ^"
0X"
0W"
b1 \"
b1 %
1}
b1 |
0Q
1{
0y
1w
b100 h
b100 T"
b1 i
b1 U"
b11100 ~
b11100 5"
b1xx0000000000000000000000000000 k
b1xx0000000000000000000000000000 /"
0)"
0<"
1("
1;"
b0 &"
b0 9"
b0 $"
b0 7"
b11100001101000000010000000000011 A
b1 d
b11100001101000000001000000000010 b
b1 [
b11100000100100010011000000000010 Y
b0xx u
b0xx S"
b0xx 5
b1 6
b11100011101000000001000000000001 8
b1xx D
b0 E
b0 I
b0 M
b0 L
b0 K
b0 J
b11100011101000000000000000000000 G
b111 N
1O
b11000 m
b11000 *"
1!
1'
#11
b1011 ."
b1011 2
b111010111111111111111111111011 ,"
b111010111111111111111111111011 )
b111010111111111111111111111011 -"
0!
0'
#12
0N"
0&
b1111 1"
b1111 2"
b1111 3"
b1011 4"
0H"
b100 ["
b100 $
b100 ^"
b0 \"
b0 %
0}
0{
0w
b1101 h
b1101 T"
b0 i
b0 U"
b100000 ~
b100000 5"
b0xx0000000000000000000000000000 k
b0xx0000000000000000000000000000 /"
b1 &"
b1 9"
b1 $"
b1 7"
b1011 B
b111010111111111111111111111011 A
b1 f
b1 C"
b0 d
b11100001101000000010000000000011 b
b1 \
b0 [
b11100001101000000001000000000010 Y
b0 u
b0 S"
b0 5
b1 :
b11100000100100010011000000000010 8
b0xx D
b1 E
b11100011101000000001000000000001 G
b11100 m
b11100 *"
1!
1'
#13
b111 ."
b111 2
b1 B"
b1 0
b11100011101000000111000000000001 ,"
b11100011101000000111000000000001 )
b11100011101000000111000000000001 -"
b11100 @"
b11100 .
b11100 ?"
b11100 -
b11100 >"
b11100 ,
0!
0'
#14
b0 $
b0 ^"
b1 \"
b1 %
b1 1
b1 L"
b1 V"
b0 1"
b111 2"
b0 3"
b1 4"
b11 ]"
b1 Q"
b1 O"
b11 J"
b0 ["
1}
b0 |
b100100 ~
b100100 5"
1l
10"
b0 k
b0 /"
b11 $"
b11 7"
b111 B
b11100011101000000111000000000001 A
b0 f
b0 C"
b11100 e
b11100 D"
b0 +
b0 E"
b11100 d
b11100 c
b111010111111111111111111111011 b
b1011 g
b1 ^
b1 F"
b0 \
b11100001101000000010000000000011 Y
b100 u
b100 S"
b100 5
b0 6
b1 ;
b0 :
b11100001101000000001000000000010 8
b0 D
b1 J
b11100000100100010011000000000010 G
b100000 m
b100000 *"
1!
1'
#15
b1 A"
b1 /
b0 @"
b0 .
b0 ?"
b0 -
b0 >"
b0 ,
b11100011101000000111000000000010 ,"
b11100011101000000111000000000010 )
b11100011101000000111000000000010 -"
0!
0'
#16
b10 $
b10 ^"
1X"
1W"
b11111111111111111111111111101100 1
b11111111111111111111111111101100 L"
b11111111111111111111111111101100 V"
b10 4"
b1110 ]"
b0 P"
b1111101100 Q"
b11110 R"
b11111011 O"
1K"
b111111111011 J"
b10 ["
b1100 \"
b1100 %
b1 |
1}
b100 h
b100 T"
0""
0M"
b11111111111111111111111111101100 j
b11111111111111111111111111101100 I"
b100000 i
b100000 U"
b101000 ~
b101000 5"
0l
00"
b1000000000000000000000000000000 k
b1000000000000000000000000000000 /"
b0 &"
b0 9"
b1 $"
b1 7"
b11100011101000000111000000000010 A
b0 e
b0 D"
b0 d
b0 c
b11100011101000000111000000000001 b
b111 g
b0 ^
b0 F"
b11100 ]
b11100 G"
b11100 \
b11100 [
b111010111111111111111111111011 Y
b1011 _
b0 u
b0 S"
b0 5
b1 6
b1 =
b0 ;
b11100001101000000010000000000011 8
b100 D
b0 E
b1 K
b0 J
b11100001101000000001000000000010 G
b100100 m
b100100 *"
1!
1'
#17
b0 B"
b0 0
b0 A"
b0 /
0!
0'
#18
b1 1
b1 L"
b1 V"
1N"
1&
b1 P"
b1 Q"
b0 R"
b1 O"
b1 J"
1H"
b10 ["
b10 $
b10 ^"
b1 \"
b1 %
1S
b1 R
1y
b1 x
1}
b1101 h
b1101 T"
1""
1M"
b0 i
b0 U"
b101100 ~
b101100 5"
b0 k
b0 /"
b1 &"
b1 9"
b10 $"
b10 7"
b1 f
b1 C"
b11100011101000000111000000000010 b
b0 ]
b0 G"
b0 \
b0 [
b11100011101000000111000000000001 Y
b111 _
b10 u
b10 S"
b10 5
b1100 6
b0 =
b11100 <
b11100 ;
b11100 :
b111010111111111111111111111011 8
b1011 >
b0 D
b1 E
b1 M
b0 K
b11100001101000000010000000000011 G
b101000 m
b101000 *"
1!
1'
#19
b11100011101000000111000000000011 ,"
b11100011101000000111000000000011 )
b11100011101000000111000000000011 -"
0!
0'
#20
b10 R
b10 x
b10 ["
b10 \"
b10 %
b10 1
b10 L"
b10 V"
b11 4"
b10 P"
b10 Q"
b0 R"
b10 O"
b10 J"
1S
0}
1y
0("
0;"
b1100 ~
b1100 5"
17
1X
1a
1@
1#"
b11100011101000000111000000000011 A
b1 d
b1 ^
b1 F"
b1 \
b11100011101000000111000000000010 Y
b1 6
b0 <
b0 ;
b0 :
b11100011101000000111000000000001 8
b111 >
b10 D
b1100 E
b0 M
b11100 L
b11100 K
b11100 J
b111010111111111111111111111011 G
b1011 N
b101100 m
b101100 *"
1!
1'
#21
b11100011101000000111000000000100 ,"
b11100011101000000111000000000100 )
b11100011101000000111000000000100 -"
b1 A"
b1 /
0!
0'
#22
b100 4"
0S
0y
b10000 ~
b10000 5"
0#"
b11100011101000000111000000000100 A
b10 d
b11100011101000000111000000000011 b
b10 \
0`
b10 6
b1 =
b1 ;
b11100011101000000111000000000010 8
0?
1F
b1 E
b0 L
b0 K
b0 J
b11100011101000000111000000000001 G
b111 N
0O
b1100 m
b1100 *"
1!
1'
#23
b0 A"
b0 /
b11100000100100010011000000000010 ,"
b11100000100100010011000000000010 )
b11100000100100010011000000000010 -"
0!
0'
#24
b10 ["
b11 \"
b11 %
b11 1
b11 L"
b11 V"
b11 P"
b11 Q"
b0 R"
b11 O"
b1 1"
b11 2"
b10 4"
b11 J"
b10100 ~
b10100 5"
0@
b11100000100100010011000000000010 A
b0 f
b0 C"
b0 d
b11100011101000000111000000000100 b
b11100011101000000111000000000011 Y
b10 ;
b10 E
b1 M
b1 K
b11100011101000000111000000000010 G
b10000 m
b10000 *"
1!
1'
#25
b11100001101000000001000000000010 ,"
b11100001101000000001000000000010 )
b11100001101000000001000000000010 -"
b1 A"
b1 /
b1 ?"
b1 -
0!
0'
#26
b10 ["
b100 \"
b100 %
b100 1
b100 L"
b100 V"
b0 1"
b1 2"
b100 P"
b100 Q"
b0 R"
b100 O"
b100 J"
b11000 ~
b11000 5"
b11100001101000000001000000000010 A
0a
b1 f
b1 C"
b1 d
b11100000100100010011000000000010 b
b0 ^
b0 F"
b0 \
b11100011101000000111000000000100 Y
b11 6
b11100011101000000111000000000011 8
b10 K
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