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xnu-qemu-arm64-5.1.0.diff
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xnu-qemu-arm64-5.1.0.diff
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diff --git a/xnu-qemu-arm64-5.1.0/hw/arm/Makefile.objs b/xnu-qemu-arm64-5.1.0/hw/arm/Makefile.objs
index 534a6a1..3cd9b77 100644
--- a/xnu-qemu-arm64-5.1.0/hw/arm/Makefile.objs
+++ b/xnu-qemu-arm64-5.1.0/hw/arm/Makefile.objs
@@ -1,4 +1,4 @@
-obj-y += boot.o
+obj-y += boot.o xnu_fb_cfg.o xnu_trampoline_hook.o xnu_pagetable.o xnu_cpacr.o xnu_dtb.o xnu_file_mmio_dev.o xnu_mem.o xnu.o j273_macos11.o guest-services.o guest-socket.o guest-fds.o guest-file.o
obj-$(CONFIG_PLATFORM_BUS) += sysbus-fdt.o
obj-$(CONFIG_ARM_VIRT) += virt.o
obj-$(CONFIG_ACPI) += virt-acpi-build.o
diff --git a/xnu-qemu-arm64-5.1.0/hw/arm/guest-fds.c b/xnu-qemu-arm64-5.1.0/hw/arm/guest-fds.c
new file mode 100644
index 0000000..f109443
--- /dev/null
+++ b/xnu-qemu-arm64-5.1.0/hw/arm/guest-fds.c
@@ -0,0 +1,72 @@
+/*
+ * QEMU TCP Tunnelling
+ *
+ * Copyright (c) 2019 Lev Aronsky <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdarg.h>
+
+#include "hw/arm/guest-services/fds.h"
+#include "cpu.h"
+
+int32_t guest_svcs_fds[MAX_FD_COUNT] = { [0 ... MAX_FD_COUNT-1] = -1 };
+
+int32_t qc_handle_close(CPUState *cpu, int32_t fd)
+{
+ VERIFY_FD(fd);
+
+ int retval = -1;
+
+ if ((retval = close(guest_svcs_fds[fd])) < 0) {
+ guest_svcs_errno = errno;
+ } else {
+ // TODO: should this be in the "else" clause, or performed regardless?
+ guest_svcs_fds[fd] = -1;
+ }
+
+ return retval;
+}
+
+int32_t qc_handle_fcntl_getfl(CPUState *cpu, int32_t fd)
+{
+ VERIFY_FD(fd);
+
+ int retval = -1;
+
+ if ((retval = fcntl(guest_svcs_fds[fd], F_GETFL)) < 0) {
+ guest_svcs_errno = errno;
+ }
+
+ return retval;
+}
+
+int32_t qc_handle_fcntl_setfl(CPUState *cpu, int32_t fd, int32_t flags)
+{
+ VERIFY_FD(fd);
+
+ int retval = -1;
+
+ if ((retval = fcntl(guest_svcs_fds[fd], F_SETFL, flags)) < 0) {
+ guest_svcs_errno = errno;
+ }
+
+ return retval;
+}
diff --git a/xnu-qemu-arm64-5.1.0/hw/arm/guest-file.c b/xnu-qemu-arm64-5.1.0/hw/arm/guest-file.c
new file mode 100644
index 0000000..f9f4709
--- /dev/null
+++ b/xnu-qemu-arm64-5.1.0/hw/arm/guest-file.c
@@ -0,0 +1,111 @@
+/*
+ * QEMU Host file guest access
+ *
+ * Copyright (c) 2020 Jonathan Afek <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/arm/guest-services/file.h"
+#include "cpu.h"
+
+static int32_t file_fds[MAX_FILE_FDS] = { [0 ... MAX_FILE_FDS-1] = -1 };
+
+void qc_file_open(uint64_t index, const char *filename)
+{
+ if (index >= MAX_FILE_FDS) {
+ abort();
+ }
+ if (-1 != file_fds[index]) {
+ abort();
+ }
+ file_fds[index] = open(filename, O_RDWR);
+ if (-1 == file_fds[index]) {
+ abort();
+ }
+}
+
+int64_t qc_handle_write_file(CPUState *cpu, uint64_t buffer_guest_ptr,
+ uint64_t length, uint64_t offset, uint64_t index)
+{
+ uint8_t buf[MAX_FILE_TRANSACTION_LEN];
+
+ if (index >= MAX_FILE_FDS) {
+ abort();
+ }
+ int fd = file_fds[index];
+ if (-1 == fd) {
+ abort();
+ }
+ if (offset != lseek(fd, offset, SEEK_SET)) {
+ abort();
+ }
+ if (length > MAX_FILE_TRANSACTION_LEN) {
+ abort();
+ }
+ cpu_memory_rw_debug(cpu, buffer_guest_ptr, &buf[0], length, 0);
+ if (length != write(fd, &buf[0], length)) {
+ abort();
+ }
+
+ return 0;
+}
+
+int64_t qc_handle_read_file(CPUState *cpu, uint64_t buffer_guest_ptr,
+ uint64_t length, uint64_t offset, uint64_t index)
+{
+ uint8_t buf[MAX_FILE_TRANSACTION_LEN];
+ if (index >= MAX_FILE_FDS) {
+ abort();
+ }
+ int fd = file_fds[index];
+ if (-1 == fd) {
+ abort();
+ }
+ if (offset != lseek(fd, offset, SEEK_SET)) {
+ abort();
+ }
+ if (length > MAX_FILE_TRANSACTION_LEN) {
+ abort();
+ }
+ if (length != read(fd, &buf[0], length)) {
+ abort();
+ }
+ cpu_memory_rw_debug(cpu, buffer_guest_ptr, &buf[0], length, 1);
+
+ return 0;
+}
+
+int64_t qc_handle_size_file(uint64_t index)
+{
+ struct stat st;
+
+ if (index >= MAX_FILE_FDS) {
+ abort();
+ }
+ int fd = file_fds[index];
+ if (-1 == fd) {
+ abort();
+ }
+ if (-1 == fstat(fd, &st)) {
+ abort();
+ }
+
+ return st.st_size;
+}
diff --git a/xnu-qemu-arm64-5.1.0/hw/arm/guest-services.c b/xnu-qemu-arm64-5.1.0/hw/arm/guest-services.c
new file mode 100644
index 0000000..fed1a7e
--- /dev/null
+++ b/xnu-qemu-arm64-5.1.0/hw/arm/guest-services.c
@@ -0,0 +1,185 @@
+/*
+ * QEMU TCP Tunnelling
+ *
+ * Copyright (c) 2019 Lev Aronsky <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "hw/arm/boot.h"
+#include "exec/address-spaces.h"
+#include "hw/misc/unimp.h"
+#include "sysemu/sysemu.h"
+#include "qemu/error-report.h"
+#include "hw/platform-bus.h"
+
+#include "hw/arm/j273_macos11.h"
+#include "hw/arm/guest-services/general.h"
+#include "hw/arm/xnu_trampoline_hook.h"
+
+int32_t guest_svcs_errno = 0;
+
+uint64_t qemu_call_status(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ // NOT USED FOR NOW
+ return 0;
+}
+
+void qemu_call(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+{
+ CPUState *cpu = qemu_get_cpu(0);
+ qemu_call_t qcall;
+ uint64_t i = 0;
+
+ static uint8_t hooks_installed = false;
+
+ if (!value) {
+ // Special case: not a regular QEMU call. This is used by our
+ // kernel task port patch to notify of the readiness for the
+ // hook installation.
+
+ J273MachineState *nms = J273_MACHINE(qdev_get_machine());
+ KernelTrHookParams *hook = &nms->hook;
+
+ if (0 != hook->va) {
+ //install the hook here because we need the MMU to be already
+ //configured and all the memory mapped before installing the hook
+ xnu_hook_tr_copy_install(hook->va, hook->pa, hook->buf_va,
+ hook->buf_pa, hook->code, hook->code_size,
+ hook->buf_size, hook->scratch_reg);
+
+ }
+
+ if (!hooks_installed) {
+ for (i = 0; i < nms->hook_funcs_count; i++) {
+ xnu_hook_tr_copy_install(nms->hook_funcs[i].va,
+ nms->hook_funcs[i].pa,
+ nms->hook_funcs[i].buf_va,
+ nms->hook_funcs[i].buf_pa,
+ nms->hook_funcs[i].code,
+ nms->hook_funcs[i].code_size,
+ nms->hook_funcs[i].buf_size,
+ nms->hook_funcs[i].scratch_reg);
+ }
+ hooks_installed = true;
+ }
+
+ //emulate original opcode: str x19, [x20]
+ value = env->xregs[19];
+ cpu_memory_rw_debug(cpu, env->xregs[20], (uint8_t*) &value,
+ sizeof(value), 1);
+ ////emulate original opcode: str x20, [x23]
+ //value = env->xregs[20];
+ //cpu_memory_rw_debug(cpu, env->xregs[23], (uint8_t*) &value,
+ // sizeof(value), 1);
+
+ return;
+ }
+
+ // Read the request
+ cpu_memory_rw_debug(cpu, value, (uint8_t*) &qcall, sizeof(qcall), 0);
+
+ switch (qcall.call_number) {
+ // File Descriptors
+ case QC_CLOSE:
+ qcall.retval = qc_handle_close(cpu, qcall.args.close.fd);
+ break;
+ case QC_FCNTL:
+ switch (qcall.args.fcntl.cmd) {
+ case F_GETFL:
+ qcall.retval = qc_handle_fcntl_getfl(
+ cpu, qcall.args.fcntl.fd);
+ break;
+ case F_SETFL:
+ qcall.retval = qc_handle_fcntl_setfl(
+ cpu, qcall.args.fcntl.fd, qcall.args.fcntl.flags);
+ break;
+ default:
+ guest_svcs_errno = EINVAL;
+ qcall.retval = -1;
+ }
+ break;
+
+ // Socket API
+ case QC_SOCKET:
+ qcall.retval = qc_handle_socket(cpu, qcall.args.socket.domain,
+ qcall.args.socket.type,
+ qcall.args.socket.protocol);
+ break;
+ case QC_ACCEPT:
+ qcall.retval = qc_handle_accept(cpu, qcall.args.accept.socket,
+ qcall.args.accept.addr,
+ qcall.args.accept.addrlen);
+ break;
+ case QC_BIND:
+ qcall.retval = qc_handle_bind(cpu, qcall.args.bind.socket,
+ qcall.args.bind.addr,
+ qcall.args.bind.addrlen);
+ break;
+ case QC_CONNECT:
+ qcall.retval = qc_handle_connect(cpu, qcall.args.connect.socket,
+ qcall.args.connect.addr,
+ qcall.args.connect.addrlen);
+ break;
+ case QC_LISTEN:
+ qcall.retval = qc_handle_listen(cpu, qcall.args.listen.socket,
+ qcall.args.listen.backlog);
+ break;
+ case QC_RECV:
+ qcall.retval = qc_handle_recv(cpu, qcall.args.recv.socket,
+ qcall.args.recv.buffer,
+ qcall.args.recv.length,
+ qcall.args.recv.flags);
+ break;
+ case QC_SEND:
+ qcall.retval = qc_handle_send(cpu, qcall.args.send.socket,
+ qcall.args.send.buffer,
+ qcall.args.send.length,
+ qcall.args.send.flags);
+ break;
+ case QC_WRITE_FILE:
+ qcall.retval = qc_handle_write_file(cpu,
+ qcall.args.write_file.buffer_guest_ptr,
+ qcall.args.write_file.length,
+ qcall.args.write_file.offset,
+ qcall.args.write_file.index);
+ break;
+ case QC_READ_FILE:
+ qcall.retval = qc_handle_read_file(cpu,
+ qcall.args.read_file.buffer_guest_ptr,
+ qcall.args.read_file.length,
+ qcall.args.read_file.offset,
+ qcall.args.read_file.index);
+ break;
+ case QC_SIZE_FILE:
+ qcall.retval = qc_handle_size_file(qcall.args.size_file.index);
+ break;
+ default:
+ // TODO: handle unknown call numbers
+ break;
+ }
+
+ qcall.error = guest_svcs_errno;
+
+ // Write the response
+ cpu_memory_rw_debug(cpu, value, (uint8_t*) &qcall, sizeof(qcall), 1);
+}
diff --git a/xnu-qemu-arm64-5.1.0/hw/arm/guest-socket.c b/xnu-qemu-arm64-5.1.0/hw/arm/guest-socket.c
new file mode 100644
index 0000000..fdf9d1e
--- /dev/null
+++ b/xnu-qemu-arm64-5.1.0/hw/arm/guest-socket.c
@@ -0,0 +1,192 @@
+/*
+ * QEMU TCP Tunnelling
+ *
+ * Copyright (c) 2019 Lev Aronsky <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/arm/guest-services/socket.h"
+#include "hw/arm/guest-services/fds.h"
+#include "sys/socket.h"
+#include "cpu.h"
+
+#define SOCKET_TIMEOUT_USECS (10)
+
+static int32_t find_free_socket(void) {
+ for (int i = 0; i < MAX_FD_COUNT; ++i) {
+ if (-1 == guest_svcs_fds[i]) {
+ return i;
+ }
+ }
+
+ guest_svcs_errno = ENOMEM;
+ return -1;
+}
+
+int32_t qc_handle_socket(CPUState *cpu, int32_t domain, int32_t type,
+ int32_t protocol)
+{
+ int retval = find_free_socket();
+
+ if (retval < 0) {
+ guest_svcs_errno = ENOTSOCK;
+ } else if ((guest_svcs_fds[retval] = socket(domain, type, protocol)) < 0) {
+ retval = -1;
+ guest_svcs_errno = errno;
+ }
+
+ return retval;
+}
+
+int32_t qc_handle_accept(CPUState *cpu, int32_t sckt, struct sockaddr *g_addr,
+ socklen_t *g_addrlen)
+{
+ struct sockaddr_in addr;
+ socklen_t addrlen;
+
+ VERIFY_FD(sckt);
+
+ int retval = find_free_socket();
+
+ // TODO: timeout
+ if (retval < 0) {
+ guest_svcs_errno = ENOTSOCK;
+ } else if ((guest_svcs_fds[retval] = accept(guest_svcs_fds[sckt],
+ (struct sockaddr *) &addr,
+ &addrlen)) < 0) {
+ retval = -1;
+ guest_svcs_errno = errno;
+ } else {
+ cpu_memory_rw_debug(cpu, (target_ulong) g_addr, (uint8_t*) &addr,
+ sizeof(addr), 1);
+ cpu_memory_rw_debug(cpu, (target_ulong) g_addrlen,
+ (uint8_t*) &addrlen, sizeof(addrlen), 1);
+ }
+
+ return retval;
+}
+
+int32_t qc_handle_bind(CPUState *cpu, int32_t sckt, struct sockaddr *g_addr,
+ socklen_t addrlen)
+{
+ struct sockaddr_in addr;
+
+ VERIFY_FD(sckt);
+
+ int retval = 0;
+
+ if (addrlen > sizeof(addr)) {
+ guest_svcs_errno = ENOMEM;
+ } else {
+ cpu_memory_rw_debug(cpu, (target_ulong) g_addr, (uint8_t*) &addr,
+ sizeof(addr), 0);
+
+ if ((retval = bind(guest_svcs_fds[sckt], (struct sockaddr *) &addr,
+ addrlen)) < 0) {
+ guest_svcs_errno = errno;
+ } else {
+ cpu_memory_rw_debug(cpu, (target_ulong) g_addr, (uint8_t*) &addr,
+ sizeof(addr), 1);
+ }
+ }
+
+ return retval;
+}
+
+int32_t qc_handle_connect(CPUState *cpu, int32_t sckt, struct sockaddr *g_addr,
+ socklen_t addrlen)
+{
+ struct sockaddr_in addr;
+
+ VERIFY_FD(sckt);
+
+ int retval = 0;
+
+ if (addrlen > sizeof(addr)) {
+ guest_svcs_errno = ENOMEM;
+ } else {
+ cpu_memory_rw_debug(cpu, (target_ulong) g_addr, (uint8_t*) &addr,
+ sizeof(addr), 0);
+
+ if ((retval = connect(guest_svcs_fds[sckt], (struct sockaddr *) &addr,
+ addrlen)) < 0) {
+ guest_svcs_errno = errno;
+ } else {
+ cpu_memory_rw_debug(cpu, (target_ulong) g_addr, (uint8_t*) &addr,
+ sizeof(addr), 1);
+ }
+ }
+
+ return retval;
+}
+
+int32_t qc_handle_listen(CPUState *cpu, int32_t sckt, int32_t backlog)
+{
+ VERIFY_FD(sckt);
+
+ int retval = 0;
+
+ if ((retval = listen(guest_svcs_fds[sckt], backlog)) < 0) {
+ guest_svcs_errno = errno;
+ }
+
+ return retval;
+}
+
+int32_t qc_handle_recv(CPUState *cpu, int32_t sckt, void *g_buffer,
+ size_t length, int32_t flags)
+{
+ VERIFY_FD(sckt);
+ uint8_t buffer[MAX_BUF_SIZE];
+
+ int retval = -1;
+
+ // TODO: timeout
+ if (length > MAX_BUF_SIZE) {
+ guest_svcs_errno = ENOMEM;
+ } else if ((retval = recv(guest_svcs_fds[sckt], buffer, length, flags)) <= 0) {
+ guest_svcs_errno = errno;
+ } else {
+ cpu_memory_rw_debug(cpu, (target_ulong) g_buffer, buffer, retval, 1);
+ }
+
+ return retval;
+}
+
+int32_t qc_handle_send(CPUState *cpu, int32_t sckt, void *g_buffer,
+ size_t length, int32_t flags)
+{
+ VERIFY_FD(sckt);
+ uint8_t buffer[MAX_BUF_SIZE];
+
+ int retval = -1;
+
+ if (length > MAX_BUF_SIZE) {
+ guest_svcs_errno = ENOMEM;
+ } else {
+ cpu_memory_rw_debug(cpu, (target_ulong) g_buffer, buffer, length, 0);
+
+ if ((retval = send(guest_svcs_fds[sckt], buffer, length, flags)) < 0) {
+ guest_svcs_errno = errno;
+ }
+ }
+
+ return retval;
+}
diff --git a/xnu-qemu-arm64-5.1.0/hw/arm/j273_macos11.c b/xnu-qemu-arm64-5.1.0/hw/arm/j273_macos11.c
new file mode 100644
index 0000000..6cda40a
--- /dev/null
+++ b/xnu-qemu-arm64-5.1.0/hw/arm/j273_macos11.c
@@ -0,0 +1,997 @@
+/*
+ * macOS 11 Big Sur - j273 - A12Z
+ *
+ * Copyright (c) 2019 Jonathan Afek <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "hw/arm/boot.h"
+#include "exec/address-spaces.h"
+#include "hw/misc/unimp.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/reset.h"
+#include "qemu/error-report.h"
+#include "hw/platform-bus.h"
+
+#include "hw/arm/j273_macos11.h"
+
+#include "hw/arm/exynos4210.h"
+#include "hw/arm/guest-services/general.h"
+
+#define J273_SECURE_RAM_SIZE (0x100000)
+#define J273_PHYS_BASE (0x40000000)
+
+//compiled nop instruction: mov x0, x0
+#define NOP_INST (0xaa0003e0)
+#define RET_INST (0xd65f03c0) // *NEW*
+#define MOV_W0_01_INST (0x52800020)
+#define CMP_X9_x9_INST (0xeb09013f)
+//compiled instruction: mov w7, #0
+#define W7_ZERO_INST (0x52800007)
+#define W10_ZERO_INST (0x5280000a)
+#define W23_ZERO_INST (0x52800017)
+#define ORR_X0_2_INST (0xb27f0000) // *NEW*
+
+//hook the kernel to execute our "driver" code in this function
+//after things are already running in the kernel but the root mount is not
+//yet mounted.
+//We chose this place in the beginning of ubc_init() inlined in bsd_init()
+//because enough things are up and running for our driver to properly setup,
+//This means that global IOKIT locks and dictionaries are already initialized
+//and in general, the IOKIT system is already initialized.
+//We are now able to initialize our driver and attach it to an existing
+//IOReg object.
+//On the other hand, no mounting of any FS happened yet so we have a chance
+//for our block device driver to present a new block device that will be
+//mounted on the root mount.
+//We need to choose the hook location carefully.
+//We need 3 instructions in a row that we overwrite that are not location
+//dependant (such as adr, adrp and branching) as we are going to execute
+//them elsewhere.
+//We also need a register to use as a scratch register that its value is
+//disregarded right after the hook and does not affect anything.
+#define UBC_INIT_VADDR_16B92 (0xfffffff0073dec10)
+
+#define J273_CPREG_FUNCS(name) \
+static uint64_t j273_cpreg_read_##name(CPUARMState *env, \
+ const ARMCPRegInfo *ri) \
+{ \
+ J273MachineState *nms = (J273MachineState *)ri->opaque; \
+ return nms->J273_CPREG_VAR_NAME(name); \
+} \
+static void j273_cpreg_write_##name(CPUARMState *env, const ARMCPRegInfo *ri, \
+ uint64_t value) \
+{ \
+ J273MachineState *nms = (J273MachineState *)ri->opaque; \
+ nms->J273_CPREG_VAR_NAME(name) = value; \
+}
+
+#define J273_CPREG_DEF(p_name, p_op0, p_op1, p_crn, p_crm, p_op2, p_access) \
+ { .cp = CP_REG_ARM64_SYSREG_CP, \
+ .name = #p_name, .opc0 = p_op0, .crn = p_crn, .crm = p_crm, \
+ .opc1 = p_op1, .opc2 = p_op2, .access = p_access, .type = ARM_CP_IO, \
+ .state = ARM_CP_STATE_AA64, .readfn = j273_cpreg_read_##p_name, \
+ .writefn = j273_cpreg_write_##p_name }
+
+#define ENABLE_EL2_REGS
+
+J273_CPREG_FUNCS(ARM64_REG_EHID1)
+J273_CPREG_FUNCS(ARM64_REG_EHID10)
+J273_CPREG_FUNCS(ARM64_REG_EHID4)
+J273_CPREG_FUNCS(ARM64_REG_HID11)
+J273_CPREG_FUNCS(ARM64_REG_HID3)
+J273_CPREG_FUNCS(ARM64_REG_HID5)
+J273_CPREG_FUNCS(ARM64_REG_HID4)
+J273_CPREG_FUNCS(ARM64_REG_HID8)
+J273_CPREG_FUNCS(ARM64_REG_HID7)
+J273_CPREG_FUNCS(ARM64_REG_LSU_ERR_STS)
+J273_CPREG_FUNCS(PMC0)
+J273_CPREG_FUNCS(PMC1)
+J273_CPREG_FUNCS(PMCR1)
+J273_CPREG_FUNCS(PMSR)
+J273_CPREG_FUNCS(L2ACTLR_EL1)
+#ifdef ENABLE_EL2_REGS
+J273_CPREG_FUNCS(ARM64_REG_MIGSTS_EL1);
+J273_CPREG_FUNCS(ARM64_REG_KERNELKEYLO_EL1);
+J273_CPREG_FUNCS(ARM64_REG_KERNELKEYHI_EL1);
+J273_CPREG_FUNCS(ARM64_REG_VMSA_LOCK_EL1);
+J273_CPREG_FUNCS(APRR_EL0);
+J273_CPREG_FUNCS(APRR_EL1);
+J273_CPREG_FUNCS(CTRR_LOCK);
+J273_CPREG_FUNCS(CTRR_A_LWR_EL1);
+J273_CPREG_FUNCS(CTRR_A_UPR_EL1);
+J273_CPREG_FUNCS(CTRR_CTL_EL1);
+J273_CPREG_FUNCS(APRR_MASK_EN_EL1);
+J273_CPREG_FUNCS(APRR_MASK_EL0);
+J273_CPREG_FUNCS(ACC_CTRR_A_LWR_EL2);
+J273_CPREG_FUNCS(ACC_CTRR_A_UPR_EL2);
+J273_CPREG_FUNCS(ACC_CTRR_CTL_EL2);
+J273_CPREG_FUNCS(ACC_CTRR_LOCK_EL2);
+J273_CPREG_FUNCS(ARM64_REG_CYC_CFG);
+J273_CPREG_FUNCS(ARM64_REG_CYC_OVRD);
+J273_CPREG_FUNCS(IPI_SR);
+J273_CPREG_FUNCS(UPMCR0);
+J273_CPREG_FUNCS(UPMPCM);
+#endif
+
+static const ARMCPRegInfo j273_cp_reginfo_kvm[] = {
+ // Apple-specific registers
+ J273_CPREG_DEF(ARM64_REG_EHID1, 3, 0, 15, 3, 1, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_EHID10, 3, 0, 15, 10, 1, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_EHID4, 3, 0, 15, 4, 1, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_HID11, 3, 0, 15, 13, 0, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_HID3, 3, 0, 15, 3, 0, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_HID4, 3, 0, 15, 4, 0, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_HID5, 3, 0, 15, 5, 0, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_HID7, 3, 0, 15, 7, 0, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_HID8, 3, 0, 15, 8, 0, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_LSU_ERR_STS, 3, 3, 15, 0, 0, PL1_RW),
+ J273_CPREG_DEF(PMC0, 3, 2, 15, 0, 0, PL1_RW),
+ J273_CPREG_DEF(PMC1, 3, 2, 15, 1, 0, PL1_RW),
+ J273_CPREG_DEF(PMCR1, 3, 1, 15, 1, 0, PL1_RW),
+ J273_CPREG_DEF(PMSR, 3, 1, 15, 13, 0, PL1_RW),
+ J273_CPREG_DEF(L2ACTLR_EL1, 3, 1, 15, 0, 0, PL1_RW),
+#ifdef ENABLE_EL2_REGS
+ J273_CPREG_DEF(ARM64_REG_MIGSTS_EL1, 3, 4, 15, 0, 4, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_KERNELKEYLO_EL1, 3, 4, 15, 1, 0, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_KERNELKEYHI_EL1, 3, 4, 15, 1, 1, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_VMSA_LOCK_EL1, 3, 4, 15, 1, 2, PL1_RW),
+ J273_CPREG_DEF(APRR_EL0, 3, 4, 15, 2, 0, PL1_RW),
+ J273_CPREG_DEF(APRR_EL1, 3, 4, 15, 2, 1, PL1_RW),
+ J273_CPREG_DEF(CTRR_LOCK, 3, 4, 15, 2, 2, PL1_RW),
+ J273_CPREG_DEF(CTRR_A_LWR_EL1, 3, 4, 15, 2, 3, PL1_RW),
+ J273_CPREG_DEF(CTRR_A_UPR_EL1, 3, 4, 15, 2, 4, PL1_RW),
+ J273_CPREG_DEF(CTRR_CTL_EL1, 3, 4, 15, 2, 5, PL1_RW),
+ J273_CPREG_DEF(APRR_MASK_EN_EL1, 3, 4, 15, 2, 6, PL1_RW),
+ J273_CPREG_DEF(APRR_MASK_EL0, 3, 4, 15, 2, 7, PL1_RW),
+ J273_CPREG_DEF(ACC_CTRR_A_LWR_EL2, 3, 4, 15, 11, 0, PL1_RW),
+ J273_CPREG_DEF(ACC_CTRR_A_UPR_EL2, 3, 4, 15, 11, 1, PL1_RW),
+ J273_CPREG_DEF(ACC_CTRR_CTL_EL2, 3, 4, 15, 11, 4, PL1_RW),
+ J273_CPREG_DEF(ACC_CTRR_LOCK_EL2, 3, 4, 15, 11, 5, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_CYC_CFG, 3, 5, 15, 4, 0, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_CYC_OVRD, 3, 5, 15, 5, 0, PL1_RW),
+ J273_CPREG_DEF(IPI_SR, 3, 5, 15, 1, 1, PL1_RW),
+ J273_CPREG_DEF(UPMCR0, 3, 7, 15, 0, 4, PL1_RW),
+ J273_CPREG_DEF(UPMPCM, 3, 7, 15, 5, 4, PL1_RW),
+#endif
+
+ // Aleph-specific registers for communicating with QEMU
+
+ // REG_QEMU_CALL:
+ { .cp = CP_REG_ARM64_SYSREG_CP, .name = "REG_QEMU_CALL",
+ .opc0 = 3, .opc1 = 3, .crn = 15, .crm = 15, .opc2 = 0,
+ .access = PL0_RW, .type = ARM_CP_IO, .state = ARM_CP_STATE_AA64,
+ .readfn = qemu_call_status,
+ .writefn = qemu_call },
+
+ REGINFO_SENTINEL,
+};
+
+// This is the same as the array for kvm, but without
+// the L2ACTLR_EL1, which is already defined in TCG.
+// Duplicating this list isn't a perfect solution,
+// but it's quick and reliable.
+static const ARMCPRegInfo j273_cp_reginfo_tcg[] = {
+ // Apple-specific registers
+ J273_CPREG_DEF(ARM64_REG_EHID1, 3, 0, 15, 3, 1, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_EHID10, 3, 0, 15, 10, 1, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_EHID4, 3, 0, 15, 4, 1, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_HID11, 3, 0, 15, 13, 0, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_HID3, 3, 0, 15, 3, 0, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_HID5, 3, 0, 15, 5, 0, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_HID4, 3, 0, 15, 4, 0, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_HID8, 3, 0, 15, 8, 0, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_HID7, 3, 0, 15, 7, 0, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_LSU_ERR_STS, 3, 3, 15, 0, 0, PL1_RW),
+ J273_CPREG_DEF(PMC0, 3, 2, 15, 0, 0, PL1_RW),
+ J273_CPREG_DEF(PMC1, 3, 2, 15, 1, 0, PL1_RW),
+ J273_CPREG_DEF(PMCR1, 3, 1, 15, 1, 0, PL1_RW),
+ J273_CPREG_DEF(PMSR, 3, 1, 15, 13, 0, PL1_RW),
+#ifdef ENABLE_EL2_REGS
+ J273_CPREG_DEF(ARM64_REG_MIGSTS_EL1, 3, 4, 15, 0, 4, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_KERNELKEYLO_EL1, 3, 4, 15, 1, 0, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_KERNELKEYHI_EL1, 3, 4, 15, 1, 1, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_VMSA_LOCK_EL1, 3, 4, 15, 1, 2, PL1_RW),
+ J273_CPREG_DEF(APRR_EL0, 3, 4, 15, 2, 0, PL1_RW),
+ J273_CPREG_DEF(APRR_EL1, 3, 4, 15, 2, 1, PL1_RW),
+ J273_CPREG_DEF(CTRR_LOCK, 3, 4, 15, 2, 2, PL1_RW),
+ J273_CPREG_DEF(CTRR_A_LWR_EL1, 3, 4, 15, 2, 3, PL1_RW),
+ J273_CPREG_DEF(CTRR_A_UPR_EL1, 3, 4, 15, 2, 4, PL1_RW),
+ J273_CPREG_DEF(CTRR_CTL_EL1, 3, 4, 15, 2, 5, PL1_RW),
+ J273_CPREG_DEF(APRR_MASK_EN_EL1, 3, 4, 15, 2, 6, PL1_RW),
+ J273_CPREG_DEF(APRR_MASK_EL0, 3, 4, 15, 2, 7, PL1_RW),
+ J273_CPREG_DEF(ACC_CTRR_A_LWR_EL2, 3, 4, 15, 11, 0, PL1_RW),
+ J273_CPREG_DEF(ACC_CTRR_A_UPR_EL2, 3, 4, 15, 11, 1, PL1_RW),
+ J273_CPREG_DEF(ACC_CTRR_CTL_EL2, 3, 4, 15, 11, 4, PL1_RW),
+ J273_CPREG_DEF(ACC_CTRR_LOCK_EL2, 3, 4, 15, 11, 5, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_CYC_CFG, 3, 5, 15, 4, 0, PL1_RW),
+ J273_CPREG_DEF(ARM64_REG_CYC_OVRD, 3, 5, 15, 5, 0, PL1_RW),
+ J273_CPREG_DEF(IPI_SR, 3, 5, 15, 1, 1, PL1_RW),
+ J273_CPREG_DEF(UPMCR0, 3, 7, 15, 0, 4, PL1_RW),
+ J273_CPREG_DEF(UPMPCM, 3, 7, 15, 5, 4, PL1_RW),
+#endif
+
+ // Aleph-specific registers for communicating with QEMU
+
+ // REG_QEMU_CALL:
+ { .cp = CP_REG_ARM64_SYSREG_CP, .name = "REG_QEMU_CALL",
+ .opc0 = 3, .opc1 = 3, .crn = 15, .crm = 15, .opc2 = 0,
+ .access = PL0_RW, .type = ARM_CP_IO, .state = ARM_CP_STATE_AA64,
+ .readfn = qemu_call_status,
+ .writefn = qemu_call },
+
+ REGINFO_SENTINEL,
+};
+
+static uint32_t g_nop_inst = NOP_INST;
+static uint32_t g_ret_inst = RET_INST;
+static uint32_t g_mov_w0_01_inst = MOV_W0_01_INST;
+static uint32_t g_compare_true_inst = CMP_X9_x9_INST;
+static uint32_t g_w7_zero_inst = W7_ZERO_INST;
+static uint32_t g_w10_zero_inst = W10_ZERO_INST;
+static uint32_t g_w23_zero_inst = W23_ZERO_INST;
+static uint32_t g_orr_x0_2_inst = ORR_X0_2_INST;
+static uint32_t g_set_cpacr_and_branch_inst[] = {
+ // 91400c21 add x1, x1, 3, lsl 12 # x1 = x1 + 0x3000
+ // d378dc21 lsl x1, x1, 8 # x1 = x1 * 0x100 (x1 = 0x300000)
+ // d5181041 msr cpacr_el1, x1 # cpacr_el1 = x1 (enable FP)
+ // d2800041 mov x1, #2
+ // d51cf081 mov apctl_el1, x1
+ // aa1f03e1 mov x1, xzr # x1 = 0
+ // 14000eb5 b 0x1fc0 # branch to regular start
+ 0x91400c21, 0xd378dc21, 0xd5181041,
+ 0xd2800041, 0xd51cf081, 0xaa1f03e1,
+ 0x14000eb5
+};
+static uint32_t g_bzero_branch_unconditionally_inst = 0x14000039;
+static uint32_t g_qemu_call = 0xd51bff1f;
+
+typedef struct darwin_patch {
+ uint64_t addr;
+ uint32_t *inst;
+ uint32_t len;
+} darwin_patch;
+
+typedef struct darwin_kernel_patch {
+ const char *darwin_str;
+ uint32_t num_patches;
+ struct darwin_patch patches[];
+} darwin_kernel_patch;
+
+// Patch is a single instruction
+#define DARWIN_PATCH(offset, instruction) \
+{ .addr = offset, .inst = &instruction, .len = sizeof(instruction) }
+
+// Patch is an array of instructions
+#define DARWIN_PATCH_A(offset, instruction) \
+{ .addr = offset, .inst = instruction, .len = sizeof(instruction) }
+
+struct darwin_kernel_patch darwin_patches_20A5364e = {
+ .darwin_str =
+ "Darwin Kernel Version 20.0.0: Sun Jun 14 21:36:36 PDT 2020; "
+ "root:Bridge_xnu-7090.111.5.2~1/RELEASE_ARM64_T8020",
+ .num_patches = 6, .patches = {
+ DARWIN_PATCH_A(0xfffffe00079f0580, g_set_cpacr_and_branch_inst), // initial branch
+ DARWIN_PATCH(0xfffffe00079e49fc, g_bzero_branch_unconditionally_inst), // bzero conditional branch
+ DARWIN_PATCH(0xfffffe0007f8330c, g_w23_zero_inst), // parse_machfile slide set instruction
+ DARWIN_PATCH(0xfffffe0007a5b47c, g_qemu_call), // notify kernel task pointer
+ DARWIN_PATCH(0xfffffe0008af5e3c, g_mov_w0_01_inst), // core trust check
+ DARWIN_PATCH(0xfffffe0007f83108, g_nop_inst), // load_machfile: disable IMGPF_NOJOP
+ }
+};
+
+struct darwin_kernel_patch darwin_patches_20B5012d = {
+ .darwin_str =
+ "Darwin Kernel Version 20.1.0: Sat Oct 24 21:20:41 PDT 2020; "
+ "root:xnu-7195.50.3.201.1~1/RELEASE_ARM64_T8020",
+ .num_patches = 6, .patches = {
+ DARWIN_PATCH_A(0xfffffe0007ab0580, g_set_cpacr_and_branch_inst), // initial branch
+ DARWIN_PATCH(0xfffffe0007aa49fc, g_bzero_branch_unconditionally_inst), // bzero conditional branch
+ DARWIN_PATCH(0xfffffe0008056168, g_w10_zero_inst), // parse_machfile slide set instruction
+ DARWIN_PATCH(0xfffffe0007b1f4d8, g_qemu_call), // notify kernel task pointer
+ DARWIN_PATCH(0xfffffe0008c96538, g_mov_w0_01_inst), // core trust check
+ DARWIN_PATCH(0xfffffe0008055f64, g_nop_inst), // load_machfile: disable IMGPF_NOJOP
+ }
+};
+
+struct darwin_kernel_patch darwin_patches_20C69 = {
+ .darwin_str =
+ "Darwin Kernel Version 20.2.0: Wed Dec 2 20:40:22 PST 2020; "
+ "root:xnu-7195.60.75~1/RELEASE_ARM64_T8020",
+ .num_patches = 5, .patches = {
+ DARWIN_PATCH_A(0xfffffe0007ac4580, g_set_cpacr_and_branch_inst), // initial branch
+ DARWIN_PATCH(0xfffffe0007ab8a3c, g_bzero_branch_unconditionally_inst), // bzero conditional branch
+ DARWIN_PATCH(0xfffffe000806b438, g_w10_zero_inst), // parse_machfile slide set instruction
+ DARWIN_PATCH(0xfffffe0008cb6538, g_mov_w0_01_inst), // core trust check
+ DARWIN_PATCH(0xfffffe000806b234, g_nop_inst), // load_machfile: disable IMGPF_NOJOP
+ }
+};
+
+struct darwin_kernel_patch *darwin_patches[] = {
+ &darwin_patches_20A5364e,
+ &darwin_patches_20B5012d,
+ &darwin_patches_20C69,
+};
+
+static void j273_add_cpregs(J273MachineState *nms)
+{
+ ARMCPU *cpu = nms->cpu;
+
+ nms->J273_CPREG_VAR_NAME(ARM64_REG_EHID1) = 0;
+ nms->J273_CPREG_VAR_NAME(ARM64_REG_EHID10) = 0;
+ nms->J273_CPREG_VAR_NAME(ARM64_REG_EHID4) = 0;
+ nms->J273_CPREG_VAR_NAME(ARM64_REG_HID11) = 0;
+ nms->J273_CPREG_VAR_NAME(ARM64_REG_HID3) = 0;
+ nms->J273_CPREG_VAR_NAME(ARM64_REG_HID5) = 0;
+ nms->J273_CPREG_VAR_NAME(ARM64_REG_HID8) = 0;
+ nms->J273_CPREG_VAR_NAME(ARM64_REG_HID7) = 0;
+ nms->J273_CPREG_VAR_NAME(ARM64_REG_LSU_ERR_STS) = 0;
+ nms->J273_CPREG_VAR_NAME(PMC0) = 0;
+ nms->J273_CPREG_VAR_NAME(PMC1) = 0;
+ nms->J273_CPREG_VAR_NAME(PMCR1) = 0;
+ nms->J273_CPREG_VAR_NAME(PMSR) = 0;
+ nms->J273_CPREG_VAR_NAME(L2ACTLR_EL1) = 0;
+#ifdef ENABLE_EL2_REGS
+ nms->J273_CPREG_VAR_NAME(ARM64_REG_MIGSTS_EL1) = 0;
+ nms->J273_CPREG_VAR_NAME(ARM64_REG_KERNELKEYLO_EL1) = 0;
+ nms->J273_CPREG_VAR_NAME(ARM64_REG_KERNELKEYHI_EL1) = 0;
+ nms->J273_CPREG_VAR_NAME(ARM64_REG_VMSA_LOCK_EL1) = 0;
+ nms->J273_CPREG_VAR_NAME(APRR_EL0) = 0;
+ nms->J273_CPREG_VAR_NAME(APRR_EL1) = 0;
+ nms->J273_CPREG_VAR_NAME(CTRR_LOCK) = 0;
+ nms->J273_CPREG_VAR_NAME(CTRR_A_LWR_EL1) = 0;
+ nms->J273_CPREG_VAR_NAME(CTRR_A_UPR_EL1) = 0;
+ nms->J273_CPREG_VAR_NAME(CTRR_CTL_EL1) = 0;
+ nms->J273_CPREG_VAR_NAME(APRR_MASK_EN_EL1) = 0;
+ nms->J273_CPREG_VAR_NAME(APRR_MASK_EL0) = 0;
+ nms->J273_CPREG_VAR_NAME(ACC_CTRR_A_LWR_EL2) = 0;
+ nms->J273_CPREG_VAR_NAME(ACC_CTRR_A_UPR_EL2) = 0;
+ nms->J273_CPREG_VAR_NAME(ACC_CTRR_CTL_EL2) = 0;
+ nms->J273_CPREG_VAR_NAME(ACC_CTRR_LOCK_EL2) = 0;
+ nms->J273_CPREG_VAR_NAME(ARM64_REG_CYC_CFG) = 0;
+ nms->J273_CPREG_VAR_NAME(ARM64_REG_CYC_OVRD) = 0;
+ nms->J273_CPREG_VAR_NAME(UPMCR0) = 0;
+ nms->J273_CPREG_VAR_NAME(UPMPCM) = 0;
+#endif
+
+ if (kvm_enabled()) {
+ define_arm_cp_regs_with_opaque(cpu, j273_cp_reginfo_kvm, nms);
+ } else {
+ define_arm_cp_regs_with_opaque(cpu, j273_cp_reginfo_tcg, nms);
+ }
+}
+
+static void j273_create_s3c_uart(const J273MachineState *nms, Chardev *chr)
+{
+ qemu_irq irq;
+ DeviceState *d;
+ SysBusDevice *s;
+ hwaddr base = nms->uart_mmio_pa;
+
+ //hack for now. create a device that is not used just to have a dummy
+ //unused interrupt
+ d = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
+ s = SYS_BUS_DEVICE(d);
+ sysbus_init_irq(s, &irq);
+ //pass a dummy irq as we don't need nor want interrupts for this UART
+ DeviceState *dev = exynos4210_uart_create(base, 256, 0, chr, irq);
+ if (!dev) {
+ abort();
+ }