you can generate verilog by use command :
sbt "test:runMain AES.testMain --target-dir generated/AES"
or you can set IDEA run configurations:
add sbt task -> fill Tasks with "test:runMain AES.testMain --target-dir generated/AES"
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AES128 encoder&decoder hardware implemented by chisel ,with 11 stages pipeline
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ddxoxpp/AES128-chisel3
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AES128 encoder&decoder hardware implemented by chisel ,with 11 stages pipeline
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