Assert GT_RSH for simd isn't TYP_LONG on xarch

src/coreclr/jit/gentree.cpp

@@ -19334,9 +19334,6 @@ GenTree* Compiler::gtNewSimdBinOpNode(genTreeOps op,
  case GT_RSH:
  case GT_RSZ:
  {
- assert(!varTypeIsByte(simdBaseType));
- assert((op != GT_RSH) || !varTypeIsUnsigned(simdBaseType));
-
  // float and double don't have actual instructions for shifting
  // so we'll just use the equivalent integer instruction instead.
 
@@ -19351,6 +19348,9 @@ GenTree* Compiler::gtNewSimdBinOpNode(genTreeOps op,
  simdBaseType = TYP_LONG;
  }
 
+ assert(!varTypeIsByte(simdBaseType));
+ assert((op != GT_RSH) || (!varTypeIsUnsigned(simdBaseType) && !varTypeIsLong(simdBaseType)));
+
  // "over shifting" is platform specific behavior. We will match the C# behavior
  // this requires we mask with (sizeof(T) * 8) - 1 which ensures the shift cannot
  // exceed the number of bits available in `T`. This is roughly equivalent to