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ARM64-SVE: Implement IF_SVE_DL_2A, IF_SVE_DZ_1A, IF_SVE_EA_1A #97068

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merged 6 commits into from
Jan 17, 2024
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ARM64-SVE: Implement IF_SVE_DL_2A, IF_SVE_DZ_1A, IF_SVE_EA_1A #97068

merged 6 commits into from
Jan 17, 2024

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amanasifkhalid
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Next batch of encodings from #94549.

JitDisasm output:

cntp    x0, p0.b, vlx2
cntp    x1, p1.b, vlx4
cntp    x2, p2.h, vlx2
cntp    x3, p3.h, vlx4
cntp    x4, p4.s, vlx2
cntp    x5, p5.s, vlx4
cntp    x6, p6.d, vlx2
cntp    x7, p7.d, vlx4
ptrue   p8.b
ptrue   p9.h
ptrue   p10.s
ptrue   p11.d
fmov    z0.h, #2.0000
fmov    z1.s, #1.0000
fmov    z2.d, #2.0000
fmov    z3.h, #-10.0000
fmov    z4.s, #-0.1250
fmov    z5.d, #31.0000

cstool output:

00822025  cntp  x0, pn0.b, vlx2
21862025  cntp  x1, pn1.b, vlx4
42826025  cntp  x2, pn2.h, vlx2
63866025  cntp  x3, pn3.h, vlx4
8482A025  cntp  x4, pn4.s, vlx2
A586A025  cntp  x5, pn5.s, vlx4
C682E025  cntp  x6, pn6.d, vlx2
E786E025  cntp  x7, pn7.d, vlx4
10782025  ptrue pn8.b
11786025  ptrue pn9.h
1278A025  ptrue pn0xA.s
1378E025  ptrue pn0xB.d
00C07925  fmov  z0.h, #2.00000000
01CEB925  fmov  z1.s, #1.00000000
02C0F925  fmov  z2.d, #2.00000000
83D47925  fmov  z3.h, #-10.00000000
04D8B925  fmov  z4.s, #-0.12500000
E5C7F925  fmov  z5.d, #31.00000000

Note that fmov is an alias for fdup, which is why we don't see the latter in the outputs. Aside from the differences in printing the predicate register numbers, the outputs look the same. cc @dotnet/arm64-contrib.

@dotnet-issue-labeler dotnet-issue-labeler bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jan 17, 2024
@ghost ghost assigned amanasifkhalid Jan 17, 2024
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ghost commented Jan 17, 2024

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

Issue Details

Next batch of encodings from #94549.

JitDisasm output:

cntp    x0, p0.b, vlx2
cntp    x1, p1.b, vlx4
cntp    x2, p2.h, vlx2
cntp    x3, p3.h, vlx4
cntp    x4, p4.s, vlx2
cntp    x5, p5.s, vlx4
cntp    x6, p6.d, vlx2
cntp    x7, p7.d, vlx4
ptrue   p8.b
ptrue   p9.h
ptrue   p10.s
ptrue   p11.d
fmov    z0.h, #2.0000
fmov    z1.s, #1.0000
fmov    z2.d, #2.0000
fmov    z3.h, #-10.0000
fmov    z4.s, #-0.1250
fmov    z5.d, #31.0000

cstool output:

00822025  cntp  x0, pn0.b, vlx2
21862025  cntp  x1, pn1.b, vlx4
42826025  cntp  x2, pn2.h, vlx2
63866025  cntp  x3, pn3.h, vlx4
8482A025  cntp  x4, pn4.s, vlx2
A586A025  cntp  x5, pn5.s, vlx4
C682E025  cntp  x6, pn6.d, vlx2
E786E025  cntp  x7, pn7.d, vlx4
10782025  ptrue pn8.b
11786025  ptrue pn9.h
1278A025  ptrue pn0xA.s
1378E025  ptrue pn0xB.d
00C07925  fmov  z0.h, #2.00000000
01CEB925  fmov  z1.s, #1.00000000
02C0F925  fmov  z2.d, #2.00000000
83D47925  fmov  z3.h, #-10.00000000
04D8B925  fmov  z4.s, #-0.12500000
E5C7F925  fmov  z5.d, #31.00000000

Note that fmov is an alias for fdup, which is why we don't see the latter in the outputs. Aside from the differences in printing the predicate register numbers, the outputs look the same. cc @dotnet/arm64-contrib.

Author: amanasifkhalid
Assignees: -
Labels:

area-CodeGen-coreclr
Milestone: -

@amanasifkhalid amanasifkhalid added arm-sve Work related to arm64 SVE/SVE2 support area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI and removed area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI labels Jan 17, 2024
@ghost
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ghost commented Jan 17, 2024

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

Issue Details

Next batch of encodings from #94549.

JitDisasm output:

cntp    x0, p0.b, vlx2
cntp    x1, p1.b, vlx4
cntp    x2, p2.h, vlx2
cntp    x3, p3.h, vlx4
cntp    x4, p4.s, vlx2
cntp    x5, p5.s, vlx4
cntp    x6, p6.d, vlx2
cntp    x7, p7.d, vlx4
ptrue   p8.b
ptrue   p9.h
ptrue   p10.s
ptrue   p11.d
fmov    z0.h, #2.0000
fmov    z1.s, #1.0000
fmov    z2.d, #2.0000
fmov    z3.h, #-10.0000
fmov    z4.s, #-0.1250
fmov    z5.d, #31.0000

cstool output:

00822025  cntp  x0, pn0.b, vlx2
21862025  cntp  x1, pn1.b, vlx4
42826025  cntp  x2, pn2.h, vlx2
63866025  cntp  x3, pn3.h, vlx4
8482A025  cntp  x4, pn4.s, vlx2
A586A025  cntp  x5, pn5.s, vlx4
C682E025  cntp  x6, pn6.d, vlx2
E786E025  cntp  x7, pn7.d, vlx4
10782025  ptrue pn8.b
11786025  ptrue pn9.h
1278A025  ptrue pn0xA.s
1378E025  ptrue pn0xB.d
00C07925  fmov  z0.h, #2.00000000
01CEB925  fmov  z1.s, #1.00000000
02C0F925  fmov  z2.d, #2.00000000
83D47925  fmov  z3.h, #-10.00000000
04D8B925  fmov  z4.s, #-0.12500000
E5C7F925  fmov  z5.d, #31.00000000

Note that fmov is an alias for fdup, which is why we don't see the latter in the outputs. Aside from the differences in printing the predicate register numbers, the outputs look the same. cc @dotnet/arm64-contrib.

Author: amanasifkhalid
Assignees: amanasifkhalid
Labels:

area-CodeGen-coreclr, arch-arm64-sve
Milestone: -

@amanasifkhalid amanasifkhalid mentioned this pull request Jan 17, 2024
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a74nh
a74nh approved these changes Jan 17, 2024
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Otherwise, LGTM

src/coreclr/jit/emitarm64.cpp Outdated
assert(isValidGeneralDatasize(id->idOpSize())); // X
case IF_SVE_DL_2A: // ........xx...... .....l.NNNNddddd -- SVE predicate count (predicate-as-counter)
assert(id->idOpSize() == EA_8BYTE);
// assert(isValidVectorLength()); // l
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Commented assert?

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Thanks for catching that; removed.

@build-analysis build-analysis bot mentioned this pull request Jan 17, 2024
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kunalspathak
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LGTM. Thanks!

@amanasifkhalid amanasifkhalid merged commit 05fe3e0 into dotnet:main Jan 17, 2024
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@amanasifkhalid amanasifkhalid deleted the if-sve-dl-2a branch January 17, 2024 15:50
@kunalspathak kunalspathak mentioned this pull request Jan 18, 2024
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tmds pushed a commit to tmds/runtime that referenced this pull request Jan 23, 2024
@amanasifkhalid @tmds
JIT ARM64-SVE: Implement IF_SVE_DL_2A, IF_SVE_DZ_1A, IF_SVE_EA_1A (do…
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…tnet#97068)
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area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI arm-sve Work related to arm64 SVE/SVE2 support
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