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Gated counter and toggle gate #111

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Gated counter and toggle gate #111

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mkorbel1
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Description & Motivation

Introduces two new components:

  • A ToggleGate which helps avoid toggles on combinational hardware when it's not necessary
  • A GatedCounter which partitions the flops into two groups and clock gates them independently as needed

Related Issue(s)

Found intel/rohd#516 during development of random tests on the GatedCounter

Testing

Lots of unit tests and random tests

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

Yes, needs API docs and component docs

@mkorbel1
Initial implementation of clock gating
689694b
@mkorbel1
tiny tweaks
7721fbe
@mkorbel1
Merge branch 'main' of https:/intel/rohd-hcl into clk_gate
f649e60
@mkorbel1
improve testing
a0a2685
@mkorbel1
updating documentation on clock gating
edce116
@mkorbel1
fixing tests, adding docs
d9b138c
@mkorbel1
Merge branch 'main' of https:/intel/rohd-hcl into clk_gate
897f75a
@mkorbel1
fix tests
4d384a2
@mkorbel1
add docs for clock gating
254c26b
@mkorbel1
fix formatting
589f49a
@mkorbel1
Clean up clock gating, fix latched enable, improve doc and examples
7c6d62d
@mkorbel1
fix required reset
69b5eee
@mkorbel1
initial work on gated counter
8734217
@mkorbel1
get test actually passing
db2ec9e
@mkorbel1
support decrement driven enables on upper
b1c99d1
@mkorbel1
add overflow support
4b28e98
@mkorbel1
handle max
bb73b9b
@mkorbel1
initial impl for underflow check
fb94e8c
@mkorbel1
refactoring sum testing for reuse
2a087d2
@mkorbel1
initial randomized counter test working
909179d
@mkorbel1
connect rest of cfg to counter and checker
50f07ed
@mkorbel1
test both kinds of counters randomly
f28a3db
@mkorbel1
random tests run, but dont pass
5933e57
@mkorbel1
basic gated counter gates somewhat reasonably
1d4db3b
@mkorbel1
move clock gating inside the toggle gate
80bbf1c
@mkorbel1
a couple random gated counters work
0a0c96e
@mkorbel1
do a better job turning off clocks for saturation cases
bc52329
@mkorbel1
upper bit incr only dont enable lower test
81c5175
@mkorbel1
disabling turns off whole counter
f6a0205
@mkorbel1
fix consistency for random tests
20dbc41
@mkorbel1
some range fixes
edad5ec
@mkorbel1
fix unstable reset value case
21a3b24
@mkorbel1
debugging errors
188a122
@mkorbel1
Merge branch 'main' of https:/intel/rohd-hcl into gated_c…
c9be886 
…ounter
@mkorbel1
down counter by 1 tests passing
4966c74
@mkorbel1
fix may underflow calculation
a842006
@mkorbel1
fix underflow issues
b3180e4
@mkorbel1
handle big increments
5f7f62f
@mkorbel1
fix another incr ungating issue
e703abc
@mkorbel1
fix some underflow issues
0339bcf
@mkorbel1
fix overflow issue
7f97a94
@mkorbel1
fix overly ambitious incr guard
3bd1838
@mkorbel1
fix over enthusiastic gating
e77b338
@mkorbel1
fix decr danger bug
fd68e99
@mkorbel1
variable amount gating on bigger counter testing
f8d5047
@mkorbel1
toggle gate test
0e9675b
@mkorbel1
toggle gate tests done
6d273e1
@mkorbel1
test with multiple intfs
dcceff8
@mkorbel1
cleanup
14596e6
@mkorbel1
test with clock gating disabled
40268a0
@mkorbel1
doc updates
c044dc6
@mkorbel1
add test for all gated together
d6bd34d
@mkorbel1
Merge branch 'main' of https:/intel/rohd-hcl into gated_c…
b44fc61 
…ounter
@mkorbel1
more docs updates
2825a73
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@desmonddak desmonddak Awaiting requested review from desmonddak

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@mkorbel1