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asap7: update to asap7 v28 + adding super low threshold option
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Fixes multiple issues: ucb-bar/hammer#624 (comment)

> ### There are some fixes in the newer version:
> 1. ICG lib with "clock gating function and state table" has been fixed. [ICG cells throw an error in library compiler The-OpenROAD-Project/asap7#3](The-OpenROAD-Project/asap7#3)
>    Edit: ICG*DC* cells with incorrect width has been fixed. [ICG*DC* cells have incorrect width The-OpenROAD-Project/asap7#12](The-OpenROAD-Project/asap7#12)
> 2. Large ASNYC FF delay has been fixed. [Wrong timing values (1e31) for ASYNC_DFFHx1_ASAP7_75t_R in the sc7p5t_SEQ_RVT_SS_nldm_201020 library The-OpenROAD-Project/asap7#9](The-OpenROAD-Project/asap7#9)
> 3. Multi-VT GDS files missing has been fixed.
>
> ### One known issue
> 1. Missing prefix in Verilog module name. ["AM" in the prefix of the module name "SRAM" is missing. The-OpenROAD-Project/asap7#33](https:/The-OpenROAD-Project/asap7/pull/33)

Signed-off-by: Jannis Schönleber <[email protected]>
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joennlae committed Sep 8, 2022
1 parent bc0cb18 commit 9a3c144

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