visualhl.ini

[visual_elite_inifile] 
[libraries] 
[conversion-type] 
reg : std_logic 
supply0 : std_logic 
supply1 : std_logic 
tri : std_logic 
tri0 : std_logic 
tri1 : std_logic 
triand : std_logic 
trior : std_logic 
wand : std_logic 
wire : std_logic 
wor : std_logic 
[vhd_ent_init_text] 
entity  %unit_name%  is 
end; 
[vhd_arch_init_text] 
architecture  %arch_name%  of  %unit_name%  is 
begin 
end; 
[vhd_pack_decl_init_text] 
package %unit_name%  is 
end; 
[vhd_pack_body_init_text] 
package body  %unit_name%  is 
end; 
[vhd_conf_decl_init_text] 
configuration %unit_name% of %conf_entity_name% is 
	for %conf_arch_name% 
	end for; 
end; 
[ver_module_init_text] 
module %unit_name% 
endmodule 
[ver_prim_init_text] 
primitive %unit_name% 
	table 
	endtable 
endprimitive 
[sc_h_init_text] 
SC_MODULE(%unit_name%) 
{ 
public: 
SC_CTOR(%unit_name%); 
}; // end_of_class 
[sc_c_init_text] 
%unit_name%::%unit_name%(sc_module_name name) 
:sc_module(name) 
{ 
} 
[browser_lines] 
Logical-name Black 
Physical-name Black 
Language Black 
Permission Black 
Modification-date Black 
Version Black 
Checked-out-by Black 
Page-number Black 
[browser_line1] 
Logical-name 
Physical-name 
Language 
[window_pos] 
1 
m 1 1 0 1507 
[options] 
use_project_manager_tool 1 
new_unit_lang VHDL 
nonstatic_range_direction_is_to True 
user_defined_menu_dir user_block_diagram_menu 
saveini True 
usereditor_useasdef False 
xemacs_default True 
xemacs_fr_repr True 
xemacs_close_on_ve_exit False 
design_pad_default False 
vcs_update_mode False 
vcsi_update_mode False 
xl_load_pli False 
synthesys_defaults_autoload True 
synthesys_defaults_autoextract False 
synthesys_defaults_run_synth_bg False 
synth_rmt_config_remote False 
editor_opt_save_name False 
editor_opt_auto_route True 
editor_opt_connector_mode_c nnmode 
editor_opt_connector_mode_ver iomode 
editor_opt_connector_mode_vhd iomode 
editor_opt_buffer_mode inout 
editor_opt_del_open_ports False 
editor_opt_encode_vhd Enumeration 
editor_opt_encode_ver Random 
editor_opt_flat True 
editor_opt_cur_sig enumeration 
editor_opt_signal_display_type 'd' 
editor_opt_grid 10 
editor_opt_create_meta_file_on_save False 
editor_opt_open_win_in_full_zoom False 
editor_opt_ttf_vhd If 
editor_opt_ttf_ver If 
editor_opt_undo 10 
editor_opt_zoom 200 
editor_opt_multi_zoom True 
editor_opt_side_pin_vis True 
editor_opt_show_def_arch True 
editor_opt_show_conf True 
editor_opt_retain_pins True 
editor_opt_update_uds False 
editor_opt_use_rule_checks True 
editor_opt_control_for_dand True 
editor_opt_support_mcl False 
editor_opt_sm_machine Synchronous 
editor_opt_rst_mode Synchronous 
editor_opt_active_rst High 
editor_opt_clk_polarity High 
editor_opt_exit_connect Exit-On-First 
editor_opt_sm_style Free-Style 
editor_opt_tran_pross Synchronous 
editor_opt_state_select_vhd Case 
editor_opt_state_select_ver Case 
editor_opt_tran_select_vhd If 
editor_opt_tran_select_ver If 
editor_opt_def_assign_at_begin False 
editor_opt_header_tx_flag False 
editor_opt_header_tx_ent_flag True 
editor_opt_header_tx_arc_flag False 
editor_opt_header_tx_pdecl_flag True 
editor_opt_header_tx_pbody_flag False 
editor_opt_header_gr_flag False 
editor_opt_fc_clk_polarity High 
editor_opt_fc_always_block True 
editor_opt_fc_encode_vhd Enumeration 
editor_opt_fc_encode_ver Random 
editor_opt_fc_blocking_assignment False 
editor_opt_fc_current_signal_type std_logic_vector 
editor_opt_tt_sync_mode Synchronous 
editor_opt_tt_rst_sync_mode Synchronous 
editor_opt_tt_rst_polarity High 
editor_opt_tt_clk_polarity High 
editor_opt_tt_block_assign False 
default_unit_type as-is 
default_init_unit_type vhdl87 
default_unit_c_type SystemC 
cmgn_comp_c_systemc 2.1.v1 
cmgn_comp_c_gcc 3.4 
min_win_num False 
auto_panning False 
ve_vers_warn True 
macro_arith_operate_by_ieee True 
macro_design_mapping_hierarchy True 
blk_globvis_blk_prefix b 
blk_globvis_blk_name True 
blk_globvis_blk_gen False 
blk_globvis_blk_act False 
blk_globvis_blk_prior False 
blk_globvis_sig_prefix s 
blk_globvis_sig_name True 
blk_globvis_sig_act True 
blk_globvis_chann_prefix ch 
blk_globvis_sock_prefix sc 
blk_globvis_exp_prefix ex 
blk_globvis_pin_prefix XXX 
blk_globvis_pin_name False 
blk_globvis_pin_act False 
blk_globvis_comp_prefix c 
blk_globvis_comp_name True 
blk_globvis_comp_gen False 
blk_globvis_tap_prefix T 
blk_globvis_tap_name False 
blk_globvis_tap_act False 
sm_globvis_state_prefix S 
sm_globvis_state_name True 
sm_globvis_state_act True 
sm_globvis_tran_prefix T 
sm_globvis_tran_name False 
sm_globvis_tran_guard True 
sm_globvis_tran_prior True 
sm_globvis_tran_act True 
sm_globvis_conn_prefix G 
sm_globvis_conn_name False 
sm_globvis_pageconn_name False 
fl_globvis_start_prefix Start 
fl_globvis_start_name True 
fl_globvis_start_act False 
fl_globvis_act_prefix A 
fl_globvis_act_name False 
fl_globvis_act_act True 
fl_globvis_cond_prefix D 
fl_globvis_cond_name False 
fl_globvis_cond_act True 
fl_globvis_wait_prefix W 
fl_globvis_wait_name False 
fl_globvis_wait_act True 
fl_globvis_loop_prefix L 
fl_globvis_loop_name False 
fl_globvis_loop_act True 
fl_globvis_end_loop_prefix E 
fl_globvis_end_loop_name False 
fl_globvis_end_loop_act True 
fl_globvis_case_prefix C 
fl_globvis_case_name False 
fl_globvis_case_act True 
fl_globvis_case_choices False 
fl_globvis_end_case_prefix EC 
fl_globvis_end_case_name False 
fl_globvis_end_case_act True 
fl_globvis_end_case_choices False 
fl_globvis_fstate_prefix S 
fl_globvis_fstate_name True 
fl_globvis_fstate_act True 
fl_globvis_pageconn_name False 
fl_globvis_globconn_prefix G 
fl_globvis_globconn_name False 
fl_globvis_globconn_prior True 
fl_globvis_globconn_act True 
page_info_width 11000 
page_info_height 11000 
page_info_type vhdstd 
page_info_orient portr 
page_info_units inch 
template_info_open True 
evcinfo_save_path /scratch/sw/vista/vista_3.5.0/VisualElite/userenv/Linux2.6/evc/rcs/ 
evcinfo_etype RCS 
evcinfo_script_extension .sh 
evcinfo_command_line /bin/sh 
evcinfo_modify_checkin_unit False 
evcinfo_generate_checkin_unit False 
evcinfo_delete_units_vcl False 
evcinfo_check_units_vcl False 
compiler_use_ieee False 
compiler_verify_synth True 
compiler_incremental_comp True 
compiler_runtime_checks partchk 
compiler_update_ext_unit False 
compiler_optimized True 
compiler_static_checks False 
compiler_style_checks True 
compiler_redundent_assign False 
compiler_uncomplete_cond False 
compiler_overlap_cond False 
compiler_invoke_extanalyzer True 
compiler_check_link_design False 
compiler_multipled_river False 
compiler_unread False 
compiler_include_sensitivity False 
compiler_undriven False 
compiler_def_tt_branch False 
compiler_def_sig_values False 
compiler_cell_connectivity False 
compiler_implicit_includes False 
compiler_invoke_comp_file True 
target_verify True 
target_define_sys SC_SYNTHESIS 
target_hdl_type As_Is 
target_hdl_synth yes 
target_hdl_vendor_vhd_vhd Synopsis 
target_hdl_vendor_ver_vhd Synopsis 
target_hdl_vendor_vhd_ver Synopsis 
target_hdl_vendor_ver_ver Synopsis 
target_hdl_vendor_sys_ver Synopsis 
target_hdl_vendor_sys_vhd Synopsis 
target_hdl_vendor_sys_sys CoCentric 
target_hdl_sched_mode cycle-fixed 
target_macro_map False 
-pragma_syn synopsys translate_off -vhd_on synopsys translate_on -ver_off synopsys translate_off -ver_on synopsys translate_on 
-pragma_generic synthesis translate_off -vhd_on synthesis translate_on -ver_off synthesis translate_off -ver_on synthesis translate_on 
-pragma_exemp exemplar translate_off -vhd_on exemplar translate_on -ver_off exemplar translate_off -ver_on exemplar translate_on 
-pragma_quick quickturn translate_off -vhd_on quickturn translate_on -ver_off quickturn translate_off -ver_on quickturn translate_on 
-pragma_synov $ synthesis_compile_off -vhd_on $ synthesis_compile_on -ver_off -ver_on 
-pragma_synpl synthesis translate_off -vhd_on synthesis translate_on -ver_off synthesis translate_off -ver_on synthesis translate_on 
-pragma_leo exemplar translate_off -vhd_on exemplar translate_on -ver_off exemplar translate_off -ver_on exemplar translate_on 
-pragma_fpga synopsys translate_off -vhd_on synopsys translate_on -ver_off synopsys translate_off -ver_on synopsys translate_on 
-pragma_build ambit synthesis off -vhd_on ambit synthesis on -ver_off ambit synthesis off -ver_on ambit synthesis on 
export_option single 
export_seprt False 
export_auto_export False 
export_use_work False 
export_attach_gl_header False 
export_split_stim False 
export_file_exp True 
export_dir_exp True 
export_seprt_systemc False 
option_to_save_object True 
naming_save_object_as <unit-name>_<lang-suffix> 
naming_save_all_arch True 
naming_save_all_arch_as <unit-name> 
style_proc_type_vhd never 
style_proc_type_ver never 
style_add_case False 
style_scalar_val 0 
style_vector_val 0 
style_att_pkg nopkg 
style_att_systemc_pkg nopkg 
style_gen_def_systemc True 
style_gen_comm_unit_part False 
style_att_dir dirv 
style_struct nostruct 
style_conf_spec noconf 
style_gen_entity genet 
style_lib_name False 
use_array False 
for_gen_vect False 

style_add_use_work_all True 
style_read_stim_add_arch True 
style_fail_safe_sm False 
style_replace_by_work False 
style_error_style True 
style_state_variab nostate_name 
style_block_assign nonblocking 
style_use_arith_pkg IEEE.STD_LOGIC_ARITH 
style_conf_decl noconf_decl 
style_clock_sync clk_sync_clk_event 
style_gen_map_assoc Position 
style_free_text freetext_slash_slash 
style_free_text_systemc freetext_slash_slash 
style_output_style synchronous 
compiler_systemc_options -g -Wno-deprecated -DVISUALSC 
if_seamless False 
style_trace_on notrace 
style_trace_on_systemc notrace 
generate_cpp_object False 
cause_effect_systemc False 
style_ModelSim_GUI ModelSimGui-Off 
style_ModelSim_InvSep False 

style_NCSim_GUI NCSimGui-Off 
style_Riviera_Cause Riviera-Cause-Off 
format_allign False 
macro_sized_value_ver False 
macro_decimal_value_ver False 
macro_block_assign_ver False 
ds_run_gui True 
format_sort_ports False 
format_ind 2 
format_max_line 80 
format_case noshift 
format_ver_case upshift 
format_wire_in False 
format_procname_sameline False 
format_wire_out False 
format_port_line False 
format_port_attach False 
format_copy_text True 
style_checks_scheme_check False 
style_checks_include_nm True 
style_checks_include_up True 
style_checks_include_lw True 
style_checks_include_us True 
style_checks_begin_us True 
style_checks_begin_up True 
style_checks_begin_lw True 
style_checks_begin_nm True 
style_checks_length False 
style_checks_length_min 3 
style_checks_length_max 8 
style_checks_check_illegal False 
style_checks_check_perform False 
attach_glo_stn True 
attach_glo_usr False 
attach_unit_stn True 
attach_unit_usr False 
global_user_ontop False 
unit_user_ontop False 
import_comp_after_imp inocomp 
import_attach_global_pkgs impat 
import_auto_import_include aimp 
v2b_40_use_comp False 
v2b_40_multi_page 2pages 
v2b_40_width 11000 
v2b_40_height 11000 
v2b_40_open_all o-one 
v2b_40_one_assign_blk 1-as-blk 
v2b_40_auto_directive False 
v2b_40_page_ndx 22 
v2b_40_orient_type portr 
v2b_40_units_type inch 
v2b_40_tree_sm True 
v2b_40_tree_fc True 
v2b_40_tree_asm True 
v2b_40_tree_afsm False 
v2b_40_tree_cell True 
v2b_40_tree_topology 1 
def_signal_type_vhd bit 
def_signal_type_ver wire 
def_signal_type_sysc bool 
vendor_system_vhd visualelite 
vendor_system_ver vcs 
vendor_system_sysc systemc 
simulation_name_nc_vhdl_com ncvhdl 
simulation_name_nc_vhdl_elb ncelab 
simulation_name_nc_vhdl_sim ncsim 
simulation_name_nc_ver_com ncvlog 
external_simulator_remote_exec False 
external_simulator_remote_exec_nc False 
external_simulator_remote_exec_vcs True 
external_simulator_remote_exec_vcsi True 
def_vector_type_vhd bit_vector 
def_vector_type_ver wire 
def_sysc_array 0 
signals_display_gap 12 
signals_display_height 21 
signals_display_text_font 14 
assertion_break_support_cause True 
assertion_break_msg none 
assertion_break_display failure 
def_time_unit ns 
def_c_time_unit ns 
browser_status True 
browser_full_qualifier False 
browser_time_stamp False 
browser_side_objects True 
browser_expandable_mark True 
browser_access_rights False 
browser_checked_out False 
browser_show_pages True 
browser_show_language True 
browser_lib_sort_type 0 
browser_project_sort_type 2 
browser_default_for_view_mode_is_new True 
browser_default_for_int_project_manager False 
browser_default_for_design_view_mode False 
font_names_red 0 
font_names_green 0 
font_names_blue 160 
font_names_size 2 
font_names_family 5 
font_names_italic 0 
font_names_bold 0 
font_names_fixed 0 
font_names_char_set 0 
font_free_text_red 0 
font_free_text_green 0 
font_free_text_blue 0 
font_free_text_size 2 
font_free_text_family 5 
font_free_text_italic 0 
font_free_text_bold 0 
font_free_text_fixed 0 
font_free_text_char_set 0 
font_text_editor_red 0 
font_text_editor_green 0 
font_text_editor_blue 0 
font_text_editor_size 3 
font_text_editor_family 2 
font_text_editor_italic 0 
font_text_editor_bold 0 
font_text_editor_fixed 1 
font_text_editor_char_set 0 
auto_save_time 60000 
auto_save_enable 0 
printer_orient portrait 
printer_paper_combo UsLetter 
printer_out_type Printer 
printer_pfile_name VisualHDL.ps 
printer_printer_name ps 
printer_dev_type PostScript 
printer_kf_line_width 0.5 
printer_gray_value 5 
printer_copies 1 
printer_color 0 
analysis_equiv_states equiv_st 
analysis_terminal_states term_st 
analysis_unreach_states unreach_st 
analysis_mem_outputs mem 
analysis_equiv_signals equiv_sig 
analysis_unexecute_branches unexec 
analysis_unspecified_loops unspec 
analysis_unused_inputs unused 
analysis_constant_outputs const 
analysis_signal_condition sig_cond 
analysis_terminal_loops term_loop 
edif2vis_lang VHDL 
edif2vis_unit Block diagram 
edif2vis_grid 10 
vhdl_compiler_options gcc  -c -O -I. -fPIC 
cell_process_type SC_THREAD 
sc_template_macro_unit_name False 
[VirtualPrototypeOptions] 
3 
0 
@targetPath /scratch/mbradley/vista/esl_to_rtl_flow/mb_vista_predictor_v0.2/vista_sharpstone_v1.0/vista_design 
@targetName <library-name>.<unit-name> 
@compilerName gcc 
@platformOptions_end 
1 
@targetPath /scratch/mbradley/vista/esl_to_rtl_flow/mb_vista_predictor_v0.2/vista_sharpstone_v1.0/vista_design 
@targetName <library-name>.<unit-name> 
@compilerName gcc 
@platformOptions_end 
2 
@targetPath /scratch/mbradley/vista/esl_to_rtl_flow/mb_vista_predictor_v0.2/vista_sharpstone_v1.0/vista_design 
@targetName <library-name>.<unit-name> 
@compilerName Microsoft Visual C++ 
@platformOptions_end 
3 
@targetPath /scratch/mbradley/vista/esl_to_rtl_flow/mb_vista_predictor_v0.2/vista_sharpstone_v1.0/vista_design 
@targetName <library-name>.<unit-name> 
@compilerName gcc 
@platformOptions_end 
4 
@targetPath /scratch/mbradley/vista/esl_to_rtl_flow/mb_vista_predictor_v0.2/vista_sharpstone_v1.0/vista_design 
@targetName <library-name>.<unit-name> 
@compilerName gcc 
@platformOptions_end 
[gidel_options] 
syn_tool_hw_acceleration Synplify 
chip_hw_acceleration APEX20KE:EP20K600E 
[colors_select]
GnrlFill Light Yellow2
AttrFill Light Green1
BrkFill Red
RchFill Rose1
UnrchFill Light Purple
PathFill Rose1
CurrFill Dark Cyan
CauseFill Light Green1
CommentGraphFill Gray94
SynthesisOffFill Gray75
GnrlLine Magenta
AttrLine Blue
BrkLine Red
RchLine Rose1
UnrchLine Light Purple
PathLine Rose1
CurrLine Dark Cyan
CauseLine Light Green1
CommentGraphLine Gray94
SynthesisOffLine Gray75
[colors_block]
BDblock Pale Blue2
BDFlatblock Pale Blue2
BDcomp Pale Blue2
BDMacro Pale Blue2
BDtap Pale Blue2
BDpinEl Black
BDhc Light Green
BDblock_L Black
BDFlatblock_L Black
BDcomp_L Black
BDMacro_l Black
BDtap_L Black
TypeSignal Black
BDhc_L Black
[colors_state]
SMstate Pale Blue2
SMstate_A Black
SMtran Black
[colors_flow]
FCstart Pale Blue2
FCstop Pale Blue2
FCaction Pale Blue2
FCstate Pale Blue2
FCcond Pale Blue2
FCwait Pale Blue2
FCcase Pale Blue2
FCloop Pale Blue2
FCstart_L Black
FCstop_L Black
FCaction_L Black
FCstate_L Black
FCcond_L Black
FCwait_L Black
FCcase_L Black
FCloop_L Black
FCarrow_L Black
[colors_symbol]
Symbol Pale Blue2
Symbol_L Black
[internal_editor_options]
4 1 1 1