[sival] Update test plan with passing silicon tests

Updates AES and KMAC with passing silicon tests. Signed-off-by: Miguel Osorio <[email protected]> (cherry picked from commit d4d944d)
lowRISC · Mar 7, 2024 · 27c5e5d · 27c5e5d
1 parent 62abbba
commit 27c5e5d
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Showing 2 changed files with 4 additions and 2 deletions.
diff --git a/hw/top_earlgrey/data/ip/chip_aes_testplan.hjson b/hw/top_earlgrey/data/ip/chip_aes_testplan.hjson
@@ -132,6 +132,7 @@
  si_stage: SV3
  lc_states: ["PROD"]
  tests: ["chip_sw_aes_entropy"]
+ bazel: ["//sw/device/tests:aes_entropy_test"]
  }
  {
  name: chip_sw_aes_prng_reseed
@@ -227,6 +228,7 @@
  si_stage: SV3
  lc_states: ["PROD"]
  tests: ["chip_sw_aes_idle"]
+ bazel: ["//sw/device/tests:aes_idle_test"]
  }
  {
  name: chip_sw_aes_sideload

diff --git a/hw/top_earlgrey/data/ip/chip_kmac_testplan.hjson b/hw/top_earlgrey/data/ip/chip_kmac_testplan.hjson
@@ -112,9 +112,9 @@
  '''
  stage: V2
  si_stage: SV3
- lc_states: ["TEST_UNLOCKED", "DEV", "PROD", "PROD_END", "RMA"]
+ lc_states: ["PROD"]
  tests: ["chip_sw_kmac_idle"]
- bazel: []
+ bazel: ["//sw/device/tests:kmac_idle_test"]
  }
  {
  name: chip_sw_kmac_sha3_stress