[clkmgr] Insert hookup buffers on all root clock inputs

This inserts clock buffers for OCC hookup (during DFT insertion) on all root clock inputs. Note that the clock dividers do not use the buffered root clocks on purpose, since they will have their own OCC inserted on their internal u_clk_div_buf hookup point. Signed-off-by: Michael Schaffner <[email protected]>
lowRISC · Jan 31, 2024 · 7c97490 · 7c97490
1 parent 52b6474
commit 7c97490
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Showing 3 changed files with 123 additions and 79 deletions.
diff --git a/hw/ip/clkmgr/data/clkmgr.sv.tpl b/hw/ip/clkmgr/data/clkmgr.sv.tpl
@@ -110,6 +110,17 @@ from topgen.lib import Name
  import prim_mubi_pkg::mubi4_test_true_loose;
  import prim_mubi_pkg::mubi4_test_false_strict;
 
+ // Hookup point for OCC's on root clocks.
+% for src in clocks.srcs.values():
+ logic clk_${src.name};
+ prim_clock_buf #(
+ .NoFpgaBuf(1'b1)
+ ) u_clk_${src.name}_buf (
+ .clk_i(clk_${src.name}_i),
+ .clk_o(clk_${src.name})
+ );
+% endfor
+
  ////////////////////////////////////////////////////
  // External step down request
  ////////////////////////////////////////////////////
@@ -121,7 +132,7 @@ from topgen.lib import Name
  .StabilityCheck(1),
  .ResetValue(MuBi4False)
  ) u_${src_name}_step_down_req_sync (
- .clk_i(clk_${src_name}_i),
+ .clk_i(clk_${src_name}),
  .rst_ni(rst_${src_name}_ni),
  .mubi_i(div_step_down_req_i),
  .mubi_o({${src_name}_step_down_req})
@@ -139,7 +150,7 @@ from topgen.lib import Name
  logic [${len(clocks.derived_srcs)-1}:0] step_down_acks;
 
 % for src_name in clocks.derived_srcs:
- logic clk_${src_name}_i;
+ logic clk_${src_name};
 % endfor
 
 % for src in clocks.derived_srcs.values():
@@ -159,12 +170,13 @@ from topgen.lib import Name
  prim_clock_div #(
  .Divisor(${src.div})
  ) u_no_scan_${src.name}_div (
+ // We're using the pre-occ hookup (*_i) version for clock derivation.
  .clk_i(clk_${src.src.name}_i),
  .rst_ni(rst_root_${src.src.name}_ni),
  .step_down_req_i(mubi4_test_true_strict(${src.src.name}_step_down_req)),
  .step_down_ack_o(step_down_acks[${loop.index}]),
  .test_en_i(mubi4_test_true_strict(${src.name}_div_scanmode[0])),
- .clk_o(clk_${src.name}_i)
+ .clk_o(clk_${src.name})
  );
 % endfor
 
@@ -184,7 +196,7 @@ from topgen.lib import Name
  .rst_ni,
  .rst_shadowed_ni,
 % for src in typed_clocks.rg_srcs:
- .clk_${src}_i,
+ .clk_${src}_i(clk_${src}),
  .rst_${src}_ni,
 % endfor
  .tl_i,
@@ -279,7 +291,7 @@ from topgen.lib import Name
  ////////////////////////////////////////////////////
 % for k,v in typed_clocks.ft_clks.items():
  prim_clock_buf u_${k}_buf (
- .clk_i(clk_${v.src.name}_i),
+ .clk_i(clk_${v.src.name}),
  .clk_o(clocks_o.${k})
  );
 
@@ -312,7 +324,7 @@ from topgen.lib import Name
  logic clk_${src}_en;
  logic clk_${src}_root;
  clkmgr_root_ctrl u_${src}_root_ctrl (
- .clk_i(clk_${src}_i),
+ .clk_i(clk_${src}),
  .rst_ni(rst_root_${src}_ni),
  .scanmode_i,
  .async_en_i(pwrmgr_${src}_en),
@@ -381,9 +393,9 @@ from topgen.lib import Name
  ) u_${src}_meas (
  .clk_i,
  .rst_ni,
- .clk_src_i(clk_${src}_i),
+ .clk_src_i(clk_${src}),
  .rst_src_ni(rst_${src}_ni),
- .clk_ref_i(clk_aon_i),
+ .clk_ref_i(clk_aon),
  .rst_ref_ni(rst_aon_ni),
  // signals on source domain
  .src_en_i(clk_${src}_en & mubi4_test_true_loose(mubi4_t'(reg2hw.${src}_meas_ctrl_en))),
@@ -413,7 +425,7 @@ from topgen.lib import Name
  prim_mubi4_sender #(
  .ResetValue(MuBi4True)
  ) u_prim_mubi4_sender_${k} (
- .clk_i(clk_${v.src.name}_i),
+ .clk_i(clk_${v.src.name}),
  .rst_ni(rst_${v.src.name}_ni),
  .mubi_i(((clk_${v.src.name}_en) ? MuBi4False : MuBi4True)),
  .mubi_o(cg_en_o.${k.split('clk_')[-1]})
@@ -432,7 +444,7 @@ from topgen.lib import Name
  prim_flop_2sync #(
  .Width(1)
  ) u_${k}_sw_en_sync (
- .clk_i(clk_${v.src.name}_i),
+ .clk_i(clk_${v.src.name}),
  .rst_ni(rst_${v.src.name}_ni),
  .d_i(reg2hw.clk_enables.${k}_en.q),
  .q_o(${k}_sw_en)
@@ -455,7 +467,7 @@ from topgen.lib import Name
  prim_clock_gating #(
  .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions.
  ) u_${k}_cg (
- .clk_i(clk_${v.src.name}_i),
+ .clk_i(clk_${v.src.name}),
  .en_i(${k}_combined_en),
  .test_en_i(mubi4_test_true_strict(${k}_scanmode[0])),
  .clk_o(clocks_o.${k})
@@ -465,7 +477,7 @@ from topgen.lib import Name
  prim_mubi4_sender #(
  .ResetValue(MuBi4True)
  ) u_prim_mubi4_sender_${k} (
- .clk_i(clk_${v.src.name}_i),
+ .clk_i(clk_${v.src.name}),
  .rst_ni(rst_${v.src.name}_ni),
  .mubi_i(((${k}_combined_en) ? MuBi4False : MuBi4True)),
  .mubi_o(cg_en_o.${k.split('clk_')[-1]})
@@ -490,7 +502,7 @@ from topgen.lib import Name
  .FpgaBufGlobal(1'b0) // This clock is used primarily locally.
 % endif
  ) u_${clk}_trans (
- .clk_i(clk_${sig.src.name}_i),
+ .clk_i(clk_${sig.src.name}),
  .clk_gated_i(clk_${sig.src.name}_root),
  .rst_ni(rst_${sig.src.name}_ni),
  .en_i(clk_${sig.src.name}_en),

diff --git a/hw/ip/clkmgr/dv/sva/clkmgr_bind.sv b/hw/ip/clkmgr/dv/sva/clkmgr_bind.sv
@@ -157,13 +157,13 @@ module clkmgr_bind;
  );
 
  bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_io_div2_powerup (
- .clk(clk_io_div2_i),
+ .clk(clk_io_div2),
  .rst_n(rst_io_div2_ni),
  .cg_en(cg_en_o.io_div2_powerup == prim_mubi_pkg::MuBi4True)
  );
 
  bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_io_div4_powerup (
- .clk(clk_io_div4_i),
+ .clk(clk_io_div4),
  .rst_n(rst_io_div4_ni),
  .cg_en(cg_en_o.io_div4_powerup == prim_mubi_pkg::MuBi4True)
  );
@@ -178,7 +178,7 @@ module clkmgr_bind;
 
  // Non-AON clock gating enables.
  bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_io_div2_infra (
- .clk(clk_io_div2_i),
+ .clk(clk_io_div2),
  .rst_n(rst_io_div2_ni),
  .ip_clk_en(clk_io_div2_en),
  .sw_clk_en(1'b1),
@@ -187,7 +187,7 @@ module clkmgr_bind;
  );
 
  bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_io_div4_infra (
- .clk(clk_io_div4_i),
+ .clk(clk_io_div4),
  .rst_n(rst_io_div4_ni),
  .ip_clk_en(clk_io_div4_en),
  .sw_clk_en(1'b1),
@@ -214,7 +214,7 @@ module clkmgr_bind;
  );
 
  bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_io_div4_secure (
- .clk(clk_io_div4_i),
+ .clk(clk_io_div4),
  .rst_n(rst_io_div4_ni),
  .ip_clk_en(clk_io_div4_en),
  .sw_clk_en(1'b1),
@@ -232,7 +232,7 @@ module clkmgr_bind;
  );
 
  bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_io_div4_timers (
- .clk(clk_io_div4_i),
+ .clk(clk_io_div4),
  .rst_n(rst_io_div4_ni),
  .ip_clk_en(clk_io_div4_en),
  .sw_clk_en(1'b1),
@@ -241,7 +241,7 @@ module clkmgr_bind;
  );
 
  bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_io_div2_peri (
- .clk(clk_io_div2_i),
+ .clk(clk_io_div2),
  .rst_n(rst_io_div2_ni),
  .ip_clk_en(clk_io_div2_en),
  .sw_clk_en(clk_io_div2_peri_sw_en),
@@ -250,7 +250,7 @@ module clkmgr_bind;
  );
 
  bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_io_div4_peri (
- .clk(clk_io_div4_i),
+ .clk(clk_io_div4),
  .rst_n(rst_io_div4_ni),
  .ip_clk_en(clk_io_div4_en),
  .sw_clk_en(clk_io_div4_peri_sw_en),