[otp_ctrl,gen] Parameterize OTP size

The hand-updated files are otp_ctrl.hjson.tpl, otp_ctrl_env_pkg.sv.tpl,
top_earlgrey.hjson, and top_darjeeling.hjson. The rest of the changes are
in generated files.

Signed-off-by: Guillermo Maturana <[email protected]>

hw/ip/otp_ctrl/data/otp_ctrl.hjson

@@ -2347,7 +2347,7 @@
  ////////////////////////////////
  // Software Config Partitions //
  ////////////////////////////////
- { skipto: "0x1000" }
+ { skipto: "0x800" }
 
  { window: {
  name: "SW_CFG_WINDOW"

hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl

@@ -14,6 +14,8 @@ for part in otp_mmap.config["partitions"]:
  if part["variant"] == "Unbuffered":
  num_part_unbuf += 1
 num_part_buf = num_part - num_part_unbuf
+otp_size_as_bytes = 2 ** otp_mmap.config["otp"]["byte_addr_width"]
+otp_size_as_uint32 = otp_size_as_bytes // 4
 %>\
 {
  name: "otp_ctrl",
@@ -172,7 +174,7 @@ num_part_buf = num_part - num_part_unbuf
  { name: "NumSwCfgWindowWords",
  desc: "Size of the TL-UL window in 32bit words. Note that the effective partition size is smaller than that.",
  type: "int",
- default: "512",
+ default: "${otp_size_as_uint32}",
  local: "true"
  }
 
@@ -1206,7 +1208,7 @@ num_part_buf = num_part - num_part_unbuf
  ////////////////////////////////
  // Software Config Partitions //
  ////////////////////////////////
- { skipto: "0x1000" }
+ { skipto: "${hex(otp_size_as_bytes)}" }
 
  { window: {
  name: "SW_CFG_WINDOW"

hw/ip/otp_ctrl/data/otp_ctrl_env_pkg.sv.tpl

@@ -7,6 +7,7 @@ from topgen.lib import Name
 
 parts_without_lc = [part for part in otp_mmap.config["partitions"] if
  part["variant"] in ["Buffered", "Unbuffered"]]
+otp_size_as_hex_text = f'{(2 ** otp_mmap.config["otp"]["byte_addr_width"]):x}'
 %>\
 package otp_ctrl_env_pkg;
  // dep packages
@@ -45,7 +46,7 @@ package otp_ctrl_env_pkg;
  parameter uint NUM_EDN = 1;
 
  parameter uint DIGEST_SIZE = 8;
- parameter uint SW_WINDOW_BASE_ADDR = 'h1000;
+ parameter uint SW_WINDOW_BASE_ADDR = 'h${otp_size_as_hex_text};
  parameter uint SW_WINDOW_SIZE = NumSwCfgWindowWords * 4;
 
  parameter uint TL_SIZE = (TL_DW / 8);

hw/ip/otp_ctrl/doc/registers.md

@@ -50,7 +50,7 @@
 | otp_ctrl.[`SECRET1_DIGEST_1`](#secret1_digest) | 0xa8 | 4 | Integrity digest for the SECRET1 partition. |
 | otp_ctrl.[`SECRET2_DIGEST_0`](#secret2_digest) | 0xac | 4 | Integrity digest for the SECRET2 partition. |
 | otp_ctrl.[`SECRET2_DIGEST_1`](#secret2_digest) | 0xb0 | 4 | Integrity digest for the SECRET2 partition. |
-| otp_ctrl.[`SW_CFG_WINDOW`](#sw_cfg_window) | 0x1000 | 2048 | Any read to this window directly maps to the corresponding offset in the creator and owner software |
+| otp_ctrl.[`SW_CFG_WINDOW`](#sw_cfg_window) | 0x800  | 2048 | Any read to this window directly maps to the corresponding offset in the creator and owner software |
 
 ## INTR_STATE
 Interrupt State Register
@@ -705,7 +705,7 @@ Any read to this window directly maps to the corresponding offset in the creator
 config partitions, and triggers an OTP readout of the bytes requested. Note that the transaction
 will block until OTP readout has completed.
 
-- Word Aligned Offset Range: `0x1000`to`0x17fc`
+- Word Aligned Offset Range: `0x800`to`0xffc`
 - Size (words): `512`
 - Access: `ro`
 - Byte writes are *not* supported.

hw/ip/otp_ctrl/dv/env/otp_ctrl_env_pkg.sv

@@ -41,7 +41,7 @@ package otp_ctrl_env_pkg;
  parameter uint NUM_EDN = 1;
 
  parameter uint DIGEST_SIZE = 8;
- parameter uint SW_WINDOW_BASE_ADDR = 'h1000;
+ parameter uint SW_WINDOW_BASE_ADDR = 'h800;
  parameter uint SW_WINDOW_SIZE = NumSwCfgWindowWords * 4;
 
  parameter uint TL_SIZE = (TL_DW / 8);

hw/ip/otp_ctrl/rtl/otp_ctrl_core_reg_top.sv

@@ -26,7 +26,7 @@ module otp_ctrl_core_reg_top (
 
  import otp_ctrl_reg_pkg::* ;
 
- localparam int AW = 13;
+ localparam int AW = 12;
  localparam int DW = 32;
  localparam int DBW = DW/8; // Byte Width
 
@@ -128,7 +128,7 @@ module otp_ctrl_core_reg_top (
  // Create steering logic
  always_comb begin
  reg_steer =
- tl_i.a_address[AW-1:0] inside {[4096:6143]} ? 1'd0 :
+ tl_i.a_address[AW-1:0] inside {[2048:4095]} ? 1'd0 :
  // Default set to register
  1'd1;
 

hw/ip/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv

@@ -185,7 +185,7 @@ package otp_ctrl_reg_pkg;
  parameter int NumAlerts = 5;
 
  // Address widths within the block
- parameter int CoreAw = 13;
+ parameter int CoreAw = 12;
  parameter int PrimAw = 5;
 
  ///////////////////////////////////////////////
@@ -442,51 +442,51 @@ package otp_ctrl_reg_pkg;
  } otp_ctrl_core_hw2reg_t;
 
  // Register offsets for core interface
- parameter logic [CoreAw-1:0] OTP_CTRL_INTR_STATE_OFFSET = 13'h 0;
- parameter logic [CoreAw-1:0] OTP_CTRL_INTR_ENABLE_OFFSET = 13'h 4;
- parameter logic [CoreAw-1:0] OTP_CTRL_INTR_TEST_OFFSET = 13'h 8;
- parameter logic [CoreAw-1:0] OTP_CTRL_ALERT_TEST_OFFSET = 13'h c;
- parameter logic [CoreAw-1:0] OTP_CTRL_STATUS_OFFSET = 13'h 10;
- parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_0_OFFSET = 13'h 14;
- parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_1_OFFSET = 13'h 18;
- parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_2_OFFSET = 13'h 1c;
- parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_3_OFFSET = 13'h 20;
- parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_4_OFFSET = 13'h 24;
- parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_5_OFFSET = 13'h 28;
- parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_6_OFFSET = 13'h 2c;
- parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_7_OFFSET = 13'h 30;
- parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_8_OFFSET = 13'h 34;
- parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_9_OFFSET = 13'h 38;
- parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET = 13'h 3c;
- parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET = 13'h 40;
- parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET = 13'h 44;
- parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET = 13'h 48;
- parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET = 13'h 4c;
- parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET = 13'h 50;
- parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET = 13'h 54;
- parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET = 13'h 58;
- parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TRIGGER_OFFSET = 13'h 5c;
- parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_REGWEN_OFFSET = 13'h 60;
- parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TIMEOUT_OFFSET = 13'h 64;
- parameter logic [CoreAw-1:0] OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET = 13'h 68;
- parameter logic [CoreAw-1:0] OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET = 13'h 6c;
- parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET = 13'h 70;
- parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET = 13'h 74;
- parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET = 13'h 78;
- parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET = 13'h 7c;
- parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET = 13'h 80;
- parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET = 13'h 84;
- parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET = 13'h 88;
- parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET = 13'h 8c;
- parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET = 13'h 90;
- parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG0_DIGEST_0_OFFSET = 13'h 94;
- parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG0_DIGEST_1_OFFSET = 13'h 98;
- parameter logic [CoreAw-1:0] OTP_CTRL_SECRET0_DIGEST_0_OFFSET = 13'h 9c;
- parameter logic [CoreAw-1:0] OTP_CTRL_SECRET0_DIGEST_1_OFFSET = 13'h a0;
- parameter logic [CoreAw-1:0] OTP_CTRL_SECRET1_DIGEST_0_OFFSET = 13'h a4;
- parameter logic [CoreAw-1:0] OTP_CTRL_SECRET1_DIGEST_1_OFFSET = 13'h a8;
- parameter logic [CoreAw-1:0] OTP_CTRL_SECRET2_DIGEST_0_OFFSET = 13'h ac;
- parameter logic [CoreAw-1:0] OTP_CTRL_SECRET2_DIGEST_1_OFFSET = 13'h b0;
+ parameter logic [CoreAw-1:0] OTP_CTRL_INTR_STATE_OFFSET = 12'h 0;
+ parameter logic [CoreAw-1:0] OTP_CTRL_INTR_ENABLE_OFFSET = 12'h 4;
+ parameter logic [CoreAw-1:0] OTP_CTRL_INTR_TEST_OFFSET = 12'h 8;
+ parameter logic [CoreAw-1:0] OTP_CTRL_ALERT_TEST_OFFSET = 12'h c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_STATUS_OFFSET = 12'h 10;
+ parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_0_OFFSET = 12'h 14;
+ parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_1_OFFSET = 12'h 18;
+ parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_2_OFFSET = 12'h 1c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_3_OFFSET = 12'h 20;
+ parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_4_OFFSET = 12'h 24;
+ parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_5_OFFSET = 12'h 28;
+ parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_6_OFFSET = 12'h 2c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_7_OFFSET = 12'h 30;
+ parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_8_OFFSET = 12'h 34;
+ parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_9_OFFSET = 12'h 38;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET = 12'h 3c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET = 12'h 40;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET = 12'h 44;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET = 12'h 48;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET = 12'h 4c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET = 12'h 50;
+ parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET = 12'h 54;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET = 12'h 58;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TRIGGER_OFFSET = 12'h 5c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_REGWEN_OFFSET = 12'h 60;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TIMEOUT_OFFSET = 12'h 64;
+ parameter logic [CoreAw-1:0] OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET = 12'h 68;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET = 12'h 6c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET = 12'h 70;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET = 12'h 74;
+ parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET = 12'h 78;
+ parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET = 12'h 7c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET = 12'h 80;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET = 12'h 84;
+ parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET = 12'h 88;
+ parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET = 12'h 8c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET = 12'h 90;
+ parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG0_DIGEST_0_OFFSET = 12'h 94;
+ parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG0_DIGEST_1_OFFSET = 12'h 98;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET0_DIGEST_0_OFFSET = 12'h 9c;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET0_DIGEST_1_OFFSET = 12'h a0;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET1_DIGEST_0_OFFSET = 12'h a4;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET1_DIGEST_1_OFFSET = 12'h a8;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET2_DIGEST_0_OFFSET = 12'h ac;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SECRET2_DIGEST_1_OFFSET = 12'h b0;
 
  // Reset values for hwext registers and their fields for core interface
  parameter logic [1:0] OTP_CTRL_INTR_TEST_RESVAL = 2'h 0;
@@ -579,7 +579,7 @@ package otp_ctrl_reg_pkg;
  parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL = 32'h 0;
 
  // Window parameters for core interface
- parameter logic [CoreAw-1:0] OTP_CTRL_SW_CFG_WINDOW_OFFSET = 13'h 1000;
+ parameter logic [CoreAw-1:0] OTP_CTRL_SW_CFG_WINDOW_OFFSET = 12'h 800;
  parameter int unsigned OTP_CTRL_SW_CFG_WINDOW_SIZE = 'h 800;
  parameter int unsigned OTP_CTRL_SW_CFG_WINDOW_IDX = 0;
 

hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson

@@ -1137,7 +1137,7 @@
  base_addrs:
  {
  core: 0x40130000
- prim: 0x40132000
+ prim: 0x40138000
  }
  clock_connections:
  {
@@ -10028,7 +10028,7 @@
  [
  {
  base_addr: 0x40130000
- size_byte: 0x2000
+ size_byte: 0x1000
  }
  ]
  xbar: false
@@ -10045,7 +10045,7 @@
  addr_range:
  [
  {
- base_addr: 0x40132000
+ base_addr: 0x40138000
  size_byte: 0x20
  }
  ]

hw/top_earlgrey/data/top_earlgrey.hjson

@@ -295,7 +295,7 @@
  clock_srcs: {clk_i: "io_div4", clk_edn_i: "main"},
  clock_group: "secure",
  reset_connections: {rst_ni: "lc_io_div4", rst_edn_ni: "lc"},
- base_addrs: {core: "0x40130000", prim: "0x40132000"}
+ base_addrs: {core: "0x40130000", prim: "0x40138000"}
  },
  { name: "lc_ctrl",
  type: "lc_ctrl",

hw/top_earlgrey/doc/design/README.md

@@ -409,7 +409,7 @@ For the purpose of `top_earlgrey`, the first option has been chosen to benefit s
 | pattgen | pattgen | 0x400E0000 (regs) |
 | rv_timer | rv_timer | 0x40100000 (regs) |
 | otp_ctrl | otp_ctrl | 0x40130000 (core) |
-| | | 0x40132000 (prim) |
+| | | 0x40138000 (prim) |
 | lc_ctrl | lc_ctrl | 0x40140000 (regs) |
 | alert_handler | alert_handler | 0x40150000 (regs) |
 | spi_host0 | spi_host | 0x40300000 (regs) |

hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv

@@ -125,10 +125,10 @@ tl_device_t xbar_devices[$] = '{
  '{32'h40460000, 32'h40460fff}
  }},
  '{"otp_ctrl__core", '{
- '{32'h40130000, 32'h40131fff}
+ '{32'h40130000, 32'h40130fff}
  }},
  '{"otp_ctrl__prim", '{
- '{32'h40132000, 32'h4013201f}
+ '{32'h40138000, 32'h4013801f}
  }},
  '{"lc_ctrl", '{
  '{32'h40140000, 32'h401400ff}

hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg

@@ -166,12 +166,11 @@
 -node tb.dut*.u_pinmux_aon tl_*i.a_address[21:19]
 -node tb.dut*.u_pinmux_aon tl_*i.a_address[29:23]
 -node tb.dut*.u_pinmux_aon tl_*i.a_address[31:31]
--node tb.dut*.u_otp_ctrl core_tl_*i.a_address[15:13]
+-node tb.dut*.u_otp_ctrl core_tl_*i.a_address[15:12]
 -node tb.dut*.u_otp_ctrl core_tl_*i.a_address[19:18]
 -node tb.dut*.u_otp_ctrl core_tl_*i.a_address[29:21]
 -node tb.dut*.u_otp_ctrl core_tl_*i.a_address[31:31]
--node tb.dut*.u_otp_ctrl prim_tl_*i.a_address[12:5]
--node tb.dut*.u_otp_ctrl prim_tl_*i.a_address[15:14]
+-node tb.dut*.u_otp_ctrl prim_tl_*i.a_address[14:5]
 -node tb.dut*.u_otp_ctrl prim_tl_*i.a_address[19:18]
 -node tb.dut*.u_otp_ctrl prim_tl_*i.a_address[29:21]
 -node tb.dut*.u_otp_ctrl prim_tl_*i.a_address[31:31]

hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson

@@ -376,7 +376,7 @@
  [
  {
  base_addr: 0x40130000
- size_byte: 0x2000
+ size_byte: 0x1000
  }
  ]
  xbar: false
@@ -393,7 +393,7 @@
  addr_range:
  [
  {
- base_addr: 0x40132000
+ base_addr: 0x40138000
  size_byte: 0x20
  }
  ]

hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg

@@ -76,12 +76,11 @@
 -node tb.dut tl_pinmux_aon_o.a_address[21:19]
 -node tb.dut tl_pinmux_aon_o.a_address[29:23]
 -node tb.dut tl_pinmux_aon_o.a_address[31:31]
--node tb.dut tl_otp_ctrl__core_o.a_address[15:13]
+-node tb.dut tl_otp_ctrl__core_o.a_address[15:12]
 -node tb.dut tl_otp_ctrl__core_o.a_address[19:18]
 -node tb.dut tl_otp_ctrl__core_o.a_address[29:21]
 -node tb.dut tl_otp_ctrl__core_o.a_address[31:31]
--node tb.dut tl_otp_ctrl__prim_o.a_address[12:5]
--node tb.dut tl_otp_ctrl__prim_o.a_address[15:14]
+-node tb.dut tl_otp_ctrl__prim_o.a_address[14:5]
 -node tb.dut tl_otp_ctrl__prim_o.a_address[19:18]
 -node tb.dut tl_otp_ctrl__prim_o.a_address[29:21]
 -node tb.dut tl_otp_ctrl__prim_o.a_address[31:31]

hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv

@@ -56,10 +56,10 @@ tl_device_t xbar_devices[$] = '{
  '{32'h40460000, 32'h40460fff}
  }},
  '{"otp_ctrl__core", '{
- '{32'h40130000, 32'h40131fff}
+ '{32'h40130000, 32'h40130fff}
  }},
  '{"otp_ctrl__prim", '{
- '{32'h40132000, 32'h4013201f}
+ '{32'h40138000, 32'h4013801f}
  }},
  '{"lc_ctrl", '{
  '{32'h40140000, 32'h401400ff}

hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv

@@ -23,7 +23,7 @@ package tl_peri_pkg;
  localparam logic [31:0] ADDR_SPACE_CLKMGR_AON = 32'h 40420000;
  localparam logic [31:0] ADDR_SPACE_PINMUX_AON = 32'h 40460000;
  localparam logic [31:0] ADDR_SPACE_OTP_CTRL__CORE = 32'h 40130000;
- localparam logic [31:0] ADDR_SPACE_OTP_CTRL__PRIM = 32'h 40132000;
+ localparam logic [31:0] ADDR_SPACE_OTP_CTRL__PRIM = 32'h 40138000;
  localparam logic [31:0] ADDR_SPACE_LC_CTRL = 32'h 40140000;
  localparam logic [31:0] ADDR_SPACE_SENSOR_CTRL_AON = 32'h 40490000;
  localparam logic [31:0] ADDR_SPACE_ALERT_HANDLER = 32'h 40150000;
@@ -50,7 +50,7 @@ package tl_peri_pkg;
  localparam logic [31:0] ADDR_MASK_RSTMGR_AON = 32'h 0000007f;
  localparam logic [31:0] ADDR_MASK_CLKMGR_AON = 32'h 0000007f;
  localparam logic [31:0] ADDR_MASK_PINMUX_AON = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_OTP_CTRL__CORE = 32'h 00001fff;
+ localparam logic [31:0] ADDR_MASK_OTP_CTRL__CORE = 32'h 00000fff;
  localparam logic [31:0] ADDR_MASK_OTP_CTRL__PRIM = 32'h 0000001f;
  localparam logic [31:0] ADDR_MASK_LC_CTRL = 32'h 000000ff;
  localparam logic [31:0] ADDR_MASK_SENSOR_CTRL_AON = 32'h 0000003f;

hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv

@@ -129,12 +129,12 @@ package top_earlgrey_pkg;
  /**
  * Peripheral size in bytes for core device on otp_ctrl in top earlgrey.
  */
- parameter int unsigned TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES = 32'h2000;
+ parameter int unsigned TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES = 32'h1000;
 
  /**
  * Peripheral base address for prim device on otp_ctrl in top earlgrey.
  */
- parameter int unsigned TOP_EARLGREY_OTP_CTRL_PRIM_BASE_ADDR = 32'h40132000;
+ parameter int unsigned TOP_EARLGREY_OTP_CTRL_PRIM_BASE_ADDR = 32'h40138000;
 
  /**
  * Peripheral size in bytes for prim device on otp_ctrl in top earlgrey.

hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs

@@ -187,13 +187,13 @@ pub const OTP_CTRL_CORE_BASE_ADDR: usize = 0x40130000;
 /// memory-mapped registers associated with this peripheral should have an
 /// address between #OTP_CTRL_CORE_BASE_ADDR and
 /// `OTP_CTRL_CORE_BASE_ADDR + OTP_CTRL_CORE_SIZE_BYTES`.
-pub const OTP_CTRL_CORE_SIZE_BYTES: usize = 0x2000;
+pub const OTP_CTRL_CORE_SIZE_BYTES: usize = 0x1000;
 
 /// Peripheral base address for prim device on otp_ctrl in top earlgrey.
 ///
 /// This should be used with #mmio_region_from_addr to access the memory-mapped
 /// registers associated with the peripheral (usually via a DIF).
-pub const OTP_CTRL_PRIM_BASE_ADDR: usize = 0x40132000;
+pub const OTP_CTRL_PRIM_BASE_ADDR: usize = 0x40138000;
 
 /// Peripheral size for prim device on otp_ctrl in top earlgrey.
 ///

hw/top_earlgrey/sw/autogen/top_earlgrey.h

@@ -239,15 +239,15 @@ extern "C" {
  * address between #TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR and
  * `TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES`.
  */
-#define TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES 0x2000u
+#define TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES 0x1000u
 
 /**
  * Peripheral base address for prim device on otp_ctrl in top earlgrey.
  *
  * This should be used with #mmio_region_from_addr to access the memory-mapped
  * registers associated with the peripheral (usually via a DIF).
  */
-#define TOP_EARLGREY_OTP_CTRL_PRIM_BASE_ADDR 0x40132000u
+#define TOP_EARLGREY_OTP_CTRL_PRIM_BASE_ADDR 0x40138000u
 
 /**
  * Peripheral size for prim device on otp_ctrl in top earlgrey.