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[top-level] Clarify uncalibrated IO/SYS/AON clock frequency test #18848

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matutem opened this issue Jun 8, 2023 · 6 comments
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[top-level] Clarify uncalibrated IO/SYS/AON clock frequency test #18848

matutem opened this issue Jun 8, 2023 · 6 comments
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Component:DV DV issue: testbench, test case, etc. Manufacturing Issues related to manufacturing tasks (hw or sw) TOP:earlgrey

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@matutem
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matutem commented Jun 8, 2023

Description

This closed-source test needs some clarification:

What is the purpose of the test? We have an external clock, which should enable clock calibration, so it is not clear what is the use of running completely uncalibrated frequency measurements.

Are all clocks meant to be uncalibrated (including AON)? What is the pass/fail criterium?

@matutem matutem added Component:DV DV issue: testbench, test case, etc. TOP:earlgrey Manufacturing Issues related to manufacturing tasks (hw or sw) labels Jun 8, 2023
@sha-ron
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sha-ron commented Jun 8, 2023

The purpose is to check the HW functionality until the clocks are calibrated or until we can switch to external clock
The most important thing is to check that we can move from raw to unlock0 LC state when all four clocks (AON, IO, System (MAIN), USB) are un-calibrated, we are supposed to have manuf_cp_unlock_raw test.
Then in unlock0 LC we need to check we can switch to external through clock manager.
(external clock should be selected by clkmgr, because when it is selected by lc ctrl only IO clock is derived from the external clock).
Another scenario is when we start from prod lc and until we see the clock are calibrated (indicated by AST init_done output).

@msfschaffner msfschaffner added this to the Discrete: M2.5.2 milestone Jun 9, 2023
@matutem
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matutem commented Jun 20, 2023

Referring to https://docs.google.com/spreadsheets/d/18Aj0hV44XGYGRlqnSZo6pEcVuZy7n7qNnPRHmPlHrQ4/edit?pli=1#gid=178420566, I think the check we can move from raw to unlock0 is the subject of line 6 in the Tasks tab, and switching to external clock is the subject of line 21. In any case, the task in line 22 explicitly refers to clock frequency test, so I think we can conclude it is invalid.

@matutem
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matutem commented Jun 20, 2023

Clock frequencies cannot be measured if the clocks are not calibrated, because until ast_init is done (at which point the clocks should be calibrated) the clkmgr clock frequency measurement hardware is disabled.

Regarding the Nuvoton tasks sheet mentioned above, I think we need to have a better description of the tasks, preferably as an issue?

Regarding a test that moves from raw to unlock0 LC state when all four clocks (AON, IO, System (MAIN), USB) are un-calibrated, is this a missing test? Line 6 seems to address the volatile RAW -> TEST_UNLOCKED0 transition, and the test seems to have been merged in #18276.

I think the tests to transition to external clock is covered by the various chip_sw_clkmgr_external_clk_src_for_sw_* tests.

Regarding a test with uncalibrated clocks starting from prod life cycle and the ROM code runs until we see the clock are calibrated (indicated by AST init_done output), all tests go through this specific transition, so I don't see the need for additional tests.

@matutem
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matutem commented Jun 22, 2023

The description in line 22 of https://docs.google.com/spreadsheets/d/18Aj0hV44XGYGRlqnSZo6pEcVuZy7n7qNnPRHmPlHrQ4/edit?pli=1#gid=178420566 is incorrect. Once that is updated I will close this issue. Makes sense?

@msfschaffner
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This test has been replaced with an adapted RAW unlock test that is now called rom_raw_unlock.
The test performs an unlock sequence with external clock (switched via LC), and then switches to an external clock in TEST_UNLOCKED0 state via the clock manager while AST remains uncalibrated.

@msfschaffner
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The test description can be found here:

name: chip_sw_rom_raw_unlock
desc: '''Configure RAW_UNLOCK via LC TAP interface and enable CPU execution.
This test characterizes the DUT initial state before RAW unlock operation, and
switches to external clock via clkmgr to ensure the system clock can be switched
right after transition into test_unlcoked0 state. The test also verifies that
AST is not initialized while CPU is executing code.
- Pre-load OTP image with RAW lc_state.
- Initiate the LC transition to test_unlocked0 state using the
RAW_UNLOCK mode of operation.
- Switch TAP interface to rv_dm and configure the ROM_EXEC_EN OTP to enable ROM
execution.
- If running with the production ROM, enable signature verification via OTBN to
improve simulation time.
- Perform POR to apply OTP changes.
- With rv_dm TAP still selected, switch to external clock via clkmgr using extclk
slow mode configuration.
- Wait for ROM to start executing code.
- Check AST init done equal to 0 via sensor_ctrl.
'''
stage: V2
tests: ["rom_raw_unlock"]
}

I am closing this now, since I think this is addressed - but please reopen if something is still unclear.

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