[top_earlgrey,tests] Fix clkmgr_external_clk_src_for_sw_slow_test_fpga_cw310_test_rom

[matutem]

Description

This test is failing on the cw310 fpga: only the main clk gets a measurement error, all others clocks are okay. The ...for_sw_fast..." test works okay.

[matutem]

It turns out the measurements of main in slow speed correspond to the expected values for fast. This means the main clk seems to be running at 96 MHz rather than the expected 48 MHz. In sim_dv main runs at the expected 48 MHz. Seems like an FPGA bug, since in silicon the external clock is used for calibration, and that flow works.

[a-will]

The FPGA doesn't support a physical external clock, nor having the main clock at a lower frequency. I think we can close this and accept that the test is not supported on FPGA, then (or at least CW310). Throwing in an alternate clock and muxing it out would consume more of already very impacted clocking resources on the CW310.

When we're in "48 MHz external clock" mode, though, what does work is compensating for clkmgr's switching of dividers. The I/O frequencies remain at the expected values.