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[chip_sw_clkmgr_jitter] #20230

Closed
6 of 10 tasks
matutem opened this issue Oct 30, 2023 · 0 comments · Fixed by #20283
Closed
6 of 10 tasks

[chip_sw_clkmgr_jitter] #20230

matutem opened this issue Oct 30, 2023 · 0 comments · Fixed by #20283
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@matutem
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Component:ChipLevelTest Used to filter the chip-level test backlog Component:SiliconValidation

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matutem commented Oct 30, 2023 •
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Test point name

chip_sw_clkmgr_jitter_cycle_measurements

Host side component

None Required

OpenTitanTool infrastructure implemented

None

Silicon Validation (SiVal)

Yes

Emulation Targets

  • None
  • CW310
  • Hyperdebug + CW310

Contact person

matutem

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • HJSON test plan updated with test name (so it shows up in the dashboard)
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression
@matutem matutem added Component:ChipLevelTest Used to filter the chip-level test backlog Component:SiliconValidation labels Oct 30, 2023
@matutem matutem self-assigned this Oct 30, 2023
matutem added a commit to matutem/opentitan that referenced this issue Nov 7, 2023
@matutem
[sival,clkmgr] Add test for chip_sw_clkmgr_jitter_cycle_measurements …
a30023b 
…testpoint

Fixes lowRISC#20230

Signed-off-by: Guillermo Maturana <[email protected]>
@matutem matutem mentioned this issue Nov 7, 2023
Merged
matutem added a commit to matutem/opentitan that referenced this issue Nov 7, 2023
@matutem
[sival,clkmgr] Add test for chip_sw_clkmgr_jitter_cycle_measurements …
2d783ae 
…testpoint

Fixes lowRISC#20230

Signed-off-by: Guillermo Maturana <[email protected]>
matutem added a commit to matutem/opentitan that referenced this issue Nov 7, 2023
@matutem
[sival,clkmgr] Add test for chip_sw_clkmgr_jitter_cycle_measurements …
599d043 
…testpoint

Fixes lowRISC#20230

Signed-off-by: Guillermo Maturana <[email protected]>
matutem added a commit that referenced this issue Nov 8, 2023
@matutem
[sival,clkmgr] Add test for chip_sw_clkmgr_jitter_cycle_measurements …
a2c84ab 
…testpoint

Fixes #20230

Signed-off-by: Guillermo Maturana <[email protected]>
@msfschaffner msfschaffner mentioned this issue Feb 15, 2024
Closed
@matutem matutem mentioned this issue Feb 15, 2024
Closed
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Labels
Component:ChipLevelTest Used to filter the chip-level test backlog Component:SiliconValidation
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[sival,clkmgr] Add test for chip_sw_clkmgr_jitter_cycle_measurements testpoint matutem/opentitan
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