[top] Provide list of desired vectors for power estimation

[tjaychen]

• power virus test that simulates maximum instantaneous step. This should include

  • staggered activation of otbn, aes, kmac/hmac.
    - kmac / aes would need to take turns being fed data
    - kmac activation should be a combination of otp background, key manager background and software
    - for otbn, any signature verification / signing event is sufficient
  • entropy complex ongoing
    - reseed / update operation ongoing
  • flash scramble ongoing (ideally both instruction and data, but data should be sufficient for now)
    - instruction scrambling gated by script availability
  • simultaneous io toggling as defined here
    - ideally for digital activity, 3xuart / 2xi2c modules should be activated
    - for first pass simplicity can activate IO portion only for now through GPIO
    - for dedicated pins, focus on SPI device quad activity
    - USB activity should be activated
    - for first pass simplicity activate IO portion only for now via pin forcing in usbdev.
  • ongoing cpu activity (icache / sram scrambling both activated)
    - servicing ongoing threads and random read/write data to memory
    - icache needs to be activated, otherwise the system may spend most of its time fetching code
    - flash verification is currently insufficient to turn on icache
  • background checks enabled wherever possible
    - rstmgr background checks
    - others?

• low power test that simulates deep sleep state

• low power test that simulates light sleep state

• general system idle that is NOT low power

Make sure to document these test cases in the test plan.

[tjaychen]

@zi-v

[zi-v]

Thanks!

[tjaychen]

@zi-v let me know if there are other scenarios of interest.

[zi-v]

For the max instantaneous step, please also consider adding concurrent IO toggling.

[tjaychen]

yes that is the plan.

…

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[zi-v]

More power scenarios:

• Power up
• Transition from Active to AON
• Transition from AON to Active

[tjaychen]

@zi-v are the latter two not covered by transition in and out of low power states? That was my intent.

[zi-v]

They are. I was just not clear to me that the above covers it already. I thought it only talk about the static state and wanted to make sure that the transitions are also covered.