initial work on SMBUS

drivers/smbus/smbus_mspm0.c

@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2024 Texas Instruments
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ti_mspm0_smbus
+
+/* Zephyr Includes */
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/smbus.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <soc.h>
+
+struct smbus_mspm0_config {
+ uint32_t base;
+};
+
+struct smbus_mspm0_data {
+ uint32_t value;
+};
+
+static void smbus_mspm0_init(const struct device *dev) {
+ i2c_mspm0_init(dev);
+}
+
+static int smbus_mspm0_configure(const struct device *dev, uint32_t dev_config){
+
+}
+
+static int smbus_mspm0_get_config(const struct device *dev, uint32_t * dev_config){
+
+}
+
+static int smbus_mspm0_quick(const struct device *dev, uint16_t addr, enum smbus_direction direction){
+
+}
+
+static const struct smbus_driver_api smbus_mspm0_driver_api = {
+ .xfer_stats = //
+ .configure = smbus_mspm0_configure,
+ .get_config = smbus_mspm0_get_config,
+ .smbalert_set_cb = //
+ .smbalert_remove_cb = //
+ .host_notify_set = //
+ .host_notify_remove_cb = //
+ .quick = smbus_mspm0_quick,
+ .byte_write = //
+ .byte_read = //
+ .byte_data_write = //
+ .byte_data_read = //
+ .word_data_write = //
+ .word_data_read = //
+ .pcall = //
+ .block_write = //
+ .block_read = //
+ .block_pcall = //
+ // add target stuff next
+};
+
+
+#define MSP_SMBUS_INIT_FN(index) \
+ \
+ PINCTRL_DT_INST_DEFINE(index); \
+ \ \
+ \
+ static const struct i2c_mspm0_config i2c_mspm0_cfg_##index = { \
+ .base = DT_INST_REG_ADDR(index), \
+ .clock_frequency = DT_INST_PROP(index, clock_frequency), \
+ .pinctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
+ .interrupt_init_function = i2c_mspm0_interrupt_init_##index, \
+ .gI2CClockConfig = {.clockSel = DL_I2C_CLOCK_BUSCLK, \
+ .divideRatio = DL_I2C_CLOCK_DIVIDE_1}}; \
+ \
+ static struct i2c_mspm0_data i2c_mspm0_data_##index; \
+ \
+ I2C_DEVICE_DT_INST_DEFINE(index, i2c_mspm0_init, NULL, &i2c_mspm0_data_##index, \
+ &i2c_mspm0_cfg_##index, POST_KERNEL, \
+ CONFIG_I2C_INIT_PRIORITY, &i2c_mspm0_driver_api); \
+ \
+ INTERRUPT_INIT_FUNCTION(index)
+
+DT_INST_FOREACH_STATUS_OKAY(MSP_SMBUS_INIT_FN)

dts/arm/ti/mspm0g3xxx.dtsi

@@ -142,6 +142,18 @@
  };
 
  };
+
+ smbus0: smbus0 {
+ compatible = "ti,mspm0-smbus";
+ i2c = <&i2c0>;
+ status = "disabled";
+ };
+
+ smbus1: smbus1 {
+ compatible = "ti,mspm0-smbus";
+ i2c = <&i2c1>;
+ status = "disabled";
+ };
 };
 
 &nvic {

dts/arm/ti/mspm0l2xxx.dtsi

@@ -122,6 +122,18 @@
  ti,watchdog-reset-action = <1>;
  };
  };
+
+ smbus0: smbus0 {
+ compatible = "ti,mspm0-smbus";
+ i2c = <&i2c0>;
+ status = "disabled";
+ };
+
+ smbus1: smbus1 {
+ compatible = "ti,mspm0-smbus";
+ i2c = <&i2c1>;
+ status = "disabled";
+ };
 };
 
 &nvic {

dts/bindings/smbus/ti,mspm0-smbus.yaml

@@ -0,0 +1,17 @@
+# Copyright (c) 2024 Texas Instruments
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+ TI MSPM0 SMBUS implementation, put on top of a
+ capable I2C peripheral in order to follow the SMBUS protocol as either
+ a controller or a target
+
+compatible: "ti,mspm0-smbus"
+
+include: base.yaml
+
+properties: 
+ i2c: 
+ type: phandle
+ required: true
+ description: The underlying I2C instance