snippets: emulated-gpio: align RRAM

Since FLPR's SRAM was shrunk, so can be the RRAM. In consequence, APP's RRAM can be extended. Signed-off-by: Marcin Szymczyk <[email protected]>
nrfconnect · Oct 18, 2024 · 00bf910 · 00bf910
1 parent 4d2b800
commit 00bf910
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Showing 3 changed files with 18 additions and 9 deletions.
diff --git a/snippets/emulated-gpio/icbmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/snippets/emulated-gpio/icbmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
@@ -10,9 +10,8 @@
  #address-cells = <1>;
  #size-cells = <1>;
 
- cpuflpr_code_partition: image@165000 {
- /* FLPR core code partition */
- reg = <0x165000 DT_SIZE_K(96)>;
+ cpuflpr_code_partition: image@179800 {
+ reg = <0x179800 DT_SIZE_K(14)>;
  };
 
  sram_rx: memory@2003b800 {
@@ -48,6 +47,10 @@
  };
 };
 
+&cpuapp_rram {
+ reg = <0x0 DT_SIZE_K(1510)>;
+};
+
 &cpuapp_sram {
  reg = <0x20000000 DT_SIZE_K(242)>;
  ranges = <0x0 0x20000000 0x3d000>;

diff --git a/snippets/emulated-gpio/icmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/snippets/emulated-gpio/icmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
@@ -10,9 +10,8 @@
  #address-cells = <1>;
  #size-cells = <1>;
 
- cpuflpr_code_partition: image@165000 {
- /* FLPR core code partition */
- reg = <0x165000 DT_SIZE_K(96)>;
+ cpuflpr_code_partition: image@17a000 {
+ reg = <0x17a000 DT_SIZE_K(12)>;
  };
 
  sram_rx: memory@2003c000 {
@@ -46,6 +45,10 @@
  };
 };
 
+&cpuapp_rram {
+ reg = <0x0 DT_SIZE_K(1512)>;
+};
+
 &cpuapp_sram {
  reg = <0x20000000 DT_SIZE_K(244)>;
  ranges = <0x0 0x20000000 0x3d000>;

diff --git a/snippets/emulated-gpio/mbox/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/snippets/emulated-gpio/mbox/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
@@ -10,9 +10,8 @@
  #address-cells = <1>;
  #size-cells = <1>;
 
- cpuflpr_code_partition: image@165000 {
- /* FLPR core code partition */
- reg = <0x165000 DT_SIZE_K(96)>;
+ cpuflpr_code_partition: image@17a000 {
+ reg = <0x17a000 DT_SIZE_K(12)>;
  };
 
  sram_rx: memory@2003c000 {
@@ -41,6 +40,10 @@
  };
 };
 
+&cpuapp_rram {
+ reg = <0x0 DT_SIZE_K(1512)>;
+};
+
 &cpuapp_sram {
  reg = <0x20000000 DT_SIZE_K(244)>;
  ranges = <0x0 0x20000000 0x3d000>;