snippets: emulated-gpio: align RRAM

applications/sdp/gpio/CMakeLists.txt

@@ -11,4 +11,5 @@ project(emulated_gpio)
 
 target_sources(app PRIVATE src/main.c)
 target_sources_ifdef(CONFIG_GPIO_NRFE_EGPIO_BACKEND_ICMSG app PRIVATE src/backend/backend_icmsg.c)
+target_sources_ifdef(CONFIG_GPIO_NRFE_EGPIO_BACKEND_ICBMSG app PRIVATE src/backend/backend_icmsg.c)
 target_sources_ifdef(CONFIG_GPIO_NRFE_EGPIO_BACKEND_MBOX app PRIVATE src/backend/backend_mbox.c)

applications/sdp/gpio/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay

@@ -4,28 +4,6 @@
  * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
  */
 
-/ {
- soc {
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
-
- sram_tx: memory@2003c000 {
- reg = <0x2003c000 0x0800>;
- };
-
- sram_rx: memory@2003c800 {
- reg = <0x2003c800 0x0800>;
- };
- };
- };
-};
-
-&cpuflpr_sram {
- reg = <0x2003d000 DT_SIZE_K(12)>;
- ranges = <0x0 0x2003d000 0x3000>;
-};
-
 &cpuflpr_vevif_rx {
  status = "okay";
  interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>;

applications/sdp/gpio/boards/nrf54l15dk_nrf54l15_cpuflpr_icbmsg.overlay

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/ {
+ soc {
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sram_tx: memory@2003b800 {
+ reg = <0x2003b800 0x0800>;
+ };
+
+ sram_rx: memory@2003c000 {
+ reg = <0x2003c000 0x0800>;
+ };
+ };
+ };
+
+ ipc {
+ ipc0: ipc0 {
+ compatible = "zephyr,ipc-icbmsg";
+ tx-region = <&sram_tx>;
+ rx-region = <&sram_rx>;
+ tx-blocks = <18>;
+ rx-blocks = <16>;
+ mboxes = <&cpuflpr_vevif_rx 16>, <&cpuflpr_vevif_tx 20>;
+ mbox-names = "rx", "tx";
+ status = "okay";
+ };
+ };
+};
+
+&cpuflpr_rram {
+ reg = <0x179800 DT_SIZE_K(14)>;
+};
+
+&cpuflpr_code_partition {
+ reg = <0x0 DT_SIZE_K(14)>;
+};
+
+&cpuflpr_sram {
+ reg = <0x2003c800 DT_SIZE_K(14)>;
+ ranges = <0x0 0x2003c800 0x3800>;
+};

applications/sdp/gpio/boards/nrf54l15dk_nrf54l15_cpuflpr_icmsg.overlay

@@ -5,6 +5,21 @@
  */
 
 / {
+ soc {
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sram_tx: memory@2003c000 {
+ reg = <0x2003c000 0x0800>;
+ };
+
+ sram_rx: memory@2003c800 {
+ reg = <0x2003c800 0x0800>;
+ };
+ };
+ };
+
  ipc {
  ipc0: ipc0 {
  compatible = "zephyr,ipc-icmsg";
@@ -16,3 +31,16 @@
  };
  };
 };
+
+&cpuflpr_rram {
+ reg = <0x17a000 DT_SIZE_K(12)>;
+};
+
+&cpuflpr_code_partition {
+ reg = <0x0 DT_SIZE_K(12)>;
+};
+
+&cpuflpr_sram {
+ reg = <0x2003d000 DT_SIZE_K(12)>;
+ ranges = <0x0 0x2003d000 0x3000>;
+};

applications/sdp/gpio/boards/nrf54l15dk_nrf54l15_cpuflpr_mbox.overlay

@@ -5,9 +5,37 @@
  */
 
 / {
+ soc {
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sram_tx: memory@2003c000 {
+ reg = <0x2003c000 0x0800>;
+ };
+
+ sram_rx: memory@2003c800 {
+ reg = <0x2003c800 0x0800>;
+ };
+ };
+ };
+
  mbox_consumer: mbox_consumer {
  compatible = "vnd,mbox-consumer";
  mboxes = <&cpuflpr_vevif_rx 16>, <&cpuflpr_vevif_tx 20>;
  mbox-names = "rx", "tx";
  };
 };
+
+&cpuflpr_rram {
+ reg = <0x17a000 DT_SIZE_K(12)>;
+};
+
+&cpuflpr_code_partition {
+ reg = <0x0 DT_SIZE_K(12)>;
+};
+
+&cpuflpr_sram {
+ reg = <0x2003d000 DT_SIZE_K(12)>;
+ ranges = <0x0 0x2003d000 0x3000>;
+};

applications/sdp/gpio/sample.yaml

@@ -26,3 +26,16 @@ tests:
  - CONFIG_GPIO_NRFE_EGPIO_BACKEND_ICMSG=y
  - CONFIG_IPC_SERVICE=y
  - CONFIG_IPC_SERVICE_BACKEND_ICMSG=y
+
+ applications.sdp.egpio_icbmsg:
+ sysbuild: true
+ build_only: true
+ platform_allow: nrf54l15dk/nrf54l15/cpuflpr
+ tags: ci_build sysbuild
+ extra_args:
+ EXTRA_DTC_OVERLAY_FILE="./boards/nrf54l15dk_nrf54l15_cpuflpr_icbmsg.overlay"
+ extra_configs:
+ - CONFIG_GPIO_NRFE_EGPIO_BACKEND_ICBMSG=y
+ - CONFIG_IPC_SERVICE=y
+ - CONFIG_IPC_SERVICE_BACKEND_ICBMSG=y
+ - CONFIG_IPC_SERVICE_BACKEND_ICBMSG_NUM_EP=1

applications/sdp/gpio/src/backend/backend.h

@@ -9,7 +9,9 @@
 
 #include <drivers/gpio/nrfe_gpio.h>
 
-#if !defined(CONFIG_GPIO_NRFE_EGPIO_BACKEND_ICMSG) && !defined(CONFIG_GPIO_NRFE_EGPIO_BACKEND_MBOX)
+#if !defined(CONFIG_GPIO_NRFE_EGPIO_BACKEND_ICMSG) && \
+ !defined(CONFIG_GPIO_NRFE_EGPIO_BACKEND_MBOX) && \
+ !defined(CONFIG_GPIO_NRFE_EGPIO_BACKEND_ICBMSG)
 #error "Define communication backend type"
 #endif
 

cmake/sysbuild/sdp.cmake

@@ -28,6 +28,18 @@ function(egpio_update_kconfig)
  endif()
  sysbuild_cache_set(VAR ${DEFAULT_IMAGE}_SNIPPET APPEND REMOVE_DUPLICATES "emulated-gpio-icmsg")
  message(STATUS "eGPIO: Using ICMSG backend")
+ elseif(SB_CONFIG_EGPIO_BACKEND_ICBMSG)
+ foreach(image ${PRE_CMAKE_IMAGES})
+ set_config_bool(${image} CONFIG_GPIO_NRFE_EGPIO_BACKEND_ICBMSG y)
+ set_property(TARGET ${image} APPEND_STRING PROPERTY CONFIG "CONFIG_IPC_SERVICE_BACKEND_ICBMSG_NUM_EP=1\n")
+ endforeach()
+ set_config_bool(flpr_egpio CONFIG_IPC_SERVICE y)
+ set_config_bool(flpr_egpio CONFIG_IPC_SERVICE_BACKEND_ICBMSG y)
+ if(DEFINED SB_CONFIG_SOC_NRF54L15)
+ sysbuild_cache_set(VAR flpr_egpio_EXTRA_DTC_OVERLAY_FILE APPEND REMOVE_DUPLICATES "./boards/nrf54l15dk_nrf54l15_cpuflpr_icbmsg.overlay")
+ endif()
+ sysbuild_cache_set(VAR ${DEFAULT_IMAGE}_SNIPPET APPEND REMOVE_DUPLICATES "emulated-gpio-icbmsg")
+ message(STATUS "eGPIO: Using ICBMSG backend")
  endif()
 endfunction()
 

drivers/gpio/CMakeLists.txt

@@ -7,7 +7,7 @@
 zephyr_library_amend()
 
 if(CONFIG_GPIO_NRFE)
- if(CONFIG_GPIO_NRFE_EGPIO_BACKEND_ICMSG)
+ if(CONFIG_GPIO_NRFE_EGPIO_BACKEND_ICMSG OR CONFIG_GPIO_NRFE_EGPIO_BACKEND_ICBMSG)
  zephyr_library_sources(gpio_nrfe_icmsg.c)
  elseif(CONFIG_GPIO_NRFE_EGPIO_BACKEND_MBOX)
  zephyr_library_sources(gpio_nrfe_mbox.c)

drivers/gpio/Kconfig

@@ -37,4 +37,9 @@ config GPIO_NRFE_EGPIO_BACKEND_ICMSG
  help
  Use ICMSG backend driver for eGPIO.
 
+config GPIO_NRFE_EGPIO_BACKEND_ICBMSG
+ bool "ICBMSG backend for eGPIO"
+ help
+ Use ICBMSG backend driver for eGPIO.
+
 endchoice

drivers/gpio/gpio_nrfe.h

@@ -10,7 +10,9 @@
 #include <drivers/gpio/nrfe_gpio.h>
 #include <zephyr/device.h>
 
-#if !defined(CONFIG_GPIO_NRFE_EGPIO_BACKEND_ICMSG) && !defined(CONFIG_GPIO_NRFE_EGPIO_BACKEND_MBOX)
+#if !defined(CONFIG_GPIO_NRFE_EGPIO_BACKEND_ICMSG) && \
+ !defined(CONFIG_GPIO_NRFE_EGPIO_BACKEND_MBOX) && \
+ !defined(CONFIG_GPIO_NRFE_EGPIO_BACKEND_ICBMSG)
 #error "Configure communication backend type"
 #endif
 

scripts/twister/alt/zephyr/samples/basic/blinky/sample.yaml

@@ -49,3 +49,22 @@ tests:
  regex:
  - "LED state: ON"
  - "LED state: OFF"
+
+ sample.basic.blinky.egpio_icbmsg:
+ sysbuild: true
+ platform_allow:
+ - nrf54l15dk/nrf54l15/cpuapp
+ integration_platforms:
+ - nrf54l15dk/nrf54l15/cpuapp
+ extra_args: SB_CONFIG_SDP=y
+ SB_CONFIG_EGPIO_FLPR_APPLICATION=y
+ SB_CONFIG_EGPIO_BACKEND_ICBMSG=y
+ SB_CONFIG_PARTITION_MANAGER=n
+ EXTRA_DTC_OVERLAY_FILE="./boards/nrf54l15dk_nrf54l15_cpuapp_egpio.overlay"
+ harness: console
+ harness_config:
+ type: multi_line
+ ordered: true
+ regex:
+ - "LED state: ON"
+ - "LED state: OFF"

snippets/emulated-gpio/icbmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay

@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/ {
+ soc {
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpuflpr_code_partition: image@179800 {
+ reg = <0x179800 DT_SIZE_K(14)>;
+ };
+
+ sram_rx: memory@2003b800 {
+ reg = <0x2003b800 0x0800>;
+ };
+
+ sram_tx: memory@2003c000 {
+ reg = <0x2003c000 0x0800>;
+ };
+ };
+
+
+ cpuflpr_sram_code_data: memory@2003c800 {
+ compatible = "mmio-sram";
+ reg = <0x2003c800 DT_SIZE_K(14)>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2003c800 0x3800>;
+ };
+ };
+
+ ipc {
+ ipc0: ipc0 {
+ compatible = "zephyr,ipc-icbmsg";
+ tx-region = <&sram_tx>;
+ rx-region = <&sram_rx>;
+ tx-blocks = <16>;
+ rx-blocks = <18>;
+ mboxes = <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_tx 16>;
+ mbox-names = "rx", "tx";
+ status = "okay";
+ };
+ };
+};
+
+&cpuapp_rram {
+ reg = <0x0 DT_SIZE_K(1510)>;
+};
+
+&cpuapp_sram {
+ reg = <0x20000000 DT_SIZE_K(242)>;
+ ranges = <0x0 0x20000000 0x3d000>;
+};
+
+&cpuflpr_vpr {
+ execution-memory = <&cpuflpr_sram_code_data>;
+ source-memory = <&cpuflpr_code_partition>;
+};
+
+&gpio2 {
+ status = "disabled";
+};
+
+&cpuapp_vevif_rx {
+ status = "okay";
+};
+
+&cpuapp_vevif_tx {
+ status = "okay";
+};
+
+&egpio {
+ status = "okay";
+};

snippets/emulated-gpio/icbmsg/emulated-gpio.overlay

@@ -0,0 +1,17 @@
+/* Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+&cpuflpr_vpr {
+ status = "okay";
+
+ egpio: gpio {
+ compatible = "nordic,nrfe-gpio";
+ gpio-controller;
+ #gpio-cells = <0x2>;
+ ngpios = <0x10>;
+ status = "disabled";
+ port = <0x2>;
+ };
+};

snippets/emulated-gpio/icbmsg/snippet.yml

@@ -0,0 +1,14 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+name: emulated-gpio-icbmsg
+append:
+ EXTRA_DTC_OVERLAY_FILE: emulated-gpio.overlay
+
+boards:
+ nrf54l15dk/nrf54l15/cpuapp:
+ append:
+ EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15dk_nrf54l15_cpuapp.overlay

snippets/emulated-gpio/icmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay

@@ -10,9 +10,8 @@
  #address-cells = <1>;
  #size-cells = <1>;
 
- cpuflpr_code_partition: image@165000 {
- /* FLPR core code partition */
- reg = <0x165000 DT_SIZE_K(96)>;
+ cpuflpr_code_partition: image@17a000 {
+ reg = <0x17a000 DT_SIZE_K(12)>;
  };
 
  sram_rx: memory@2003c000 {
@@ -46,6 +45,10 @@
  };
 };
 
+&cpuapp_rram {
+ reg = <0x0 DT_SIZE_K(1512)>;
+};
+
 &cpuapp_sram {
  reg = <0x20000000 DT_SIZE_K(244)>;
  ranges = <0x0 0x20000000 0x3d000>;