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[hardware] 🐛Fix vasub&vasubu error in simd_alu.
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Bowen-0x00 authored and mp-17 committed Sep 7, 2024
1 parent c5e7d17 commit df5b8d4
Showing 1 changed file with 4 additions and 4 deletions.
8 changes: 4 additions & 4 deletions hardware/src/lane/simd_alu.sv
Original file line number Diff line number Diff line change
Expand Up @@ -328,7 +328,7 @@ module simd_alu import ara_pkg::*; import rvv_pkg::*; #(
2'b10: r = 1'b0;
2'b11: r = !sub[1] & (sub[0]!=0);
endcase
res.w8[b] = (op_i == VSSUBU) ? (sub[7:0] >> 1) + r : $signed(sub[7:0]) >>> 1 + r;
res.w8[b] = (op_i == VASUBU) ? (sub[7:0] >> 1) + r : ($signed(sub[7:0]) >>> 1) + r;
end
EW16: for (int b = 0; b < 4; b++) begin
automatic logic [ 16:0] sub = opb.w16[b] - opa.w16[b];
Expand All @@ -338,7 +338,7 @@ module simd_alu import ara_pkg::*; import rvv_pkg::*; #(
2'b10: r = 1'b0;
2'b11: r = !sub[1] & (sub[0]!=0);
endcase
res.w16[b] = (op_i == VSSUBU) ? (sub[15:0] >> 1) + r : $signed(sub[15:0]) >>> 1 + r;
res.w16[b] = (op_i == VASUBU) ? (sub[15:0] >> 1) + r : ($signed(sub[15:0]) >>> 1) + r;
end
EW32: for (int b = 0; b < 2; b++) begin
automatic logic [ 32:0] sub = opb.w32[b] - opa.w32[b];
Expand All @@ -348,7 +348,7 @@ module simd_alu import ara_pkg::*; import rvv_pkg::*; #(
2'b10: r = 1'b0;
2'b11: r = !sub[1] & (sub[0]!=0);
endcase
res.w32[b] = (op_i == VSSUBU) ? (sub[31:0] >> 1) + r : $signed(sub[31:0]) >>> 1 + r;
res.w32[b] = (op_i == VASUBU) ? (sub[31:0] >> 1) + r : ($signed(sub[31:0]) >>> 1) + r;
end
EW64: for (int b = 0; b < 1; b++) begin
automatic logic [ 64:0] sub = opb.w64[b] - opa.w64[b];
Expand All @@ -358,7 +358,7 @@ module simd_alu import ara_pkg::*; import rvv_pkg::*; #(
2'b10: r = 1'b0;
2'b11: r = !sub[1] & (sub[0]!=0);
endcase
res.w64[b] = (op_i == VSSUBU) ? (sub[63:0] >> 1) + r : $signed(sub[63:0]) >>> 1 + r;
res.w64[b] = (op_i == VASUBU) ? (sub[63:0] >> 1) + r : ($signed(sub[63:0]) >>> 1) + r;
end
endcase

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