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[hardware] 🐛 Fix legality checks for vmadc/vmsbc
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@mp-17
mp-17 committed Aug 26, 2024
1 parent 60293d1 commit e99e7b6
Showing 1 changed file with 7 additions and 70 deletions.
77 changes: 7 additions & 70 deletions hardware/src/ara_dispatcher.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -579,23 +579,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
ara_req_d.op = ara_pkg::VMADC;

// Check whether we can access vs1 and vs2
unique case (ara_req_d.emul)
LMUL_2:
if (((insn.varith_type.rs1 & 5'b00001) == (insn.varith_type.rd & 5'b00001)) ||
((insn.varith_type.rs2 & 5'b00001) == (insn.varith_type.rd & 5'b00001)))
illegal_insn = 1'b1;
LMUL_4:
if (((insn.varith_type.rs1 & 5'b00011) == (insn.varith_type.rd & 5'b00011)) ||
((insn.varith_type.rs2 & 5'b00011) == (insn.varith_type.rd & 5'b00011)))
illegal_insn = 1'b1;
LMUL_8:
if (((insn.varith_type.rs1 & 5'b00111) == (insn.varith_type.rd & 5'b00111)) ||
((insn.varith_type.rs2 & 5'b00111) == (insn.varith_type.rd & 5'b00111)))
illegal_insn = 1'b1;
default:
if ((insn.varith_type.rs1 == insn.varith_type.rd) ||
(insn.varith_type.rs2 == insn.varith_type.rd)) illegal_insn = 1'b1;
endcase
if ((insn.varith_type.rs1 == insn.varith_type.rd) ||
(insn.varith_type.rs2 == insn.varith_type.rd)) illegal_insn = 1'b1;
end
6'b010010: begin
ara_req_d.op = ara_pkg::VSBC;
Expand All @@ -608,23 +593,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
ara_req_d.op = ara_pkg::VMSBC;

// Check whether we can access vs1 and vs2
unique case (ara_req_d.emul)
LMUL_2:
if (((insn.varith_type.rs1 & 5'b00001) == (insn.varith_type.rd & 5'b00001)) ||
((insn.varith_type.rs2 & 5'b00001) == ( insn.varith_type.rd & 5'b00001)))
illegal_insn = 1'b1;
LMUL_4:
if (((insn.varith_type.rs1 & 5'b00011) == (insn.varith_type.rd & 5'b00011)) ||
((insn.varith_type.rs2 & 5'b00011) == (insn.varith_type.rd & 5'b00011)))
illegal_insn = 1'b1;
LMUL_8:
if (((insn.varith_type.rs1 & 5'b00111) == (insn.varith_type.rd & 5'b00111)) ||
((insn.varith_type.rs2 & 5'b00111) == (insn.varith_type.rd & 5'b00111)))
illegal_insn = 1'b1;
default:
if ((insn.varith_type.rs1 == insn.varith_type.rd) ||
(insn.varith_type.rs2 == insn.varith_type.rd)) illegal_insn = 1'b1;
endcase
if ((insn.varith_type.rs1 == insn.varith_type.rd) ||
(insn.varith_type.rs2 == insn.varith_type.rd)) illegal_insn = 1'b1;
end
6'b011000: begin
ara_req_d.op = ara_pkg::VMSEQ;
Expand Down Expand Up @@ -811,18 +781,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
ara_req_d.op = ara_pkg::VMADC;

// Check whether we can access vs1 and vs2
unique case (ara_req_d.emul)
LMUL_2:
if ((insn.varith_type.rs2 & 5'b00001) == (insn.varith_type.rd & 5'b00001))
illegal_insn = 1'b1;
LMUL_4:
if ((insn.varith_type.rs2 & 5'b00011) == (insn.varith_type.rd & 5'b00011))
illegal_insn = 1'b1;
LMUL_8:
if ((insn.varith_type.rs2 & 5'b00111) == (insn.varith_type.rd & 5'b00111))
illegal_insn = 1'b1;
default: if (insn.varith_type.rs2 == insn.varith_type.rd) illegal_insn = 1'b1;
endcase
if (insn.varith_type.rs2 == insn.varith_type.rd) illegal_insn = 1'b1;
end
6'b010010: begin
ara_req_d.op = ara_pkg::VSBC;
Expand All @@ -837,18 +796,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
ara_req_d.op = ara_pkg::VMSBC;

// Check whether we can access vs1 and vs2
unique case (ara_req_d.emul)
LMUL_2:
if ((insn.varith_type.rs2 & 5'b00001) == (insn.varith_type.rd & 5'b00001))
illegal_insn = 1'b1;
LMUL_4:
if ((insn.varith_type.rs2 & 5'b00011) == (insn.varith_type.rd & 5'b00011))
illegal_insn = 1'b1;
LMUL_8:
if ((insn.varith_type.rs2 & 5'b00111) == (insn.varith_type.rd & 5'b00111))
illegal_insn = 1'b1;
default: if (insn.varith_type.rs2 == insn.varith_type.rd) illegal_insn = 1'b1;
endcase
if (insn.varith_type.rs2 == insn.varith_type.rd) illegal_insn = 1'b1;
end
6'b011000: begin
ara_req_d.op = ara_pkg::VMSEQ;
Expand Down Expand Up @@ -1007,18 +955,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
ara_req_d.op = ara_pkg::VMADC;

// Check whether we can access vs1 and vs2
unique case (ara_req_d.emul)
LMUL_2:
if ((insn.varith_type.rs2 & 5'b00001) == (insn.varith_type.rd & 5'b00001))
illegal_insn = 1'b1;
LMUL_4:
if ((insn.varith_type.rs2 & 5'b00011) == (insn.varith_type.rd & 5'b00011))
illegal_insn = 1'b1;
LMUL_8:
if ((insn.varith_type.rs2 & 5'b00111) == (insn.varith_type.rd & 5'b00111))
illegal_insn = 1'b1;
default: if (insn.varith_type.rs2 == insn.varith_type.rd) illegal_insn = 1'b1;
endcase
if (insn.varith_type.rs2 == insn.varith_type.rd) illegal_insn = 1'b1;
end
6'b011000: begin
ara_req_d.op = ara_pkg::VMSEQ;
Expand Down

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