mcyclecfg.OF and minstretcfg.OF

[sorear]

I'm extremely late to the party but I can't find where this was previously discussed. "cycles" and "instructions" are two of the most useful events for perf-record, and since instret is deterministic stopping at an instruction count would enable portable reverse-execution tools that jump to known positions in the instruction stream (icount triggers are less useful for this since they are limited to 2^14 instructions and interrupts are counted as instructions).

Is there an analysis on providing interrupt enables and overflow flags for cycle and instret to bring them up to parity with the non-architectural counters?

[atishp04]

Yes. LCOFI support for cycles/instret was discussed multiple times. It was concluded that vendor implementation should support that via hpmcounters. Any 2 hpmcounter can be reserved for cycle/instret to allow overflow/interrupt. Current Qemu implementation follows that approach as well. @bcstrongx for visibility.

[bcstrongx]

Right. In discussions I've had with Greg and Andrew, there was a strong desire to have dedicated counters, for cycles and instructions retired, that even user software can reliably do two reads and compute a delta. If these counters were used for sampling, there would be a risk of a sample being collected between the reads, and the counter being re-initialized. For this reason sampling on these events requires using the HPM counters. We probably should look at standardizing some fixed-event HPMs for these events, since they are commonly used and it's a waste of (expensive) programmable counter resources to use them on these simple events. But we don't have that yet.