Merge #30

30: add riscv32i target r=Disasm a=sbourdeauducq This adds support for the simplest RISC-V processor possible, which is useful e.g. for experimenting with FPGA softcore implementations. Co-authored-by: Sebastien Bourdeauducq <[email protected]>
rust-embedded · Jul 27, 2019 · 4094a32 · 4094a32
2 parents 7f1e4a5 + b53e0a5
commit 4094a32
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diff --git a/assemble.sh b/assemble.sh
@@ -7,6 +7,9 @@ crate=riscv
 # remove existing blobs because otherwise this will append object files to the old blobs
 rm -f bin/*.a
 
+riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32i asm.S -o bin/$crate.o
+ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o
+
 riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imc asm.S -o bin/$crate.o
 ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
 ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o

diff --git a/bin/riscv32i-unknown-none-elf.a b/bin/riscv32i-unknown-none-elf.a