Skip to content

Commit

Permalink
Merge #30
Browse files Browse the repository at this point in the history
30: Fix docs, add MSRV policy, bump version r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <[email protected]>
  • Loading branch information
bors[bot] and Disasm committed Mar 11, 2019
2 parents 816b3ce + e85c1fb commit fdc92f3
Show file tree
Hide file tree
Showing 5 changed files with 14 additions and 5 deletions.
3 changes: 3 additions & 0 deletions riscv-rt/.travis.yml
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@ language: rust
rust:
- nightly
- stable
- 1.31.0 # MSRV

env:
- TARGET=x86_64-unknown-linux-gnu
Expand All @@ -15,6 +16,8 @@ matrix:
exclude:
- rust: stable
env: TARGET=riscv64imac-unknown-none-elf
- rust: 1.31.0 # MSRV
env: TARGET=riscv64imac-unknown-none-elf


before_install: set -e
Expand Down
2 changes: 1 addition & 1 deletion riscv-rt/Cargo.toml
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
[package]
name = "riscv-rt"
version = "0.4.0"
version = "0.5.0"
repository = "https:/rust-embedded/riscv-rt"
authors = ["The RISC-V Team <[email protected]>"]
categories = ["embedded", "no-std"]
Expand Down
2 changes: 1 addition & 1 deletion riscv-rt/macros/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -28,4 +28,4 @@ version = "0.5.5"
default-features = false

[dev-dependencies]
riscv-rt = { path = "..", version = "0.4.0" }
riscv-rt = { path = "..", version = "0.5.0" }
5 changes: 2 additions & 3 deletions riscv-rt/macros/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -29,9 +29,8 @@ use proc_macro::TokenStream;
/// private modules between the item and the root of the crate); if the item is in the root of the
/// crate you'll be fine. This reachability restriction doesn't apply to Rust 1.31 and newer releases.
///
/// The specified function will be called by the reset handler *after* RAM has been initialized. In
/// the case of the `thumbv7em-none-eabihf` target the FPU will also be enabled before the function
/// is called.
/// The specified function will be called by the reset handler *after* RAM has been initialized.
/// If present, the FPU will also be enabled before the function is called.
///
/// The type of the specified function must be `[unsafe] fn() -> !` (never ending function)
///
Expand Down
7 changes: 7 additions & 0 deletions riscv-rt/src/lib.rs
Original file line number Diff line number Diff line change
@@ -1,5 +1,12 @@
//! Minimal startup / runtime for RISC-V CPU's
//!
//! # Minimum Supported Rust Version (MSRV)
//!
//! This crate is guaranteed to compile on stable Rust 1.31 and up. It *might*
//! compile with older versions but that may change in any new patch release.
//! Note that `riscv64imac-unknown-none-elf` and `riscv64gc-unknown-none-elf` targets
//! are not supported on stable yet.
//!
//! # Features
//!
//! This crate provides
Expand Down

0 comments on commit fdc92f3

Please sign in to comment.