Examples for Yosys Synthesis and Equivalence Verification

Yosys is an OpenSource Tool mainly for Synthesis, but also provides equivalence checks
Comparing two Verilog Designs
Comparing Verilog against VHDL
- Using GHDL and ghdl-yosys-plugin

Examples

formal

Some testcases to work with equivalence check in Yosys,

based on Yosys Isse #639, with some modifications.
Register Files

synth

Some examples using the Yosys GHDL plugin