Update JTAG logic and testing infrastracture

constraints/profpga-xc7v2000t-epochs0-gf12/profpga-xc7v2000t-epochs0-gf12-chip-emu-eth-constraints.xdc

@@ -33,3 +33,5 @@ set clk_emu_elab [get_clocks -of_objects [get_nets clk_emu_p]]
 set_clock_groups -asynchronous -group [get_clocks erx_clk] -group [get_clocks $clk_emu_elab]
 
 set_clock_groups -asynchronous -group [get_clocks etx_clk] -group [get_clocks $clk_emu_elab]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets chip_i/tclk_pad/xcv.x0/tclk_0]

rtl/sockets/jtag/apb2jtag.vhd

@@ -1,4 +1,4 @@
--- Copyright (c) 2011-2021 Columbia University, System Level Design Group
+-- Copyright (c) 2011-2022 Columbia University, System Level Design Group
 -- SPDX-License-Identifier: Apache-2.0
 
 library ieee;
@@ -45,6 +45,7 @@ entity apb2jtag is
  piso_c : in std_logic;
  piso_l : in std_logic;
  piso_en : in std_logic;
+ load_invld : in std_logic;
  tdi : out std_logic);
 end apb2jtag;
 
@@ -54,7 +55,7 @@ architecture rtl of apb2jtag is
  constant reg_a2j_pindex : integer range 0 to NAPBSLV - 1 := 0;
  constant reg_a2j_paddr : integer range 0 to 4095 := 16#100#;
  constant reg_a2j_pmask : integer range 0 to 4095 := 16#FFF#;
-
+ constant invld_flit : std_logic_vector(NOC_FLIT_SIZE+8 downto 0) := X"000000000000000000" & "101";
  signal this_paddr, this_pmask : integer range 0 to 4095;
  signal this_pirq : integer range 0 to 15;
 
@@ -67,7 +68,7 @@ architecture rtl of apb2jtag is
  signal tdi_in : std_logic;
 
  signal full_fifo, en_fifo_in, ack : std_logic_vector(5 downto 0);
- signal trace_in, fifo_out  : std_logic_vector(74 downto 0);
+ signal trace_in, fifo_out, piso_in : std_logic_vector(74 downto 0);
 
  attribute mark_debug : string;
 
@@ -133,7 +134,7 @@ begin
  async_fifo_01 : inferred_async_fifo
  generic map (
  g_data_width => NOC_FLIT_SIZE+9,
- g_size => 40)
+ g_size => 200)
  port map (
  rst_wr_n_i => rst,
  clk_wr_i => main_clk,
@@ -160,6 +161,7 @@ begin
  F => tracein1(0),
  X => fifo_out);
 
+ piso_in <= fifo_out when load_invld = '0' else invld_flit;
 
  piso0 : piso_jtag
  generic map(sz => NOC_FLIT_SIZE+9,
@@ -169,7 +171,7 @@ begin
  clk => tclk,
  clear => piso_c,
  load => piso_l,
- A => fifo_out,
+ A => piso_in,
  shift_en => piso_en,
  Y => tdi_in,
  done => open);

rtl/sockets/jtag/apb2jtag_reg.vhd

@@ -1,5 +1,4 @@
-
--- Copyright (c) 2011-2021 Columbia University, System Level Design Group
+-- Copyright (c) 2011-2022 Columbia University, System Level Design Group
 -- SPDX-License-Identifier: Apache-2.0
 
 library ieee;
@@ -62,7 +61,6 @@ architecture arch of apb2jtag_reg is
  attribute mark_debug of r : signal is "true";
  attribute mark_debug of sample : signal is "true";
 
-
 begin
 
  apbo.prdata <= (others => '0');
@@ -106,6 +104,7 @@ begin
  v.write_en := '0';
  if rstn = '1' and apbreq = '1' and apbi.psel(pindex) = '1' then
  v.state := aread;
+ v.write_en := '1';
  end if;
 
 

rtl/sockets/jtag/counter_jtag.vhd

@@ -1,4 +1,4 @@
--- Copyright (c) 2011-2021 Columbia University, System Level Design Group
+-- Copyright (c) 2011-2022 Columbia University, System Level Design Group
 -- SPDX-License-Identifier: Apache-2.0
 library ieee;
 use ieee.std_logic_1164.all;

rtl/sockets/jtag/demux_1to2.vhd

@@ -1,4 +1,4 @@
--- Copyright (c) 2011-2021 Columbia University, System Level Design Group
+-- Copyright (c) 2011-2022 Columbia University, System Level Design Group
 -- SPDX-License-Identifier: Apache-2.0
 library ieee;
 use ieee.std_logic_1164.all;

rtl/sockets/jtag/demux_1to6.vhd

@@ -1,4 +1,4 @@
--- Copyright (c) 2011-2021 Columbia University, System Level Design Group
+-- Copyright (c) 2011-2022 Columbia University, System Level Design Group
 -- SPDX-License-Identifier: Apache-2.0
 library ieee;
 use ieee.std_logic_1164.all;

rtl/sockets/jtag/demux_1to6_vs.vhd

@@ -1,4 +1,4 @@
--- Copyright (c) 2011-2021 Columbia University, System Level Design Group
+-- Copyright (c) 2011-2022 Columbia University, System Level Design Group
 -- SPDX-License-Identifier: Apache-2.0
 library ieee;
 use ieee.std_logic_1164.all;

rtl/sockets/jtag/fpga_proxy_jtag.vhd

@@ -1,4 +1,4 @@
--- Copyright (c) 2011-2021 Columbia University, System Level Design Group
+-- Copyright (c) 2011-2022 Columbia University, System Level Design Group
 -- SPDX-License-Identifier: Apache-2.0
 
 library ieee;
@@ -90,6 +90,7 @@ architecture rtl of fpga_proxy_jtag is
  signal testin_piso_en, count_clear, source_sipo_clear : std_logic;
  signal testout_sipo_clear, count_en, ack2apb : std_logic;
  signal ack2apb_r, apbreq : std_logic;
+ signal load_invld : std_logic;
  signal sel_tdo : std_logic_vector(1 downto 0);
 
  signal source_sipo_out, req_flit, wr_flit, empty_fifo : std_logic_vector(5 downto 0);
@@ -155,18 +156,6 @@ begin
  apbo(1)<=apbo1;
 
  ack_r <= '1';
-
- -- process (apbi, ack2apb, ack2apb_r)
- -- begin
- -- if apbi.psel(0) = '1' then
- -- ack_r <= ack2apb;
- -- elsif apbi.psel(1) = '1' then
- -- ack_r <= ack2apb_r;
- -- else
- -- ack_r <= '0';
- -- end if;
- -- end process;
-
 
  apb2jtagdev : apb2jtag
  port map(
@@ -175,14 +164,14 @@ begin
  main_clk => main_clk,
  apbi => apbi,
  apbo => apbo0,
- -- ack_w => ack,
  apbreq => apbreq,
  ack2apb => ack2apb,
  req_flit => req_flit,
  empty_fifo => empty_fifo,
  piso_c => testin_piso_clear,
  piso_l => testin_piso_load,
  piso_en => testin_piso_en,
+ load_invld => load_invld,
  tdi => tdi);
 
  jtag2apbdev : jtag2apb
@@ -225,6 +214,7 @@ begin
 
  testin_piso_clear <= '0';
  testin_piso_load <= '0';
+ load_invld <= '0';
  testin_piso_en <= '0';
 
  testout_sipo_en <= '0';
@@ -271,6 +261,10 @@ begin
  req_flit <= source_sipo_out;
  testin_piso_load <= '1';
  v.state := inject;
+ else
+ testin_piso_load <='1';
+ load_invld <= '1';
+ v.state := inject;
  end if;
 
  when inject => source_sipo_clear <= '1';

rtl/sockets/jtag/jtag2apb.vhd

@@ -1,4 +1,4 @@
--- Copyright (c) 2011-2021 Columbia University, System Level Design Group
+-- Copyright (c) 2011-2022 Columbia University, System Level Design Group
 -- SPDX-License-Identifier: Apache-2.0
 
 library ieee;
@@ -104,7 +104,7 @@ begin
  async_fifo_01 : inferred_async_fifo
  generic map (
  g_data_width => NOC_FLIT_SIZE+8,
- g_size => 20)
+ g_size => 200)
  port map (
  rst_wr_n_i => rst,
  clk_wr_i => tclk,

rtl/sockets/jtag/jtag2apb_reg.vhd

@@ -1,4 +1,4 @@
--- Copyright (c) 2011-2021 Columbia University, System Level Design Group
+-- Copyright (c) 2011-2022 Columbia University, System Level Design Group
 -- SPDX-License-Identifier: Apache-2.0
 
 library ieee;
@@ -181,7 +181,6 @@ begin
  readdata <= (others => '0');
  readd <= (others => '0');
 
- -- if (apbi.psel(pindex) = '1' and apbi.penable = '1' and apbi.pwrite = '0' and read_en = '1' and r.free(DEV_START) = '0') then
  if (apbi.psel(pindex) = '1' and apbi.penable = '1' and r.free(DEV_START)='0' and apbi.pwrite='0' and read_en='1') then
 
  readd(idx) <= '1';

rtl/sockets/jtag/jtag_apb_config.vhd

@@ -0,0 +1,120 @@
+-- Copyright (c) 2011-2021 Columbia University, System Level Design Group
+-- SPDX-License-Identifier: Apache-2.0
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.esp_global.all;
+use work.amba.all;
+use work.stdlib.all;
+use work.sld_devices.all;
+use work.devices.all;
+use work.gencomp.all;
+use work.leon3.all;
+use work.ariane_esp_pkg.all;
+use work.misc.all;
+-- pragma translate_off
+use work.sim.all;
+library unisim;
+use unisim.all;
+-- pragma translate_on
+use work.monitor_pkg.all;
+use work.sldacc.all;
+use work.nocpackage.all;
+use work.tile.all;
+use work.cachepackage.all;
+use work.coretypes.all;
+use work.grlib_config.all;
+use work.socmap.all;
+use work.jtag_pkg.all;
+
+
+entity jtag_apb_config is
+ generic (
+ DEF_TILE : std_logic_vector(31 downto 0) := (others => '0');
+ DEF_TMS : std_logic_vector(31 downto 0) := (others => '0'));
+ port (
+ rst : in std_ulogic;
+ main_clk : in std_ulogic;
+ ahbsi : in ahb_slv_in_type;
+ ahbso : out ahb_slv_out_type;
+ out_p : out std_logic_vector(31 downto 0);
+ out_p1 : out std_logic_vector(31 downto 0));
+
+end;
+
+
+architecture rtl of jtag_apb_config is
+
+ constant CFG_APBADDR_FP : integer := 16#200#;
+ constant ahb2apb_hmask_fp : integer := 16#FFE#;
+ constant ahb2apb_hindex_fp : integer := 1;
+
+ constant apb_slv_mask : std_logic_vector(0 to NAPBSLV - 1) := (
+ 0 => '1', --2
+ 1 => '1', --2
+ -- 2 => '1', --2
+ others => '0');
+
+-- APB BUS
+ signal apbi : apb_slv_in_type;
+ signal apbo : apb_slv_out_vector;
+ signal apbo0 : apb_slv_out_type;
+ signal apbo1 : apb_slv_out_type;
+ signal ack_r : std_logic;
+ signal ack2apb_r, apbreq : std_logic;
+
+begin
+
+ apb_ctrl_norm : patient_apbctrl -- AHB/APB bridge
+ generic map
+ (hindex => ahb2apb_hindex_fp,
+ haddr => CFG_APBADDR_FP,
+ hmask => ahb2apb_hmask_fp,
+ nslaves => NAPBSLV,
+ remote_apb => apb_slv_mask)
+ port map
+ (rst,
+ main_clk,
+ ahbsi,
+ ahbso,
+ apbi,
+ apbo,
+ apbreq,
+ ack_r);
+
+ no_pslv_gen : for i in 2 to NAPBSLV - 1 generate
+ apbo(i)<=apb_none;
+ end generate no_pslv_gen;
+
+ apbo(0)<=apbo0;
+ apbo(1)<=apbo1;
+ ack_r <= '1';
+
+ tmsregdev : jtag_apb_slv_config
+ generic map (
+ lpindex => 0,
+ DEF_TMS => DEF_TMS)
+ port map(
+ rst => rst,
+ main_clk => main_clk,
+ apbi => apbi,
+ apbo => apbo0,
+ apbreq => apbreq,
+ out_p => out_p);
+
+ jtag_tileregdev : jtag_apb_slv_config
+ generic map (
+ lpindex => 1,
+ DEF_TMS => DEF_TILE)
+ port map(
+ rst => rst,
+ main_clk => main_clk,
+ apbi => apbi,
+ apbo => apbo1,
+ apbreq => apbreq,
+ out_p => out_p1);
+
+end;
+