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[2021.1.1]
Added
- Enable ESP cache hierarchy with Ibex core (The result exist a quite strange error when using caches. (ibex core) #92)
Fixed
Cache hierarchy
- Fix endianness of the SystemC implementation for instances of ESP using a RISC-V core (The result exist a quite strange error when using caches. (ibex core) #92)
Ibex
- Use Xilinx primitives for Ibex implementation on FPGA
- Disable ESP L2 invalidation master port on AHB bus (The result exist a quite strange error when using caches. (ibex core) #92)
Infrastructure
- Fix link update of the object dump used in full-system RTL simulations (The RTL simulation with Ariane core has "Illegal Instruction" error. (Ariane core) #93)
- Save HLS log files for the cache hierarchy into log folder
- Restore optimized floorplanning for proFPGA XCVU440 (proFPGA-xcvu440 floorplanning scripts have incorrect paths after restructuring #94)