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Asap2 direct 3.3 next #450

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01a3701
switchdev: Use flags when checking parent HW id
hadarhenzion Dec 7, 2016
040ad25
net/mlx5e: Avoid recursion when checking switchdev parent HW id
hadarhenzion Dec 7, 2016
00eca51
net/mlx5e: Disallow TC offloading of unsupported match/action combina…
ogerlitz Jun 11, 2017
3f7c3d5
net/mlx5: Fix counter list hardware structure
Jul 10, 2017
b58f804
net/mlx5: Increase the maximum flow counters supported
Jul 9, 2017
3d2d9a7
net/mlx5: Enlarge the NIC TC offload table size
ogerlitz Jan 12, 2017
589fa8d
net/mlx5: Convert linear search for free index to ida
matanb10 May 28, 2017
9918e6b
net/mlx5: Don't store reserved part in FTEs and FGs
matanb10 Aug 7, 2017
b9366f8
net/mlx5: Add hash table to search FTEs in a flow-group
matanb10 May 28, 2017
03f69f3
net/mlx5: Add hash table for flow groups in flow table
matanb10 May 28, 2017
f3469a3
net/mlx5: Add tracepoints
matanb10 May 28, 2017
4a9b337
net/mlx5: Fix creating a new FTE when an existing but full FTE exists
matanb10 Aug 10, 2017
70ecb50
net/mlx5e: Check encap state when creating flow table entry
w1ldptr Aug 8, 2017
b70b347
net/mlx5e: IPoIB, Fix KASAN error when releasing rdma netdev
roidayan Aug 21, 2017
57ce54c
net/mlx5e: Properly resolve TC offloaded ipv6 vxlan tunnel source add…
Aug 22, 2017
699606d
net/mlx5: E-Switch, Unload the representors in the correct order
Aug 1, 2017
4b007dd
idr: Add new APIs to support unsigned long
mishuang2017 Aug 17, 2017
fdff7db
net/sched: Change cls_flower to use IDR
mishuang2017 Aug 17, 2017
2583f3c
net/sched: Change act_api and act_xxx modules to use IDR
mishuang2017 Aug 22, 2017
15390b2
net/sched: Change tc_action refcnt and bindcnt to atomic
mishuang2017 Aug 24, 2017
a18ec50
net/sched: Use action array instead of action list as parameter
mishuang2017 Aug 24, 2017
4d3f831
net/mlx5e: Fix erroneous freeing of encap header buffer
Sep 5, 2017
9162e9f
net_sched: remove cls_flower idr on failure
congwang Sep 20, 2017
f031786
net/mlx5e: Fix double encap cleanup
roidayan Oct 1, 2017
016b216
net/mlx5: Add hairpin definitions to the FW API
ogerlitz Jun 25, 2017
744be84
net/mlx5e: Hairpin low-level objects setup
ogerlitz Jun 25, 2017
ab425d9
net/mlx5e: Support offloading TC NIC hairpin flows
ogerlitz Jun 25, 2017
e8e73b6
Revert "net/mlx5e: Fix double encap cleanup"
roidayan Oct 26, 2017
c21f1a1
net/mlx5e: Properly deal with encap flows add/del under neigh update
ogerlitz Oct 17, 2017
ff00ea4
net: sched: don't use GFP_KERNEL under spin lock
Sep 5, 2017
b46a1c3
net/mlx5e: Enable stateless offloads for VF representor netdevs
Nov 14, 2017
27b3360
net/mlx5e: Change VF representor's RQ size and type
Nov 15, 2017
5ef7c32
Revert "net/mlx5e: Change VF representor's RQ size and type"
roidayan Nov 30, 2017
589d3f7
net/mlx5: Increased the representor's RQ size
Nov 5, 2017
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5 changes: 4 additions & 1 deletion drivers/net/ethernet/mellanox/mlx5/core/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,8 @@ subdir-ccflags-y += -I$(src)
mlx5_core-y := main.o cmd.o debugfs.o fw.o eq.o uar.o pagealloc.o \
health.o mcg.o cq.o srq.o alloc.o qp.o port.o mr.o pd.o \
mad.o transobj.o vport.o sriov.o fs_cmd.o fs_core.o \
fs_counters.o rl.o lag.o dev.o wq.o lib/gid.o
fs_counters.o rl.o lag.o dev.o wq.o lib/gid.o \
diag/fs_tracepoint.o

mlx5_core-$(CONFIG_MLX5_ACCEL) += accel/ipsec.o

Expand All @@ -22,3 +23,5 @@ mlx5_core-$(CONFIG_MLX5_CORE_IPOIB) += ipoib/ipoib.o ipoib/ethtool.o

mlx5_core-$(CONFIG_MLX5_EN_IPSEC) += en_accel/ipsec.o en_accel/ipsec_rxtx.o \
en_accel/ipsec_stats.o

CFLAGS_tracepoint.o := -I$(src)
1 change: 1 addition & 0 deletions drivers/net/ethernet/mellanox/mlx5/core/diag/Makefile
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
subdir-ccflags-y += -I$(src)/..
261 changes: 261 additions & 0 deletions drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,261 @@
/*
* Copyright (c) 2017, Mellanox Technologies. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/

#define CREATE_TRACE_POINTS

#include "fs_tracepoint.h"
#include <linux/stringify.h>

#define DECLARE_MASK_VAL(type, name) struct {type m; type v; } name
#define MASK_VAL(type, spec, name, mask, val, fld) \
DECLARE_MASK_VAL(type, name) = \
{.m = MLX5_GET(spec, mask, fld),\
.v = MLX5_GET(spec, val, fld)}
#define MASK_VAL_BE(type, spec, name, mask, val, fld) \
DECLARE_MASK_VAL(type, name) = \
{.m = MLX5_GET_BE(type, spec, mask, fld),\
.v = MLX5_GET_BE(type, spec, val, fld)}
#define GET_MASKED_VAL(name) (name.m & name.v)

#define GET_MASK_VAL(name, type, mask, val, fld) \
(name.m = MLX5_GET(type, mask, fld), \
name.v = MLX5_GET(type, val, fld), \
name.m & name.v)
#define PRINT_MASKED_VAL(name, p, format) { \
if (name.m) \
trace_seq_printf(p, __stringify(name) "=" format " ", name.v); \
}
#define PRINT_MASKED_VALP(name, cast, p, format) { \
if (name.m) \
trace_seq_printf(p, __stringify(name) "=" format " ", \
(cast)&name.v);\
}

static void print_lyr_2_4_hdrs(struct trace_seq *p,
const u32 *mask, const u32 *value)
{
#define MASK_VAL_L2(type, name, fld) \
MASK_VAL(type, fte_match_set_lyr_2_4, name, mask, value, fld)
DECLARE_MASK_VAL(u64, smac) = {
.m = MLX5_GET(fte_match_set_lyr_2_4, mask, smac_47_16) << 16 |
MLX5_GET(fte_match_set_lyr_2_4, mask, smac_15_0),
.v = MLX5_GET(fte_match_set_lyr_2_4, value, smac_47_16) << 16 |
MLX5_GET(fte_match_set_lyr_2_4, value, smac_15_0)};
DECLARE_MASK_VAL(u64, dmac) = {
.m = MLX5_GET(fte_match_set_lyr_2_4, mask, dmac_47_16) << 16 |
MLX5_GET(fte_match_set_lyr_2_4, mask, dmac_15_0),
.v = MLX5_GET(fte_match_set_lyr_2_4, value, dmac_47_16) << 16 |
MLX5_GET(fte_match_set_lyr_2_4, value, dmac_15_0)};
MASK_VAL_L2(u16, ethertype, ethertype);

PRINT_MASKED_VALP(smac, u8 *, p, "%pM");
PRINT_MASKED_VALP(dmac, u8 *, p, "%pM");
PRINT_MASKED_VAL(ethertype, p, "%04x");

if (ethertype.m == 0xffff) {
if (ethertype.v == ETH_P_IP) {
#define MASK_VAL_L2_BE(type, name, fld) \
MASK_VAL_BE(type, fte_match_set_lyr_2_4, name, mask, value, fld)
MASK_VAL_L2_BE(u32, src_ipv4,
src_ipv4_src_ipv6.ipv4_layout.ipv4);
MASK_VAL_L2_BE(u32, dst_ipv4,
dst_ipv4_dst_ipv6.ipv4_layout.ipv4);

PRINT_MASKED_VALP(src_ipv4, typeof(&src_ipv4.v), p,
"%pI4");
PRINT_MASKED_VALP(dst_ipv4, typeof(&dst_ipv4.v), p,
"%pI4");
} else if (ethertype.v == ETH_P_IPV6) {
static const struct in6_addr full_ones = {
.in6_u.u6_addr32 = {htonl(0xffffffff),
htonl(0xffffffff),
htonl(0xffffffff),
htonl(0xffffffff)},
};
DECLARE_MASK_VAL(struct in6_addr, src_ipv6);
DECLARE_MASK_VAL(struct in6_addr, dst_ipv6);

memcpy(src_ipv6.m.in6_u.u6_addr8,
MLX5_ADDR_OF(fte_match_set_lyr_2_4, mask,
src_ipv4_src_ipv6.ipv6_layout.ipv6),
sizeof(src_ipv6.m));
memcpy(dst_ipv6.m.in6_u.u6_addr8,
MLX5_ADDR_OF(fte_match_set_lyr_2_4, mask,
dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
sizeof(dst_ipv6.m));
memcpy(src_ipv6.v.in6_u.u6_addr8,
MLX5_ADDR_OF(fte_match_set_lyr_2_4, value,
src_ipv4_src_ipv6.ipv6_layout.ipv6),
sizeof(src_ipv6.v));
memcpy(dst_ipv6.v.in6_u.u6_addr8,
MLX5_ADDR_OF(fte_match_set_lyr_2_4, value,
dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
sizeof(dst_ipv6.v));

if (!memcmp(&src_ipv6.m, &full_ones, sizeof(full_ones)))
trace_seq_printf(p, "src_ipv6=%pI6 ",
&src_ipv6.v);
if (!memcmp(&dst_ipv6.m, &full_ones, sizeof(full_ones)))
trace_seq_printf(p, "dst_ipv6=%pI6 ",
&dst_ipv6.v);
}
}

#define PRINT_MASKED_VAL_L2(type, name, fld, p, format) {\
MASK_VAL_L2(type, name, fld); \
PRINT_MASKED_VAL(name, p, format); \
}

PRINT_MASKED_VAL_L2(u8, ip_protocol, ip_protocol, p, "%02x");
PRINT_MASKED_VAL_L2(u16, tcp_flags, tcp_flags, p, "%x");
PRINT_MASKED_VAL_L2(u16, tcp_sport, tcp_sport, p, "%u");
PRINT_MASKED_VAL_L2(u16, tcp_dport, tcp_dport, p, "%u");
PRINT_MASKED_VAL_L2(u16, udp_sport, udp_sport, p, "%u");
PRINT_MASKED_VAL_L2(u16, udp_dport, udp_dport, p, "%u");
PRINT_MASKED_VAL_L2(u16, first_vid, first_vid, p, "%04x");
PRINT_MASKED_VAL_L2(u8, first_prio, first_prio, p, "%x");
PRINT_MASKED_VAL_L2(u8, first_cfi, first_cfi, p, "%d");
PRINT_MASKED_VAL_L2(u8, ip_dscp, ip_dscp, p, "%02x");
PRINT_MASKED_VAL_L2(u8, ip_ecn, ip_ecn, p, "%x");
PRINT_MASKED_VAL_L2(u8, cvlan_tag, cvlan_tag, p, "%d");
PRINT_MASKED_VAL_L2(u8, svlan_tag, svlan_tag, p, "%d");
PRINT_MASKED_VAL_L2(u8, frag, frag, p, "%d");
}

static void print_misc_parameters_hdrs(struct trace_seq *p,
const u32 *mask, const u32 *value)
{
#define MASK_VAL_MISC(type, name, fld) \
MASK_VAL(type, fte_match_set_misc, name, mask, value, fld)
#define PRINT_MASKED_VAL_MISC(type, name, fld, p, format) {\
MASK_VAL_MISC(type, name, fld); \
PRINT_MASKED_VAL(name, p, format); \
}
DECLARE_MASK_VAL(u64, gre_key) = {
.m = MLX5_GET(fte_match_set_misc, mask, gre_key_h) << 8 |
MLX5_GET(fte_match_set_misc, mask, gre_key_l),
.v = MLX5_GET(fte_match_set_misc, value, gre_key_h) << 8 |
MLX5_GET(fte_match_set_misc, value, gre_key_l)};

PRINT_MASKED_VAL(gre_key, p, "%llu");
PRINT_MASKED_VAL_MISC(u32, source_sqn, source_sqn, p, "%u");
PRINT_MASKED_VAL_MISC(u16, source_port, source_port, p, "%u");
PRINT_MASKED_VAL_MISC(u8, outer_second_prio, outer_second_prio,
p, "%u");
PRINT_MASKED_VAL_MISC(u8, outer_second_cfi, outer_second_cfi, p, "%u");
PRINT_MASKED_VAL_MISC(u16, outer_second_vid, outer_second_vid, p, "%u");
PRINT_MASKED_VAL_MISC(u8, inner_second_prio, inner_second_prio,
p, "%u");
PRINT_MASKED_VAL_MISC(u8, inner_second_cfi, inner_second_cfi, p, "%u");
PRINT_MASKED_VAL_MISC(u16, inner_second_vid, inner_second_vid, p, "%u");

PRINT_MASKED_VAL_MISC(u8, outer_second_cvlan_tag,
outer_second_cvlan_tag, p, "%u");
PRINT_MASKED_VAL_MISC(u8, inner_second_cvlan_tag,
inner_second_cvlan_tag, p, "%u");
PRINT_MASKED_VAL_MISC(u8, outer_second_svlan_tag,
outer_second_svlan_tag, p, "%u");
PRINT_MASKED_VAL_MISC(u8, inner_second_svlan_tag,
inner_second_svlan_tag, p, "%u");

PRINT_MASKED_VAL_MISC(u8, gre_protocol, gre_protocol, p, "%u");

PRINT_MASKED_VAL_MISC(u32, vxlan_vni, vxlan_vni, p, "%u");
PRINT_MASKED_VAL_MISC(u32, outer_ipv6_flow_label, outer_ipv6_flow_label,
p, "%x");
PRINT_MASKED_VAL_MISC(u32, inner_ipv6_flow_label, inner_ipv6_flow_label,
p, "%x");
}

const char *parse_fs_hdrs(struct trace_seq *p,
u8 match_criteria_enable,
const u32 *mask_outer,
const u32 *mask_misc,
const u32 *mask_inner,
const u32 *value_outer,
const u32 *value_misc,
const u32 *value_inner)
{
const char *ret = trace_seq_buffer_ptr(p);

if (match_criteria_enable &
1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS) {
trace_seq_printf(p, "[outer] ");
print_lyr_2_4_hdrs(p, mask_outer, value_outer);
}

if (match_criteria_enable &
1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS) {
trace_seq_printf(p, "[misc] ");
print_misc_parameters_hdrs(p, mask_misc, value_misc);
}
if (match_criteria_enable &
1 << MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS) {
trace_seq_printf(p, "[inner] ");
print_lyr_2_4_hdrs(p, mask_inner, value_inner);
}
trace_seq_putc(p, 0);
return ret;
}

const char *parse_fs_dst(struct trace_seq *p,
const struct mlx5_flow_destination *dst,
u32 counter_id)
{
const char *ret = trace_seq_buffer_ptr(p);

switch (dst->type) {
case MLX5_FLOW_DESTINATION_TYPE_VPORT:
trace_seq_printf(p, "vport=%u\n", dst->vport_num);
break;
case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE:
trace_seq_printf(p, "ft=%p\n", dst->ft);
break;
case MLX5_FLOW_DESTINATION_TYPE_TIR:
trace_seq_printf(p, "tir=%u\n", dst->tir_num);
break;
case MLX5_FLOW_DESTINATION_TYPE_COUNTER:
trace_seq_printf(p, "counter_id=%u\n", counter_id);
break;
}

trace_seq_putc(p, 0);
return ret;
}

EXPORT_TRACEPOINT_SYMBOL(mlx5_fs_add_fg);
EXPORT_TRACEPOINT_SYMBOL(mlx5_fs_del_fg);
EXPORT_TRACEPOINT_SYMBOL(mlx5_fs_set_fte);
EXPORT_TRACEPOINT_SYMBOL(mlx5_fs_del_fte);
EXPORT_TRACEPOINT_SYMBOL(mlx5_fs_add_rule);
EXPORT_TRACEPOINT_SYMBOL(mlx5_fs_del_rule);

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