AVR support #2021
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AVR support #2021
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glennsec
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aquynh
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Oct 3, 2024
samples/sample_avr.c
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| break; | ||
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| // Initialize registers | ||
| uint8_t regs[32]; |
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please move all the variable declaration to the beginning of the function
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Thanks for the contribution!
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can you look at the issues of the CI? |
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You need to add Rust bindings manually😅 |
Signed-off-by: Glenn Baker <[email protected]>
Add AVR related definitions into QEMU, make AVR support buildable. [AM: Remove word 'Atmel' from filenames and all elements of code] Suggested-by: Aleksandar Markovic <[email protected]> Signed-off-by: Michael Rolnik <[email protected]> Signed-off-by: Richard Henderson <[email protected]> Signed-off-by: Aleksandar Markovic <[email protected]> Tested-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Aleksandar Markovic <[email protected]> Signed-off-by: Thomas Huth <[email protected]> Message-Id: <[email protected]> [PMD: Fixed @avr tag in qapi/machine.json] Signed-off-by: Philippe Mathieu-Daudé <[email protected]> (cherry picked from commit 42f3ff001339e37df4f13b709d2db00a488ee45c) Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
This is needed because the AVR CPU has separate code and data address spaces that both start from zero. Use 0x08000000 base for Flash memory and 0x00000000 base for CPU registers, IO registers and SRAM as the fast case. Signed-off-by: Glenn Baker <[email protected]>
Separate AVR architectures ("avr5", "avr51", "avr6", etc.) from actual
MCU models. Only list the most representative MCU models.
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
Signed-off-by: Glenn Baker <[email protected]>
glennsec
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done |
Fixed all of those except arm64 & ppc64 failures. The arm64 bits may be fixed by #1935 ? |
There are also macos failures. |
Hi, this is related to the tcg/aarch64 backend issue mentioned in #1908 with proposed fix in #1935. I have another patch suggestion that fixes the issue, as you can see in the last CI run at https:/glennsec/unicorn/actions/runs/11298077207 |
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Hi, this adds support for AVR (#939), while keeping XMEGA bits (with DES instruction) currently separate. This PR is rebased against the current dev branch, while original support was developed and more thoroughly tested against unicorn 2.0.x.