Merge "Merge arm branch into master"

zephyrproject-rtos · Apr 28, 2017 · 9a6d066 · 9a6d066
2 parents 1d36cfb + 3d3adc8
commit 9a6d066
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diff --git a/.gitreview b/.gitreview
@@ -2,3 +2,4 @@
 host=gerrit.zephyrproject.org
 port=29418
 project=zephyr.git
+defaultremote=origin
diff --git a/MAINTAINERS b/MAINTAINERS
@@ -117,7 +117,7 @@ BOARDS/ARM - CC32XX LAUNCHXL
 M: Gil Pitney <[email protected]>
 S: Supported
 F: boards/arm/cc3200_launchxl/
-F: boards/arm/cc3220s_launchxl/
+F: boards/arm/cc3220sf_launchxl/
 
 BOARDS/ARM - NXP FRDM-K64F
 M: Maureen Helm <[email protected]>

diff --git a/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAA b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAA
@@ -12,12 +12,6 @@ config SOC
  string
  default nRF51822_QFAA
 
-config SRAM_SIZE
- default 16
-
-config FLASH_SIZE
- default 256
-
 config ISR_STACK_SIZE
  default 640
 

diff --git a/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAB b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAB
@@ -12,12 +12,6 @@ config SOC
  string
  default nRF51822_QFAB
 
-config SRAM_SIZE
- default 16
-
-config FLASH_SIZE
- default 128
-
 config ISR_STACK_SIZE
  default 640
 

diff --git a/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAC b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAC
@@ -12,10 +12,4 @@ config SOC
  string
  default nRF51822_QFAC
 
-config SRAM_SIZE
- default 32
-
-config FLASH_SIZE
- default 256
-
 endif # SOC_NRF51822_QFAC
diff --git a/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.series b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.series
@@ -19,20 +19,10 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config SYS_POWER_MANAGEMENT
  default y
 
-config SRAM_BASE_ADDRESS
- default 0x20000000
-
-config FLASH_BASE_ADDRESS
- default 0x00000000
-
 config NUM_IRQS
  int
  default 26
 
-config NUM_IRQ_PRIO_BITS
- int
- default 2
-
 if SENSOR
 
 config TEMP_NRF5

diff --git a/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52832_QFAA b/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52832_QFAA
@@ -12,14 +12,6 @@ config SOC
  string
  default nRF52832_QFAA
 
-if !HAS_DTS
-config SRAM_SIZE
- default 64
-
-config FLASH_SIZE
- default 512
-endif
-
 config NUM_IRQS
  int
  default 39

diff --git a/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52840_QIAA b/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52840_QIAA
@@ -12,12 +12,6 @@ config SOC
  string
  default nRF52840_QIAA
 
-config SRAM_SIZE
- default 256
-
-config FLASH_SIZE
- default 1024
-
 config NUM_IRQS
  int
  default 46

diff --git a/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.series b/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.series
@@ -19,16 +19,4 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config SYS_POWER_MANAGEMENT
  default y
 
-if !HAS_DTS
-config SRAM_BASE_ADDRESS
- default 0x20000000
-
-config FLASH_BASE_ADDRESS
- default 0x00000000
-
-config NUM_IRQ_PRIO_BITS
- int
- default 3
-endif
-
 endif # SOC_SERIES_NRF52X
diff --git a/arch/arm/soc/nxp_kinetis/Kconfig b/arch/arm/soc/nxp_kinetis/Kconfig
@@ -58,6 +58,12 @@ config HAS_LPUART
  help
  Set if the low power uart (LPUART) module is present in the SoC.
 
+config HAS_LPSCI
+ bool
+ default n
+ help
+ Set if the low power uart (LPSCI) module is present in the SoC.
+
 if HAS_OSC
 
 choice

diff --git a/arch/arm/soc/nxp_kinetis/kl2x/Kconfig.defconfig.mkl25z4 b/arch/arm/soc/nxp_kinetis/kl2x/Kconfig.defconfig.mkl25z4
@@ -31,7 +31,7 @@ endif # GPIO
 
 if SERIAL
 
-config UART_MCUX
+config UART_MCUX_LPSCI
  def_bool y
 
 endif # SERIAL

diff --git a/arch/arm/soc/nxp_kinetis/kl2x/Kconfig.soc b/arch/arm/soc/nxp_kinetis/kl2x/Kconfig.soc
@@ -15,6 +15,7 @@ config SOC_MKL25Z4
  select HAS_MCUX
  select HAS_OSC
  select HAS_MCG
+ select HAS_LPSCI
 
 endchoice
 

diff --git a/arch/arm/soc/nxp_kinetis/kl2x/soc.c b/arch/arm/soc/nxp_kinetis/kl2x/soc.c
@@ -13,6 +13,8 @@
 #include <fsl_clock.h>
 #include <arch/cpu.h>
 
+#define LPSCI0SRC_MCGFLLCLK (1)
+
 /*******************************************************************************
  * Variables
  ******************************************************************************/
@@ -93,8 +95,8 @@ static ALWAYS_INLINE void clkInit(void)
  CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
  CLOCK_SetSimConfig(&simConfig);
 
-#ifdef CONFIG_UART_MCUX_0
- CLOCK_SetLpsci0Clock(1);
+#ifdef CONFIG_UART_MCUX_LPSCI_0
+ CLOCK_SetLpsci0Clock(LPSCI0SRC_MCGFLLCLK);
 #endif
 }
 

diff --git a/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series b/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series
@@ -42,7 +42,7 @@ endif #SERIAL
 
 if CLOCK_CONTROL
 
-config CLOCK_CONTROL_STM32F4X
+config CLOCK_CONTROL_STM32_CUBE
  def_bool y
 
 endif #CLOCK_CONTROL

diff --git a/arch/arm/soc/st_stm32/stm32f4/Kconfig.soc b/arch/arm/soc/st_stm32/stm32f4/Kconfig.soc
@@ -12,12 +12,12 @@ depends on SOC_SERIES_STM32F4X
 config SOC_STM32F401XE
  bool "STM32F401XE"
 
-config SOC_STM32F411XE
- bool "STM32F411XE"
-
 config SOC_STM32F407XX
  bool "STM32F407XX"
 
+config SOC_STM32F411XE
+ bool "STM32F411XE"
+
 config SOC_STM32F429XX
  bool "STM32F429XX"
 

diff --git a/arch/arm/soc/st_stm32/stm32f4/flash_registers.h b/arch/arm/soc/st_stm32/stm32f4/flash_registers.h
@@ -15,15 +15,6 @@
  * Chapter 3.4: Embedded Flash Memory
  */
 
-enum {
- STM32F4X_FLASH_LATENCY_0 = 0x0,
- STM32F4X_FLASH_LATENCY_1 = 0x1,
- STM32F4X_FLASH_LATENCY_2 = 0x2,
- STM32F4X_FLASH_LATENCY_3 = 0x3,
- STM32F4X_FLASH_LATENCY_4 = 0x4,
- STM32F4X_FLASH_LATENCY_5 = 0x5,
-};
-
 union __flash_acr {
  u32_t val;
  struct {
@@ -48,102 +39,4 @@ struct stm32f4x_flash {
  volatile u32_t optctrl;
 };
 
-/**
- * @brief setup embedded flash controller
- *
- * Configure flash access time latency (wait states) depending on
- * SYSCLK. This code assumes that we're using a supply voltage of
- * 2.7V or higher, for lower voltages this code must be changed.
- *
- * The following tables show the required latency value required for a
- * certain CPU frequency (HCLK) and supply voltage. See the section
- * "Relation between CPU clock frequency and Flash memory read time"
- * in the reference manual for more information.
- *
- * Note that the highest frequency might be limited for other reaasons
- * than wait states, for example the STM32F405xx is limited to 168MHz
- * even with 5 wait states and the highest supply voltage.
- *
- * STM32F401xx:
- *
- * LATENCY | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.4V | 1.8V - 2.1V
- * ------- | ----------- | ----------- | ----------- | -----------
- * 0 | 30 MHz | 24 MHz | 18 MHz | 16 MHz
- * 1 | 60 MHz | 48 MHz | 36 MHz | 32 MHz
- * 2 | 84 MHz | 72 MHz | 54 MHz | 48 MHz
- * 3 | | 84 MHz | 72 MHz | 64 MHz
- * 4 | | | 84 MHz | 80 MHz
- * 5 | | | | 84 MHz
- *
- * STM32F405xx/407xx/415xx/417xx/42xxx/43xxx:
- *
- * LATENCY | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.4V | 1.8V - 2.1V
- * ------- | ----------- | ----------- | ----------- | -----------
- * 0 | 30 MHz | 24 MHz | 22 MHz | 20 MHz
- * 1 | 60 MHz | 48 MHz | 44 MHz | 40 MHz
- * 2 | 90 MHz | 72 MHz | 66 MHz | 60 MHz
- * 3 | 120 MHz | 96 MHz | 88 MHz | 80 MHz
- * 4 | 150 MHz | 120 MHz | 110 MHz | 100 MHz
- * 5 | 180 MHz | 144 MHz | 132 MHz | 120 MHz
- * 6 | | 168 MHz | 154 MHz | 140 MHz
- * 7 | | 180 MHz | 176 MHz | 160 MHz
- * 8 | | | 180 MHz | 168 MHz
- *
- * STM32F411x:
- *
- * LATENCY | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.4V | 1.7V - 2.1V
- * ------- | ----------- | ----------- | ----------- | -----------
- * 0 | 30 MHz | 24 MHz | 18 MHz | 16 MHz
- * 1 | 64 MHz | 48 MHz | 36 MHz | 32 MHz
- * 2 | 90 MHz | 72 MHz | 54 MHz | 48 MHz
- * 3 | 100 MHz | 96 MHz | 72 MHz | 64 MHz
- * 4 | | 100 MHz | 90 MHz | 80 MHz
- * 5 | | | 100 MHz | 96 MHz
- * 6 | | | | 100 MHz
- */
-static inline void __setup_flash(void)
-{
- volatile struct stm32f4x_flash *regs;
- u32_t tmpreg = 0;
-
- regs = (struct stm32f4x_flash *) FLASH_R_BASE;
-
- if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 30000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_0;
- }
-#ifdef CONFIG_SOC_STM32F401XE
- else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 60000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1;
- } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 84000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2;
- }
-#elif CONFIG_SOC_STM32F411XE
- else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 64000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1;
- } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 90000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2;
- } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 100000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_3;
- }
-#elif defined(CONFIG_SOC_STM32F407XX) || defined(CONFIG_SOC_STM32F429XX)
- else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 60000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1;
- } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 90000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2;
- } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 120000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_3;
- } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 150000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_4;
- } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 180000000) {
- regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_5;
- }
-#else
-#error Flash latency configuration for MCU model is missing
-#endif
-
- /* Make sure latency was set */
- tmpreg = regs->acr.bit.latency;
-
-}
-
 #endif /* _STM32F4X_FLASHREGISTERS_H_ */