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Toolchain Compile Error of RISC-V(rv32m1-vega board) #34014
Labels
area: RISCV
RISCV Architecture (32-bit & 64-bit)
bug
The issue is a bug, or the PR is fixing a bug
platform: NXP
NXP
priority: low
Low impact/importance bug
Comments
carlescufi
added
area: RISCV
RISCV Architecture (32-bit & 64-bit)
platform: NXP
NXP
labels
Apr 6, 2021
Glancing at 3.1.3.6 RI5CY Memory map and register descriptions in the RV32M1RM it looks like mtval isn't a supported CSR. |
galak
added a commit
to galak/zephyr
that referenced
this issue
Apr 7, 2021
Don't report MTVAL on the OpenISA RV32M1 SoC as this CSR isn't supported on the SoC. Fixes: zephyrproject-rtos#34014 Signed-off-by: Kumar Gala <[email protected]>
ioannisg
pushed a commit
that referenced
this issue
Apr 8, 2021
Don't report MTVAL on the OpenISA RV32M1 SoC as this CSR isn't supported on the SoC. Fixes: #34014 Signed-off-by: Kumar Gala <[email protected]>
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Labels
area: RISCV
RISCV Architecture (32-bit & 64-bit)
bug
The issue is a bug, or the PR is fixing a bug
platform: NXP
NXP
priority: low
Low impact/importance bug
Describe the bug
asm volatile("csrr %0, mtval" : "=r" (mtval));
A compile error of assembly code rv32m1-vega board (RISC-V) by using open-isa official toolchain.
The toolchain is https:/open-isa-org/open-isa.org/releases
What have you tried to diagnose or workaround this issue?
Comment the code out
// asm volatile("csrr %0, mtval" : "=r" (mtval));
then no compile error.
To Reproduce
Steps to reproduce the behavior:
+++++++++++++++++++++++++++++++++++
[58/123] Building C object zephyr/arch/arch/riscv/core/CMakeFiles/arch__riscv__core.dir/fatal.c.obj
FAILED: zephyr/arch/arch/riscv/core/CMakeFiles/arch__riscv__core.dir/fatal.c.obj
ccache /opt/toolchain/risc-v/riscv32-unknown-elf-gcc/bin/riscv32-unknown-elf-gcc -DBUILD_VERSION=zephyr-v2.5.0-1954-g5ee6793e57ac -DCPU_RV32M1_ri5cy -DKERNEL -DXCVR_GENFSK_ENABLED -D_FORTIFY_SOURCE=2 -D__ZEPHYR_SUPERVISOR__ -D__ZEPHYR__=1 -I../../../kernel/include -I../../../arch/riscv/include -I../../../include -Izephyr/include/generated -I../../../soc/riscv/openisa_rv32m1 -I/opt/zephyrproject/modules/hal/openisa/vega_sdk_riscv/RISCV -I/opt/zephyrproject/modules/hal/openisa/vega_sdk_riscv/devices/RV32M1 -I/opt/zephyrproject/modules/hal/openisa/vega_sdk_riscv/devices/RV32M1/drivers/. -isystem ../../../lib/libc/minimal/include -isystem /opt/toolchain/risc-v/riscv32-unknown-elf-gcc/bin/../lib/gcc/riscv32-unknown-elf/7.1.1/include -isystem /opt/toolchain/risc-v/riscv32-unknown-elf-gcc/bin/../lib/gcc/riscv32-unknown-elf/7.1.1/include-fixed -Os -imacros /opt/zephyrproject/zephyr/samples/hello_world/build/zephyr/include/generated/autoconf.h -ffreestanding -fno-common -g -mabi=ilp32 -march=rv32ima -imacros /opt/zephyrproject/zephyr/include/toolchain/zephyr_stdint.h -Wall -Wformat -Wformat-security -Wno-format-zero-length -Wno-main -Wno-pointer-sign -Wpointer-arith -Wexpansion-to-defined -Wno-unused-but-set-variable -Werror=implicit-int -fno-asynchronous-unwind-tables -fno-pie -fno-pic -fno-strict-overflow -fno-reorder-functions -fno-defer-pop -ffunction-sections -fdata-sections -march=rv32imcxpulpv2 -std=c99 -nostdinc -MD -MT zephyr/arch/arch/riscv/core/CMakeFiles/arch__riscv__core.dir/fatal.c.obj -MF zephyr/arch/arch/riscv/core/CMakeFiles/arch__riscv__core.dir/fatal.c.obj.d -o zephyr/arch/arch/riscv/core/CMakeFiles/arch__riscv__core.dir/fatal.c.obj -c /opt/zephyrproject/zephyr/arch/riscv/core/fatal.c
/opt/zephyrproject/zephyr/arch/riscv/core/fatal.c: Assembler messages:
/opt/zephyrproject/zephyr/arch/riscv/core/fatal.c:109: Error: Instruction csrr requires absolute expression
[67/123] Building C object zephyr/lib/libc/minim.../lib__libc__minimal.dir/source/stdlib/exit.c.obj
ninja: build stopped: subcommand failed.
+++++++++++++++++++++++++++++++++++
Expected behavior
No compile error.
Impact
Failed to build the code for risc-v
Logs and console output
If applicable, add console logs or other types of debug information
e.g Wireshark capture or Logic analyzer capture (upload in zip archive).
copy-and-paste text and put a code fence (```) before and after, to help
explain the issue. (if unable to obtain text log, add a screenshot)
Environment (please complete the following information):
OS: Linux
Toolchain (https:/open-isa-org/open-isa.org/releases)
Commit:
++++++++++++++++++++++++++++++++++++++++++++++++
Commit 8db3683
Author: Jim Shu [email protected]
Date: Sun Mar 14 02:08:49 2021 +0800
arch: riscv: improve exception messages
Add exception descriptions of mcause id 6~15. Also print mtval CSR for
memory access fault & illegal instruction exceptions.
Signed-off-by: Jim Shu [email protected]
++++++++++++++++++++++++++++++++++++++++++++++++
Additional context
Add any other context about the problem here.
The text was updated successfully, but these errors were encountered: