UART failure with CONFIG_UART_ASYNC_API and DMA #32832
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FRASTM
added
platform: STM32
github-actions
bot
added
the
area: Tests
FRASTM
added
area: UART
dcpleung
reviewed
Mar 3, 2021
dcpleung
requested changes
Mar 10, 2021
drivers/serial/uart_stm32.c
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| /* | ||
| if (data->dma_rx.buffer != event.data.rx.buf) { | ||
| memcpy(event.data.rx.buf, | ||
| data->dma_rx.dma_aligned_buffer, | ||
| data->dma_rx_buffer_len); | ||
| } | ||
| */ |
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Please remove commented out code blocks.
drivers/serial/uart_stm32.c
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| /* | ||
| if (addr_diff == 0 && buf_size >= __SCB_DCACHE_LINE_SIZE) { | ||
| buf_size = UART_STM32_ROUND_DOWN(buf_size); | ||
| } else { | ||
| if (addr_diff != 0) { | ||
| buf_size = MIN(buf_size, addr_diff); | ||
| } | ||
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| buf_size = MIN(buf_size, __SCB_DCACHE_LINE_SIZE); | ||
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| memcpy(data->dma_tx.dma_aligned_buffer, | ||
| data->dma_tx.buffer, buf_size); | ||
| tx_data = data->dma_tx.dma_aligned_buffer; | ||
| } | ||
| */ |
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Remove commented out code block
drivers/serial/uart_stm32.c
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| /* | ||
| if (addr_diff == 0 && buf_size >= __SCB_DCACHE_LINE_SIZE) { | ||
| buf_size = UART_STM32_ROUND_DOWN(buf_size); | ||
| } else { | ||
| if (addr_diff != 0) { | ||
| buf_size = MIN(buf_size, addr_diff); | ||
| } | ||
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| buf_size = MIN(buf_size, __SCB_DCACHE_LINE_SIZE); | ||
| rx_buf = data->dma_rx.dma_aligned_buffer; | ||
| } | ||
| */ |
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Remove commented out code block
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This pull request has been marked as stale because it has been open (more than) 60 days with no activity. Remove the stale label or add a comment saying that you would like to have the label removed otherwise this pull request will automatically be closed in 14 days. Note, that you can always re-open a closed pull request at any time. |
This sets the dts of dma for using the uart 6 asynch api. The stm32f746 has a dma V1 with request 5 for Tx/Rx usart6 The Tx&Rx pins (PG14, PG9) of the usart6 are connected on the nucleo_f746zg board to pass the test Signed-off-by: Francois Ramu <[email protected]>
This sets the dts of dma for using the uart 6 asynch api The stm32f767 has a dma V1 with request 5 for Tx/Rx usart6 The Tx&Rx pins (PG14, PG9) of the usart6 are connected on the nucleo_f767zi board to pass the test Signed-off-by: Francois Ramu <[email protected]>
Remove the cache configuration from the stm32f7 soc, as the core/aarch32/cortex_m inhibits it. Signed-off-by: Francois Ramu <[email protected]>
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initial issue is now closed |
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when enabling the DMA of the stm32f7 soc, especially on the tests/drivers/uart/uart_async_api,
the cache DMA is not coherent.
--> Same approach than the #27911
This PR is to help for fixing of the #31711
This still give an error on the
test_chained_writetest caseSigned-off-by: Francois Ramu [email protected]