drivers: clock_control: stm32g0 soc requires flash latency #34307
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This patch set a flash latency of 1 wait state for the STM32G0 soc devices, as the default value of 0 wait state is not enough to pass some tests cases. Signed-off-by: Francois Ramu <[email protected]>
erwango
requested changes
Apr 15, 2021
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Flash latency is set as part of calls to LL_PLL_ConfigSystemClock_ and LL_SetFlashLatency, which should eventually end up in setting a value of LL_FLASH_LATENCY_2
Forcing a default value overrides previous settings that could be done at these stages and will probably lead to failures in other cases, so I prefer we understand why previous calls failed to set a working value in current case.
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Correct, the nucleo_g071rb has a flash latency of 2 wait-states, as expect, since the hclk is 64MHz (AHBprescaler is 1). However it appears that 1-wait state can make the tests/kernel/timer/timer_api/ test_timeout_abs pass. |
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This WA is no more relevant since the #32839 is now closed |
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This patch set a flash latency of 1 wait state for the STM32G0 soc devices, as the default value of 0 wait state is not enough
to pass some test cases.
It fixes the tests/kernel/fifo/fifo_timeout executed on nucleo_g071rb
Fix #32839
Signed-off-by: Francois Ramu [email protected]